CN111312696B

CN111312696B - Isolation capacitor for improving withstand voltage value of digital isolator chip

Info

Publication number: CN111312696B
Application number: CN201811516650.6A
Authority: CN
Inventors: 丁万新; 史广达; 陶晶晶; 陈东坡
Original assignee: Shanghai Chuantu Microelectronics Co ltd
Current assignee: Shanghai Chuantu Microelectronics Co ltd
Priority date: 2018-12-12
Filing date: 2018-12-12
Publication date: 2022-06-17
Anticipated expiration: 2038-12-12
Also published as: CN111312696A

Abstract

The invention provides an isolation capacitor for improving the withstand voltage value of a digital isolator chip, and relates to the field of digital isolator chipsThe off-capacitor comprises a lower polar plate, an upper polar plate and SiO arranged between the lower polar plate and the upper polar plate in sequence₂A layer and a passivation layer of SiO₂And Si₃N₄The thickness of the passivation layer is 2-3 um, SiO₂The thickness of the layer is 8 ~ 9 um. The invention solves the problem that the withstand voltage value of the capacitor isolator chip in the prior art can not meet the requirement of enhanced isolation withstand voltage.

Description

Isolation capacitor for improving withstand voltage value of digital isolator chip

Technical Field

The invention relates to the field of digital isolator chips, in particular to an isolation capacitor for improving the withstand voltage value of a digital isolator chip.

Background

The existing method for isolating the capacitor isolator chip is mainly to isolate silicon dioxide (SiO) between the capacitor lower polar plate metal and the capacitor upper polar plate metal₂) To realize withstand voltage. Under normal conditions, a lower plate of the isolation capacitor, an upper plate of the isolation capacitor are filled with dense SiO₂By adding SiO₂Such that the isolated capacitor chip is capable of isolating higher voltages.

The working principle of the capacitive isolator chip is shown in fig. 1, a digital signal is input from a VIN pin of the capacitive isolator chip, the frequency of the digital signal is generally DC-150 Mbps, the digital signal is affected by a transmission path and parasitic capacitance to cause the problem of signal quality degradation, for example, the rising edge/falling edge time is prolonged, a schmitt trigger (schmitt trigger) is needed for signal shaping, and a better square wave is obtained; the square wave signal is modulated on a Carrier wave generated by a high-frequency oscillator (RF Carrier general) through an internal Modulator (Modulator), the Modulator (Modulator) is connected with one end of an isolation barrier (isolation barrier) of a capacitive isolator chip, the isolation barrier (isolation barrier) is two capacitors arranged in series, the other end of the isolation barrier (isolation barrier) can also receive a weak signal, the signal is amplified and demodulated through a demodulator (demodulator) to recover an original input signal, the signal increases driving capability through a Driver (Driver), the signal is output from a VOUT pin on the other side of the capacitive isolator chip, and grounding between two chips (Die1 and Die2) in the capacitive isolator chip is separated and independent, so that complete electrical isolation between signal input and signal output is realized.

As shown in FIG. 2, the overall isolation of the capacitive isolator chip is realized by two isolation capacitors (C1 and C2) arranged in series, and the middle is connected with the upper plates of the two isolation capacitors (C1 and C2) through Bonding wires (Bonding wires), so the overall withstand voltage of the capacitive isolator chip is the sum of the withstand voltages of the two capacitors (C1 and C2), usually the withstand voltage of SiO2 is about 500V/um, and the CMOS process of 0.18um is general, as shown in FIG. 3, if M1 is the lower plate of the isolation capacitor and M6 is the upper plate of the isolation capacitor, then the isolation thicknesses of SiO2 are VIA12, M2, VIA23, M3, VIA34, M4, VIA45, M5, VIA56, (M2, M3, M4, M5 are metal layers, VIA12, VIA23, VIA34, VIA 59 56 are also SiO 592 between the metal layers₂Thickness), about 6-7 um, that is to say, the withstand voltage of single isolation capacitor (C1 and C2) is about 3000V-3500V, and the withstand voltage of two isolation capacitors is about 6000V-7000V. The voltage resistance can meet common and conventional applications and cannot meet the voltage resistance requirement of enhanced isolation.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide an isolation capacitor for increasing the voltage endurance of a digital isolator chip, which is used to solve the problem that the voltage endurance of the capacitor isolator chip in the prior art cannot meet the voltage endurance requirement of enhanced isolation.

To achieve the above and other related objects, the present invention provides an isolation capacitor for increasing the withstand voltage of a digital isolator chip, the isolation capacitor comprising a lower plate, an upper plate, and a SiO layer sequentially disposed between the lower plate and the upper plate₂A layer and a passivation layer of SiO₂And Si₃N₄The thickness of the passivation layer is 2-3 um, SiO₂The thickness of the layer is 8 ~ 9 um.

Further, Si of the passivation layer₃N₄Is arranged on SiO in an overlapping way₂And (3) upward.

Furthermore, the upper polar plate is made of metal Cu.

As described above, the isolation capacitor for improving the withstand voltage of the digital isolator chip according to the present invention has the following beneficial effects: in the scheme, the withstand voltage value of the isolation capacitor can be improved, so that the thickness of a single isolation capacitor is about 12um, and the withstand voltage value can reach 6000V, therefore, the total thickness of two isolation capacitors connected in series is about 24um, and the total withstand voltage value can reach 12000V, so that the requirement of enhanced isolation is met.

Drawings

FIG. 1 is a schematic diagram of the operation of a capacitive isolator chip as disclosed in the prior art of the present invention;

FIG. 2 is a schematic diagram of an isolation capacitor connection of a capacitive isolator chip according to the prior art;

FIG. 3 is a schematic diagram of an isolation capacitor disclosed in the prior art;

fig. 4 is a schematic structural diagram of the isolation capacitor disclosed in the embodiment.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the features in the following embodiments and examples may be combined with each other without conflict.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

As shown in fig. 4, the invention provides an isolation capacitor for improving the withstand voltage of a digital isolator chip, which includes a lower plate M1, an upper plate, and a SiO2 layer and a passivation layer sequentially disposed between the lower plate M1 and the upper plate, where the passivation layer is a stack of SiO2 and Si3N 4.

The thickness of the SiO2 layer is mainly VIA12, M2, VIA23, M3, VIA34, M4, VIA45, M5, VIA56 and M6, the sum thickness is 8-9 um, and the thickness of the passivation layer is 2-3 um.

Further, the Si3N4 of the passivation layer is stacked above SiO2, because Si3N4 has better compactness and pressure resistance than SiO 2.

Furthermore, the upper polar plate is made of metal Cu, the substrate of the wafer is arranged below the lower polar plate M1, the upper polar plate is formed by processing the rear end of the wafer, a layer of metal Cu is generated on the passivation layer, and the metal Cu is also used as a PAD PAD at the same time and is convenient to connect with the isolation capacitors which are arranged in parallel.

According to the invention, through process adjustment, the thickness of the passivation layer is controlled to be about 2.5um, the thickness of a single isolation capacitor is about 12um approximately, and the withstand voltage value can reach 6000V, so that the total thickness of two isolation capacitors connected in series is about 24um, the total withstand voltage value can reach 12000V, the requirement of isolation enhancement can be met, the capacitance value of the isolation capacitor is reduced after thickening, the area of an isolation capacitor pole plate can be properly increased, the capacitance value of the isolation capacitor is basically kept unchanged, and the transmission quality of the whole isolation signal is not influenced.

In summary, the invention can improve the voltage withstanding value of the isolation capacitor, so that the thickness of a single isolation capacitor is about 12um, and the voltage withstanding value can reach 6000V, therefore, the total thickness of two isolation capacitors connected in series is about 24um, and the total voltage withstanding value can reach 12000V, thereby satisfying the requirement of enhanced isolation. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. An isolation capacitor for improving the withstand voltage value of a digital isolator chip is characterized in that: the isolation capacitor comprises a lower polar plate, an upper polar plate and SiO sequentially arranged between the lower polar plate and the upper polar plate₂A layer and a passivation layer of SiO₂And Si₃N₄The thickness of the passivation layer is 2-3 um, SiO₂The thickness of the layer is 8-9 um; si of the passivation layer₃N₄Is arranged on SiO in an overlapping way₂An upper part; the upper polar plate is made of metal Cu.