CN111312328B - Method and device for testing embedded flash memory and embedded flash memory chip - Google Patents
Method and device for testing embedded flash memory and embedded flash memory chip Download PDFInfo
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- CN111312328B CN111312328B CN202010210573.2A CN202010210573A CN111312328B CN 111312328 B CN111312328 B CN 111312328B CN 202010210573 A CN202010210573 A CN 202010210573A CN 111312328 B CN111312328 B CN 111312328B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
- G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
- G06F16/21—Design, administration or maintenance of databases
- G06F16/215—Improving data quality; Data cleansing, e.g. de-duplication, removing invalid entries or correcting typographical errors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
Abstract
The application discloses a testing method and testing equipment of an embedded flash memory and an embedded flash memory chip, comprising the following steps: receiving a first instruction; writing target data stored in the flash memory cell array into the cache module according to the first instruction, and erasing the target data from the flash memory cell array; receiving a second instruction; and writing the target data from the cache module back into the flash memory cell array according to the second instruction. According to the application, the target data stored in the flash memory cell array is written into the cache module before the embedded type is baked, the target data is erased from the flash memory cell array, and after the embedded type flash memory chip is baked, the target data is written back into the flash memory cell array from the cache module, and the reading and writing of the target data are performed in the embedded type flash memory chip, so that the speed is high, and the problem that the reading and writing speeds of the target data between the chip and the device are low due to the fact that the target data are backed up in the test device in the related art is solved.
Description
Technical Field
The present application relates to the field of memory device manufacturing technologies, and in particular, to a method and apparatus for testing an embedded flash memory, and an embedded flash memory chip.
Background
An Embedded Flash memory (hereinafter, abbreviated as a "Flash memory") is a non-volatile memory, and is widely used in electronic devices such as mobile phones, digital cameras, tablet computers, etc., because it has the advantages of being able to repeatedly erase, read, write, etc., without losing data even after power is turned off.
Before the embedded flash memory is manufactured and shipped, multiple tests are required to be performed on parameters such as electrical connection performance, power consumption, reading, writing, erasing, crosstalk, data retention capability and the like of the embedded flash memory chip. In the process of testing an embedded flash memory chip, the chip is generally required to be baked to test the data retention capability of the flash memory at a high temperature, for example, after the embedded flash memory chip storing data is baked, the data stored in the baked chip is tested.
However, the depth of data of the embedded flash memory chip after baking is weakened to a certain extent, so that the data stored in the chip after baking is lost to a certain extent. In view of this, a testing method of an embedded flash memory is provided in the related art to solve the problem of data loss of an embedded flash memory chip after baking, which is specifically as follows:
in the testing process of the embedded flash memory chip, the testing equipment stores the data stored in the chip into an address failure storage (Address Failure Memory, AFM) module through a data output port by data reading operation, reads the data in the AFM module into a memory of the testing equipment, and writes the data into a vector generator; after the baking is finished, the data is rewritten into the chip by performing a write operation.
However, the testing method of the embedded flash memory provided in the related art requires a long time to perform the processes of reading and writing data from and into the testing device, and reading and writing back the data from and into the testing device, which reduces the manufacturing efficiency of the embedded flash memory chip.
Disclosure of Invention
The application provides a testing method, testing equipment and an embedded flash memory chip for an embedded flash memory, which can solve the problem of lower manufacturing efficiency caused by longer time consumption of the testing mode of the embedded flash memory provided in the related technology.
In one aspect, an embodiment of the present application provides a method for testing an embedded flash memory, where the method is performed by an embedded flash memory chip, and the embedded flash memory chip includes a flash memory cell array and a cache module, and the method includes:
receiving a first instruction, wherein the first instruction is an instruction sent to the embedded flash memory chip by test equipment before baking the embedded flash memory chip in the process of testing the embedded flash memory chip;
writing target data stored in the flash memory cell array into the cache module according to the first instruction, and erasing the target data from the flash memory cell array;
receiving a second instruction, wherein the second instruction is an instruction sent to the flash memory chip by the test equipment after baking the embedded flash memory chip in the process of testing the embedded flash memory chip;
and writing the target data from the cache module back into the flash memory cell array according to the second instruction.
Optionally, the flash memory chip further includes a built-in Self Test (BIST) module, and the BIST module is configured to establish a communication connection with the Test device when the embedded flash memory chip is tested;
the receiving a first instruction includes:
receiving the first instruction through the BIST module;
the receiving a second instruction includes:
the second instruction is received by the BIST module.
Optionally, the first instruction and the second instruction are test design (Dessign for Testing, DFT) instructions.
Optionally, the buffer module is a page buffer module disposed in the flash memory cell array.
Optionally, the capacity of the cache module is 1 page to 9 pages.
In another aspect, the present application provides a method for testing an embedded flash memory, the method being performed by a test device for testing the embedded flash memory chip, the method comprising:
before baking the embedded flash memory chip in the process of testing the embedded flash memory chip, sending a first instruction, wherein the first instruction is used for enabling the embedded flash memory chip to write target data stored in the flash memory cell array into a cache module according to the first instruction, and erasing the target data from the flash memory cell array;
and after baking the embedded flash memory chip in the process of testing the embedded flash memory chip, sending a second instruction, wherein the second instruction is used for enabling the embedded flash memory chip to write the target data back into the flash memory cell array from the cache module according to the second instruction.
In another aspect, the present application provides an embedded flash memory chip, comprising:
the flash memory unit array is used for writing target data stored in the flash memory unit array into the cache module according to the first instruction after receiving the first instruction, and erasing the target data from the flash memory unit array;
the cache module is used for writing the target data from the cache module back into the flash memory cell array according to the second instruction after receiving the second instruction;
the first instruction is an instruction sent to the embedded flash memory chip by test equipment before baking the embedded flash memory chip in the process of testing the embedded flash memory chip; the second instruction is an instruction sent to the embedded flash memory chip by the testing equipment after baking the embedded flash memory chip in the process of testing the embedded flash memory chip.
Optionally, the embedded flash memory chip further includes a BIST module, where the BIST module is configured to receive the first instruction and the second instruction.
Optionally, the first instruction and the second instruction are DFT instructions.
Optionally, the buffer module is a page buffer module disposed in the flash memory cell array.
Optionally, the capacity of the cache module is 1 page to 9 pages.
In another aspect, the present application provides a test apparatus for testing an embedded flash memory chip, the embedded flash memory chip including a flash memory cell array and a cache module, the apparatus comprising:
the vector generator is used for generating a first instruction before baking the embedded flash memory chip and generating a second instruction after baking the embedded flash memory chip;
the pin circuit is used for enabling the testing equipment to establish communication connection with the embedded flash memory chip through the pin circuit when the embedded flash memory chip is tested, sending the first instruction to the embedded flash memory chip before the embedded flash memory chip is baked, and sending the second instruction after the embedded flash memory chip is baked;
the first instruction is used for enabling the embedded flash memory chip to write target data stored in the flash memory cell array into a cache module according to the first instruction, erasing the target data from the flash memory cell array, and the second instruction is used for enabling the embedded flash memory chip to write the target data back into the flash memory cell array from the cache module according to the second instruction.
Optionally, the first instruction and the second instruction are DFT instructions.
Optionally, the embedded flash memory chip includes a BIST module, and the pin circuit establishes a communication connection with the BIST module when testing the embedded flash memory chip, and sends the first instruction and the second instruction through the BIST module.
In another aspect, the present application provides a test system for an embedded flash memory, including an embedded flash memory chip as described in any one of the embodiments above; and
the test apparatus as described in any of the above embodiments.
The technical scheme of the application at least comprises the following advantages:
before the embedded flash memory chip is baked, target data stored in the flash memory cell array are written into the cache module according to the first instruction, the target data are erased from the flash memory cell array, after the embedded flash memory chip is baked, the target data are written back into the flash memory cell array from the cache module according to the second instruction, and as the reading and writing of the target data are executed in the embedded flash memory chip, the speed is high, so that the problem that the reading and writing speeds of the target data between the chip and the device are low due to the fact that the target data are backed up in the test device in the related art is solved, the test speed of the embedded flash memory chip is improved, and the manufacturing efficiency of the embedded flash memory chip is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a test system for embedded flash memory according to an exemplary embodiment of the present application;
fig. 2 is a flowchart of a method for testing an embedded flash memory according to an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Referring to fig. 1, a schematic diagram of a test system of an embedded flash memory according to an exemplary embodiment of the present application is shown, the system includes a test device 110 and an embedded flash memory chip 120, where the embedded flash memory chip 120 is a chip to be tested.
Test equipment 110 includes a vector generator 111 and a pin circuit 112, with a communication connection between vector generator 111 and pin circuit 112. The vector generator 111 is configured to generate a first instruction before baking the embedded flash memory chip 120 during testing of the embedded flash memory chip 120, and generate a second instruction after baking the embedded flash memory chip 120 during testing of the embedded flash memory chip 120; the pin circuit 112 is configured to, when testing the embedded flash memory chip 120, establish a communication connection between the test device 110 and the embedded flash memory chip 120 through the pin circuit 112, send a first instruction to the embedded flash memory chip 120 before baking the embedded flash memory chip 120, and send a second instruction after baking the embedded flash memory chip 120.
The embedded flash memory chip 120 includes a flash memory cell array 121 and a buffer module 122, and the flash memory cell array 121 and the buffer module 122 are in communication connection. The flash memory cell array 121 is configured to write target data stored in the flash memory cell array 121 into the cache module according to the first instruction after receiving the first instruction, and erase the target data from the flash memory cell array 121; the buffer module 122 is configured to write the target data from the buffer module 122 back to the flash memory cell array 121 according to the second instruction after receiving the second instruction.
Optionally, in this embodiment, the embedded flash memory chip 120 further includes a BIST module 123, the flash memory cell array 112 and the buffer module 122 are respectively in communication connection with the BIST module 123, and when the embedded flash memory chip 120 is tested, a Probe (Probe) of the pin circuit 121 is connected with a data input/output port led out by the BIST module 123, so that the test device 110 and the embedded flash memory chip 120 are in communication connection.
Optionally, in this embodiment, the buffer module 122 is a page buffer module disposed in the flash memory cell array 112; alternatively, the capacity of the buffer module 122 is 1 page to 9 pages.
Optionally, in this embodiment, the first instruction and the second instruction are DFT instructions.
Referring to fig. 2, there is shown a method for testing an embedded flash memory chip according to an exemplary embodiment of the present application, the method being performed by the test system of the embedded flash memory shown in fig. 1, the method comprising:
in step 201, before baking the embedded flash memory chip in the process of testing the embedded flash memory chip, the test device sends a first instruction to the embedded flash memory chip.
In the process of testing the embedded flash memory chip, the test equipment can be connected with a data input/output port led out by the BIST module of the embedded flash memory chip through a probe of the pin circuit, so that the test equipment and the embedded flash memory chip are in communication connection. Before baking the embedded flash memory chip, the test equipment generates a first instruction through the vector generator and sends the first instruction to the embedded flash memory chip through the pin circuit. Optionally, the first instruction is a DFT instruction.
The process of testing the embedded flash memory chip comprises testing the data retention capacity of the embedded flash memory chip.
Step 202, the embedded flash memory chip writes the target data stored in the flash memory cell array into the cache module according to the first instruction, and erases the target data from the flash memory cell array.
The embedded flash memory chip receives a first instruction through the pin circuit, writes target data stored in the flash memory cell array into the cache module according to the first instruction, and erases the target data from the flash memory cell array. Optionally, the buffer module is a page buffer module disposed in the flash memory cell array, and the capacity of the buffer module is 1 page to 9 pages.
Step 203, after baking the embedded flash memory chip in the process of testing the embedded flash memory chip, the testing device sends a second instruction to the embedded flash memory chip.
Illustratively, between step 202 and step 203, the embedded flash memory chip is baked, and after the embedded flash memory chip is baked, the test device generates a second instruction through the vector generator, and sends the second instruction to the embedded flash memory chip through the pin circuit. Optionally, the second instruction is a DFT instruction.
In step 204, the embedded flash memory chip writes the target data back into the flash memory cell array from the cache module according to the second instruction.
The embedded flash memory chip receives a second instruction through the BIST module, and writes the target data back into the flash memory cell array from the cache module according to the second instruction. Optionally, before step 201, after step 204, performance of at least one parameter of electrical connection, power consumption, reading, writing, erasing, and crosstalk of the embedded flash memory chip is tested.
In summary, in the embodiment of the application, before the embedded flash memory chip is baked, the target data stored in the flash memory cell array is written into the cache module according to the first instruction, the target data is erased from the flash memory cell array, after the embedded flash memory chip is baked, the target data is written back into the flash memory cell array from the cache module according to the second instruction, and because the reading and writing of the target data are performed in the embedded flash memory chip, the speed is higher, thus solving the problem that the reading and writing speeds of the target data between the chip and the device are slower due to the fact that the target data are backed up in the test device in the related art, improving the test speed of the embedded flash memory chip and further improving the manufacturing efficiency of the embedded flash memory chip.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.
Claims (15)
1. A method for testing an embedded flash memory, the method being performed by an embedded flash memory chip, the embedded flash memory chip comprising an array of flash memory cells and a cache module, the method comprising:
the method comprises the steps that the flash memory cell array receives a first instruction, wherein the first instruction is an instruction sent by test equipment to the embedded flash memory chip before the embedded flash memory chip is baked in the process of testing the embedded flash memory chip;
the flash memory cell array writes target data stored in the flash memory cell array into the cache module according to the first instruction, and erases the target data from the flash memory cell array;
the cache module receives a second instruction, wherein the second instruction is an instruction sent to the embedded flash memory chip by the test equipment after baking the embedded flash memory chip in the process of testing the embedded flash memory chip;
and the cache module writes the target data back into the flash memory cell array from the cache module according to the second instruction.
2. The method of claim 1, wherein the embedded flash memory chip further comprises a BIST module for establishing a communication connection with the test equipment when the embedded flash memory chip is tested;
the flash memory cell array receives a first instruction, including:
the flash memory cell array receives the first instruction through the BIST module;
the flash memory cell array receives a second instruction, including:
the flash memory cell array receives the second instruction through the BIST module.
3. The method of claim 2, wherein the first instruction and the second instruction are DFT instructions.
4. The method of claim 1, wherein the cache module is a page cache module disposed in an array of flash memory cells.
5. The method of claim 4, wherein the cache module has a capacity of 1 page to 9 pages.
6. A method of testing an embedded flash memory, the method performed by a test device for testing an embedded flash memory chip, the device comprising a vector generator and pin circuitry, the method comprising:
before baking the embedded flash memory chip in the process of testing the embedded flash memory chip, the vector generator generates a first instruction, the pin circuit sends the first instruction, and the first instruction is used for enabling the embedded flash memory chip to write target data stored in a flash memory cell array into a cache module according to the first instruction and erase the target data from the flash memory cell array;
and after the embedded flash memory chip is baked in the process of testing the embedded flash memory chip, the vector generator generates a second instruction, the pin circuit sends the second instruction, and the second instruction is used for enabling the embedded flash memory chip to write the target data back into the flash memory unit array from the cache module according to the second instruction.
7. An embedded flash memory chip, comprising:
the flash memory unit array is used for writing target data stored in the flash memory unit array into the cache module according to the first instruction after receiving the first instruction, and erasing the target data from the flash memory unit array;
the cache module is used for writing the target data from the cache module back into the flash memory cell array according to the second instruction after receiving the second instruction;
the first instruction is an instruction sent to the embedded flash memory chip by test equipment before baking the embedded flash memory chip in the process of testing the embedded flash memory chip; the second instruction is an instruction sent to the embedded flash memory chip by the testing equipment after baking the embedded flash memory chip in the process of testing the embedded flash memory chip.
8. The flash memory chip of claim 7, wherein the embedded flash memory chip further comprises a BIST module for receiving the first instruction and the second instruction.
9. The embedded flash memory chip of claim 8, wherein the first instruction and the second instruction are DFT instructions.
10. The embedded flash memory chip of claim 7, wherein the cache module is a page cache module disposed in an array of flash memory cells.
11. The embedded flash memory chip of claim 9, wherein the cache module has a capacity of 1 page to 9 pages.
12. A test apparatus for testing an embedded flash memory chip, the embedded flash memory chip comprising an array of flash memory cells and a cache module, the apparatus comprising:
the vector generator is used for generating a first instruction before baking the embedded flash memory chip and generating a second instruction after baking the embedded flash memory chip;
the pin circuit is used for enabling the testing equipment to establish communication connection with the embedded flash memory chip through the pin circuit when the embedded flash memory chip is tested, sending the first instruction to the embedded flash memory chip before the embedded flash memory chip is baked, and sending the second instruction after the embedded flash memory chip is baked;
the first instruction is used for enabling the embedded flash memory chip to write target data stored in the flash memory cell array into a cache module according to the first instruction, erasing the target data from the flash memory cell array, and the second instruction is used for enabling the embedded flash memory chip to write the target data back into the flash memory cell array from the cache module according to the second instruction.
13. The test apparatus of claim 12, wherein the first instruction and the second instruction are DFT instructions.
14. The test apparatus of claim 12, wherein the embedded flash memory chip includes a BIST module, the pin circuitry establishing a communication connection with the BIST module through which the first and second instructions are sent when the embedded flash memory chip is tested.
15. A test system for embedded flash memory, comprising the embedded flash memory chip of any one of claims 7 to 11; and
the test device of any one of claims 12 to 14.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010210573.2A CN111312328B (en) | 2020-03-24 | 2020-03-24 | Method and device for testing embedded flash memory and embedded flash memory chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010210573.2A CN111312328B (en) | 2020-03-24 | 2020-03-24 | Method and device for testing embedded flash memory and embedded flash memory chip |
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| CN111312328B true CN111312328B (en) | 2023-10-20 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103824600A (en) * | 2014-03-05 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Memory test method and device |
| CN103839592A (en) * | 2014-03-05 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Built-in self-test method and device for embedded-type flash memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7159145B2 (en) * | 2003-05-12 | 2007-01-02 | Infineon Technologies Ag | Built-in self test system and method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103824600A (en) * | 2014-03-05 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Memory test method and device |
| CN103839592A (en) * | 2014-03-05 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Built-in self-test method and device for embedded-type flash memory |
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