CN111308430A - Direction finding and anti-interference method and system based on FPGA and multi-core DSP hardware architecture - Google Patents

Direction finding and anti-interference method and system based on FPGA and multi-core DSP hardware architecture Download PDF

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CN111308430A
CN111308430A CN202010117758.9A CN202010117758A CN111308430A CN 111308430 A CN111308430 A CN 111308430A CN 202010117758 A CN202010117758 A CN 202010117758A CN 111308430 A CN111308430 A CN 111308430A
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interference
subarray
level
fpga
adaptive
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CN111308430B (en
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陶海红
鲍俊竹
李靖
智开宇
朱晨睿
瞿建
任月
曾操
何学辉
廖桂生
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Xidian University
CETC 54 Research Institute
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/36—Means for anti-jamming, e.g. ECCM, i.e. electronic counter-counter measures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/023—Interference mitigation, e.g. reducing or avoiding non-intentional interference with other HF-transmitters, base station transmitters for mobile communication or other radar systems, e.g. using electro-magnetic interference [EMI] reduction techniques
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S3/00—Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received
    • G01S3/02—Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received using radio waves
    • G01S3/14—Systems for determining direction or deviation from predetermined direction
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/021—Auxiliary means for detecting or identifying radar signals or the like, e.g. radar jamming signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/41—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00 using analysis of echo signal for target characterisation; Target signature; Target cross-section
    • G01S7/414—Discriminating targets with respect to background clutter
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

The invention belongs to the field of radar signal processing, and particularly relates to a direction finding and anti-interference method and system based on an FPGA and multi-core DSP hardware architecture, which are used for acquiring an analog input signal; converting the analog input signal to a digital input signal; carrying out digital down-conversion operation on the digital signal to obtain a baseband signal; carrying out amplitude-phase error correction on the baseband signal to obtain a corrected signal; carrying out subarray synthesis on the corrected signals to obtain M paths of subarray level data, wherein M is larger than 0; processing the plurality of subarray level data to obtain a self-adaptive zero-adaptive conformal anti-interference weight; and weighting the corrected signal according to the self-adaptive zero-adaptive conformal anti-interference weight value to realize interference suppression. The method has the beneficial effect of reducing the time for calculating the direction finding and the anti-interference weight.

Description

Direction finding and anti-interference method and system based on FPGA and multi-core DSP hardware architecture
Technical Field
The invention belongs to the field of radar signal processing, and particularly relates to a direction finding and anti-interference method and system based on an FPGA and multi-core DSP hardware architecture.
Background
The signal processing generally has a very high requirement on real-time performance, and in many cases, when the direction finding of interference and the formation of an adaptive weight are to be completed, many DSPs are often required to cooperate to realize the measurement of a target or an interference direction at the fastest speed. However, signal processing devices are strictly limited in power, heat dissipation, weight, cost and other aspects in many cases, and communication and data transmission efficiency among multiple DSPs is not the highest, so that direction finding of multiple DSPs at the same time is limited in many cases, and direction finding of a target and formation of a self-adaptive anti-interference weight cannot be quickly completed.
The multiple signal classification (MUSIC) algorithm is a symbolic algorithm in a space spectrum estimation theory system, belongs to a typical super-resolution algorithm, and can be used for carrying out direction finding on a target or an interference signal in a space domain. The basic idea is to perform eigen decomposition on the covariance matrix of any array output data to obtain a signal subspace corresponding to the signal component and a noise subspace orthogonal to the signal component, and then to estimate the parameters of the signal using the orthogonality of the two subspaces. Since the MUSIC algorithm needs to scan the search space domain, the calculation amount of the process is huge, and especially under the condition of small scanning interval, a large amount of time is consumed. In engineering, many DSPs are often required to cooperate to achieve the determination of the target or disturbance direction in the shortest time. However, signal processing devices are strictly limited in power, heat dissipation, weight, cost and other aspects in many cases, and communication and data transmission efficiency among multiple DSPs is not the highest, so that direction finding of multiple DSPs at the same time is limited in many cases, and direction finding of a target and formation of a self-adaptive anti-interference weight cannot be quickly completed.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a direction finding and anti-interference method and system based on an FPGA and multi-core DSP hardware architecture. The technical problem to be solved by the invention is realized by the following technical scheme:
the direction finding and anti-interference method based on the FPGA and the multi-core DSP hardware architecture comprises the following steps:
acquiring an analog input signal;
converting the analog input signal to a digital input signal;
carrying out digital down-conversion operation on the digital signal to obtain a baseband signal;
carrying out amplitude-phase error correction on the baseband signal to obtain a corrected signal;
carrying out subarray synthesis on the corrected signals to obtain M paths of subarray level data, wherein M is larger than 0;
processing the plurality of subarray level data to obtain a self-adaptive zero-adaptive conformal anti-interference weight;
and weighting the corrected signal according to the self-adaptive zero-adaptive conformal anti-interference weight value to realize interference suppression.
In an embodiment of the present invention, performing subarray synthesis on the corrected signal to obtain M paths of subarray-level data includes:
and multiplying N array elements corresponding to each of M subarrays in the corrected signal by the beam direction to obtain M paths of subarray-level data, wherein M is larger than 0.
In an embodiment of the present invention, processing the plurality of subarray level data to obtain an adaptive nulling conformal interference rejection weight includes:
presetting a subarray-level scanning guide vector;
carrying out covariance matrix calculation on the M paths of subarray-level data to obtain an M-dimensional covariance matrix;
performing eigenvalue decomposition on the M-dimensional covariance matrix to obtain M eigenvalues and an eigenvector corresponding to each eigenvalue;
obtaining a plurality of large characteristic values according to the M characteristic values;
obtaining the number of interferences according to the large eigenvalues;
obtaining a noise subspace according to the feature vectors corresponding to the large feature values and each feature value;
searching interference signals in a space domain by using a plurality of cores in parallel for the DSP according to the noise subspace and the subarray level scanning guide vector to obtain a plurality of initial interference signals;
judging the initial interference signals to obtain a plurality of interference signals;
obtaining guide vectors of a plurality of subarray-level interference directions according to the plurality of interference signals;
obtaining a constraint matrix according to the guide vectors of the plurality of subarray-level interference directions;
obtaining a steering vector of a subarray level target direction according to the beam direction and the subarray level scanning steering vector;
and obtaining a self-adaptive zero-adaptive conformal anti-interference weight according to the constraint matrix and the guide vector of the subarray level target direction.
Referring to fig. 3, fig. 3 is a schematic diagram of a direction-finding and anti-interference system based on an FPGA and a multi-core DSP hardware architecture according to an embodiment of the present invention, including:
the analog-to-digital converter is used for acquiring an analog input signal and converting the analog input signal into a digital input signal;
referring to fig. 5, fig. 5 is a schematic diagram of a process of an FPGA in a direction-finding and anti-interference system based on the FPGA and a multi-core DSP hardware architecture according to an embodiment of the present invention, where the FPGA is configured to perform digital down-conversion operation on the digital signal to obtain a baseband signal; the device is also used for carrying out amplitude-phase error correction on the baseband signal to obtain a corrected signal; and is used for carrying on the subarray synthesis to the said corrected signal and getting M pieces of subarray level data, M > 0;
the DSP is used for processing the sub-array level data of the plurality of paths to obtain a self-adaptive zero-fitting conformal anti-interference weight;
and after the DSP obtains the self-adaptive zero-preserving anti-interference weight, the FPGA is also used for weighting the corrected signal according to the self-adaptive zero-preserving anti-interference weight to realize interference suppression.
In an embodiment of the present invention, please refer to fig. 4, fig. 4 is a schematic diagram of DSP multi-core parallel spectral peak search of a direction finding and anti-interference system based on an FPGA and a multi-core DSP hardware architecture according to an embodiment of the present invention, where the DSP is specifically configured to pre-store a subarray-level scan guide vector; the M-dimensional covariance matrix calculation module is used for performing covariance matrix calculation on the M paths of subarray-level data to obtain an M-dimensional covariance matrix; the characteristic value decomposition is carried out on the M dimensional covariance matrix to obtain M number of characteristic values and a characteristic vector corresponding to each characteristic value; the M characteristic values are used for obtaining a plurality of large characteristic values; the interference number is obtained according to the large characteristic values; the noise subspace is obtained according to the characteristic vectors corresponding to the large characteristic values and the characteristic values; the system comprises a DSP, a sub-array level scanning guide vector, a noise subspace and a plurality of kernel parallel search channels, wherein the noise subspace and the sub-array level scanning guide vector are used for searching interference signals in a space domain by using a plurality of kernels to obtain a plurality of initial interference signals; the system is used for judging the initial interference signals to obtain a plurality of interference signals; the guiding vectors are used for obtaining a plurality of subarray-level interference directions according to the plurality of interference signals; the constraint matrix is obtained according to the guide vectors of the plurality of subarray-level interference directions; the steering vector used for obtaining the target direction of the subarray level according to the beam direction and the subarray level scanning steering vector; and the adaptive zero-adaptive conformal anti-interference weight value is obtained according to the constraint matrix and the guide vector of the subarray level target direction.
In one embodiment of the invention, the FPGA employs FPGAXC7VX 690T.
In one embodiment of the invention, the DSP adopts an 8-core TMS320C6678 DSP.
The invention has the beneficial effects that:
(1) according to the invention, two-stage weighting is performed in the FPGA, each subarray in the first stage is added with a static weight pointing to a target, the anti-interference weight value obtained by DSP calculation is added in the second stage, the number of channels can be greatly reduced through the first-stage weighting, the signal processing calculation complexity and the calculation amount of the subarray stage are reduced, the direction finding and anti-interference calculation time is reduced, and the static weight pointing to the target is used, so that the target signal gain can be improved, and the performance of the radar can be improved. Interference can be suppressed by the second-stage weighting, and the added weight is an anti-interference weight which is obtained by calculating the subarray-level signal through a self-adaptive algorithm and points to a target direction;
(2) the invention uses 8 cores of the multi-core DSP to simultaneously calculate the covariance matrix, when the row number of the matrix is very large, the time for calculating the covariance matrix of the matrix is large, at the moment, 8 cores are used for calculating the covariance matrix in a blocking way, and a large amount of time can be saved;
(3) before the covariance matrix is calculated, the matrix needs to be subjected to conjugate transposition, a transposition function in a function library is optimized, and complex number conjugate taking is completed while transposition is realized, so that the efficiency of calculating the conjugate transposition matrix is greatly improved, and the time of calculating the covariance matrix is saved;
(4) the 0 core of the multi-core DSP is used for data processing before spectral peak searching and self-adaptive weight calculation after a target interference direction is found, an airspace direction in which a target possibly exists is divided into seven subregions, the rest seven cores are used, each core is responsible for peak value searching of one subregion, the peak value with the same interference number of each subregion is obtained by combining the interference number judged before, the corresponding angle information of the peak value is recorded, a completion signal is sent to the core 0 after the search of each core is completed, the core 0 starts the self-adaptive anti-interference weight calculation after receiving the completion signals of all other seven cores, the process is realized in parallel in one DSP, the calculation efficiency is improved, the engineering application problem caused by using a plurality of DSPs is avoided, and the difficulty in hardware realization is reduced;
(5) in the invention, the noise subspaces of each batch of data are different, but the search guide vectors are the same, so that in order to avoid repeated calculation, after the DSP completes initialization, the subarray-level scan guide vectors are stored in the DDR3, and then when spectrum peak search is carried out, the EDMA is directly used for reading from the DDR3, thereby achieving the purpose of saving time.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic flowchart of a direction-finding and anti-interference method based on an FPGA and multi-core DSP hardware architecture according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of a direction finding and anti-interference method based on an FPGA and multi-core DSP hardware architecture according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a direction-finding and anti-interference system based on an FPGA and multi-core DSP hardware architecture according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of DSP multi-core parallel spectral peak search of a direction finding and anti-interference system based on an FPGA and a multi-core DSP hardware architecture according to an embodiment of the present invention;
fig. 5 is a schematic process diagram of an FPGA in the direction-finding and anti-interference system based on the FPGA and the multi-core DSP hardware architecture according to the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Referring to fig. 1, fig. 1 is a schematic flow chart of a direction finding and anti-interference method based on an FPGA and a multi-core DSP hardware architecture according to an embodiment of the present invention, where the direction finding and anti-interference method based on the FPGA and the multi-core DSP hardware architecture includes:
acquiring an analog input signal;
converting the analog input signal to a digital input signal;
carrying out digital down-conversion operation on the digital signal to obtain a baseband signal;
carrying out amplitude-phase error correction on the baseband signal to obtain a corrected signal;
specifically, each array element correction coefficient y adopted in correction2，…，yN，…，yM×Ny2，…，yN，…，yM×NPre-calculated and stored in the FPGA memory.
The corrected signals are subjected to subarray synthesis through static weights W (1,1), W (1,2), …, W (1, N), …, W (M,1), W (M,2), … and W (M, N) of all subarrays pointing to the target direction to obtain M paths of subarray level data, M is larger than 0, and the static weights can be obtained through precalculation and stored;
processing the plurality of subarray level data to obtain a self-adaptive zero-adaptive conformal anti-interference weight;
and weighting the corrected signal according to the self-adaptive zero-adaptive conformal anti-interference weight value to realize interference suppression.
Referring to fig. 2, fig. 2 is a schematic diagram of a specific flow of a direction-finding and anti-interference method based on an FPGA and a multi-core DSP hardware architecture according to an embodiment of the present invention, where two-stage weighting is performed in the FPGA, each subarray of a first stage is added with a static weight pointing to a target, and an anti-interference weight obtained by DSP calculation is added to a second stage, so that the number of channels can be greatly reduced by the first stage weighting, the calculation complexity and the amount of operation are reduced, and the direction-finding and anti-interference time is reduced, and the second stage weighting can suppress interference by using the calculated anti-interference weight; the invention uses 8 cores of the multi-core DSP to simultaneously calculate the covariance matrix, when the row number of the matrix is very large, the time for calculating the covariance matrix of the matrix is large, at the moment, 8 cores are used for calculating the covariance matrix in a blocking way, and a large amount of time can be saved; before the covariance matrix is calculated, the matrix needs to be subjected to conjugate transposition, a transposition function in a function library is optimized, and complex number conjugate taking is completed while transposition is realized, so that the efficiency of calculating the conjugate transposition matrix is greatly improved, and the time of calculating the covariance matrix is saved; the 0 core of the multi-core DSP is used for data processing before spectral peak searching and self-adaptive weight generation after a target interference direction is found, an airspace direction in which a target possibly exists is divided into seven subregions, the rest seven cores are used, each core is responsible for peak value searching of one subregion, the peak value with the same number as the interference number of each subregion is obtained by combining the interference number judged before, angle information corresponding to the peak value is recorded, a completion signal is sent to the core 0 after the search of each core is completed, and the calculation of the self-adaptive anti-interference weight is started after the core 0 receives the completion signals of all other seven cores; in the invention, the noise subspace of each batch of Data is different, but the search guide vectors are the same, so that in order to avoid repeated calculation, after the DSP finishes initialization, the subarray-level scan guide vectors are stored in a DDR3 SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory, third-generation Double-Data-Rate Synchronous Dynamic Random Access Memory), and then when spectrum peak search is carried out, EDMA (Enhanced direct Memory Access) is directly used for reading from the DDR3 SDRAM, thereby achieving the purpose of saving time.
In an embodiment of the present invention, performing subarray synthesis on the corrected signal to obtain M paths of subarray-level data includes:
and multiplying N array elements corresponding to each of M subarrays in the corrected signal by the beam direction to obtain M paths of subarray-level data, wherein M is larger than 0.
Specifically, the corrected signal has M subarrays, each subarray has N array elements, and at this time, M × N paths of data are shared; and multiplying the array element data of the M sub-arrays by the beam direction to realize sub-array synthesis, and reducing the original M paths of the data to M paths. Therefore, on the premise of ensuring the accuracy of the interference direction finding and the anti-interference effect, the calculation complexity is reduced, the calculation amount is reduced, and the interference direction finding and the anti-interference weight value obtaining can be realized in a shorter time.
In an embodiment of the present invention, processing the plurality of subarray level data to obtain an adaptive nulling conformal interference rejection weight includes:
presetting a subarray-level scanning guide vector;
specifically, the DDR3 SDRAM of the DSP is initialized, and then the pre-calculated corresponding steering vectors of the incident signals at various angles on the array are stored in the DDR3 SDRAM as the sub-array level SCAN steering vector array SCAN _ steer.
Carrying out covariance matrix calculation on the M paths of subarray-level data to obtain an M-dimensional covariance matrix;
specifically, after the FPGA completes preprocessing of received signal data, M-path sub-array level data, that is, an array X is obtained, the array X is transmitted to a shared Memory MSRAM (Static Random Access Memory) of the TMS320C6678 via SRIO (Serial Rapid I/O), and the FPGA notifies the DSP that the received data can be processed.
Further, after the DSP obtains signals of the FPGA, 8 cores of the DSP divide the received M paths of sub-matrix level data X into blocks and perform covariance matrix calculation, and the matrix X is divided into 8 sub-matrixes (X) according to rows1，X2，X3，X4，X5，X6，X7，X8) Each core undertakes multiplication calculation of a submatrix and a matrix X, and the calculation result of each core is stored in RxxCorresponding to the position to finally obtain an M-dimensional covariance matrix R of the matrix Xxx。
Performing eigenvalue decomposition on the M-dimensional covariance matrix to obtain M eigenvalues and an eigenvector corresponding to each eigenvalue;
obtaining a plurality of large characteristic values according to the M characteristic values;
obtaining the number of interferences according to the large eigenvalues;
obtaining a noise subspace according to the feature vectors corresponding to the large feature values and each feature value;
specifically, the kernel 0 of the DSP performs eigenvalue decomposition on the M-dimensional covariance matrix to obtain eigenvalues of the same number as the number of matrix dimensions and eigenvectors corresponding to each eigenvalue, and since the interference signals are significantly stronger than the target signals and noise, the number of the interference signals will be the same as the number of the interference signalsThe same large eigenvalue, so the number Num _ jam of the interference can be judged according to the number of the large eigenvalue, and the noise subspace Un can be obtained by omitting the eigenvector corresponding to the large eigenvalue; computing
Figure BDA0002392015910000091
Storing into shared memory [ ]]HIs a complex conjugate transpose.
Searching interference signals in a space domain by using a plurality of cores in parallel for the DSP according to the noise subspace and the subarray level scanning guide vector to obtain a plurality of initial interference signals;
specifically, the spatial domain range to be searched is averagely divided into seven parts, each core is responsible for one spatial domain part except for 0 core, spectral peak search is carried out, a subarray-level scanning guide vector required when each core carries out the spectral peak search is transmitted to an L2D memory of each core from DDR3 by EDMA respectively, and the search is carried out according to a formula
Figure BDA0002392015910000101
Calculating the spatial spectrum function value P of each anglemusicA spatial spectrum is obtained.
Judging the initial interference signals to obtain a plurality of interference signals; searching a current core for searching a spectral peak value of an airspace, wherein each core stores the spectral peak values with the same number as the interference number Num _ jam and a pitch angle and an azimuth angle corresponding to the spectral peak values in a shared memory, and stores the pitch angle and the azimuth angle as a matrix Result _ core; the number of rows of the matrix Result _ core is the number of interference Num _ jam multiplied by 7, the number of columns is 3, the first column stores a spectrum peak value, and the second column and the third column respectively store a corresponding pitch angle and an azimuth angle.
Judging the initial interference signals to obtain a plurality of interference signals;
specifically, after each core finishes scanning the space domain in charge of, sending a scanning completion notification to the core 0 through semaphore (semaphore), after the core 0 receives the notifications of all seven cores, sorting the matrix Result _ core stored in the shared memory by each core in the core 0 according to the size of the first column of spectral peak values of the matrix Result _ core, so as to obtain spectral peak values the same as the interference number Num _ jam, wherein the Num _ jam large spectral peak values correspond to the large spectral peak valuesThe angle information of (a) is the angle information of the interference, which can be expressed as
Figure BDA0002392015910000102
Figure BDA0002392015910000103
Obtaining guide vectors of a plurality of subarray-level interference directions according to the plurality of interference signals;
obtaining a constraint matrix according to the guide vectors of the plurality of subarray-level interference directions;
in particular, based on interference signal angle information
Figure BDA0002392015910000104
Figure BDA0002392015910000105
EDMA (Enhanced Direct Memory Access) transmits a guide vector corresponding to each interference from DDR3 SDRAM to an L2D Memory of a core 0 to form a constraint matrix C; constraint matrix C is then used among cores 0.
Obtaining a steering vector of a subarray level target direction according to the beam direction and the subarray level scanning steering vector;
and obtaining a self-adaptive zero-adaptive conformal anti-interference weight according to the constraint matrix and the guide vector of the subarray level target direction.
In particular, the formula P ═ I-C (C) is combinedHC)-1CHObtaining a projection matrix P, and obtaining a projection matrix P according to a formula Wopt ═ PwdObtaining an adaptive zero-adaptive conformal anti-interference weight Wopt, wherein wdWopt is a column vector consisting of M complex numbers as the desired weight vector; in addition, when the core 0 calculates the adaptive weight, other cores can perform interference direction finding on a new batch of received data, and 8 cores of the multi-core DSP are closely matched, so that the efficiency is highest.
The invention also provides a direction finding and anti-interference system based on the FPGA and multi-core DSP hardware architecture, which comprises:
the analog-to-digital converter is used for acquiring an analog input signal and converting the analog input signal into a digital input signal;
the FPGA is used for carrying out digital down-conversion operation on the digital signal to obtain a baseband signal; the device is also used for carrying out amplitude-phase error correction on the baseband signal to obtain a corrected signal; and is used for carrying on the subarray synthesis to the said corrected signal and getting M pieces of subarray level data, M > 0;
the DSP is used for processing the sub-array level data of the plurality of paths to obtain a self-adaptive zero-fitting conformal anti-interference weight;
and after the DSP obtains the self-adaptive zero-preserving anti-interference weight, the FPGA is also used for weighting the corrected signal according to the self-adaptive zero-preserving anti-interference weight to realize interference suppression.
Further, in order to enhance the real-time performance of signal processing and improve the signal processing efficiency, the high-resolution direction finding method of the invention adopts the following technologies: firstly, two-stage weighting is carried out in an FPGA, each subarray of the first stage is added with a static weight pointing to a target, the adaptive zero-adaptive conformal anti-interference weight obtained by DSP calculation is added to the second stage, the number of channels can be greatly reduced through the first stage weighting, the calculation complexity and the calculation amount are reduced, the direction finding and anti-interference time is reduced, and the second stage weighting can realize the suppression of interference by using the anti-interference weight obtained by calculation. Secondly, 8 cores of the multi-core DSP are used for simultaneously calculating the covariance matrix, when the row number of the matrix is very large, a large amount of time is needed for calculating the covariance matrix of the matrix, and at the moment, 8 cores are used for calculating the covariance matrix in a blocking mode, so that a large amount of time can be saved. Thirdly, before the covariance matrix is calculated, the matrix needs to be subjected to conjugate transpose, a transpose function in a function base is optimized, and complex number conjugate taking is completed while transpose is achieved, so that the efficiency of calculating the conjugate transpose matrix is greatly improved, and the time of calculating the covariance matrix is saved. Fourthly, the 0 core of the multi-core DSP is used for data processing before spectral peak searching and adaptive weight generation after a target interference direction is found, the airspace direction in which the target possibly exists is divided into seven subregions, the rest seven cores are used, each core is responsible for peak value searching of one subregion, the peak value of each subregion, which is the same as the interference number, is obtained by combining the interference number judged before, the corresponding angle of the peak value is recorded, a completion signal is sent to the core 0 after the searching of each core is completed, and the calculation of the adaptive anti-interference weight is started after the core 0 receives the completion signals of all the other seven cores. Fifthly, the noise subspaces of each batch of data are different, but the search guide vectors are the same, in order to avoid repeated calculation, after the DSP completes initialization, the subarray level scan guide vectors are stored in the DDR3, and then when spectral peak search is carried out, the EDMA is directly used for reading from the DDR3, so that the purpose of saving time is achieved. After the interference direction is determined, when the core 0 calculates the interference resistance weight, the FPGA can send a new batch of data to the DSP.
In an embodiment of the present invention, the DSP is specifically configured to pre-store a subarray-level scan guidance vector; the M-dimensional covariance matrix calculation module is used for performing covariance matrix calculation on the M paths of subarray-level data to obtain an M-dimensional covariance matrix; the characteristic value decomposition is carried out on the M dimensional covariance matrix to obtain M number of characteristic values and a characteristic vector corresponding to each characteristic value; the M characteristic values are used for obtaining a plurality of large characteristic values; the interference number is obtained according to the large characteristic values; the noise subspace is obtained according to the characteristic vectors corresponding to the large characteristic values and the characteristic values; the system comprises a DSP, a sub-array level scanning guide vector, a noise subspace and a plurality of kernel parallel search channels, wherein the noise subspace and the sub-array level scanning guide vector are used for searching interference signals in a space domain by using a plurality of kernels to obtain a plurality of initial interference signals; the system is used for judging the initial interference signals to obtain a plurality of interference signals; the guiding vectors are used for obtaining a plurality of subarray-level interference directions according to the plurality of interference signals; the constraint matrix is obtained according to the guide vectors of the plurality of subarray-level interference directions; the steering vector used for obtaining the target direction of the subarray level according to the beam direction and the subarray level scanning steering vector; and the adaptive zero-adaptive conformal anti-interference weight value is obtained according to the constraint matrix and the guide vector of the subarray level target direction.
In one embodiment of the invention, the FPGA employs FPGAXC7VX 690T.
In one embodiment of the invention, the DSP adopts an 8-core TMS320C6678 DSP.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (7)

1. A direction finding and anti-interference method based on FPGA and multi-core DSP hardware architecture is characterized by comprising the following steps:
acquiring an analog input signal;
converting the analog input signal to a digital input signal;
carrying out digital down-conversion operation on the digital signal to obtain a baseband signal;
carrying out amplitude-phase error correction on the baseband signal to obtain a corrected signal;
carrying out subarray synthesis on the corrected signals to obtain M paths of subarray level data, wherein M is larger than 0;
processing the plurality of subarray level data to obtain a self-adaptive zero-adaptive conformal anti-interference weight;
and weighting the corrected signal according to the self-adaptive zero-adaptive conformal anti-interference weight value to realize interference suppression.
2. The direction-finding and anti-interference method based on the FPGA and multi-core DSP hardware architecture according to claim 1, wherein the obtaining of M-path subarray-level data by subarray synthesis of the corrected signals comprises:
and multiplying N array elements corresponding to each of M subarrays in the corrected signal by the beam direction to obtain M paths of subarray-level data, wherein M is larger than 0.
3. The direction-finding and anti-jamming method based on FPGA and multi-core DSP hardware architecture of claim 1, wherein processing the plurality of subarray level data to obtain adaptive null-steering conformal anti-jamming weights comprises:
presetting a subarray-level scanning guide vector;
carrying out covariance matrix calculation on the M paths of subarray-level data to obtain an M-dimensional covariance matrix;
performing eigenvalue decomposition on the M-dimensional covariance matrix to obtain M eigenvalues and an eigenvector corresponding to each eigenvalue;
obtaining a plurality of large characteristic values according to the M characteristic values;
obtaining the number of interferences according to the large eigenvalues;
obtaining a noise subspace according to the feature vectors corresponding to the large feature values and each feature value;
searching interference signals in a space domain by using a plurality of cores in parallel for the DSP according to the noise subspace and the subarray level scanning guide vector to obtain a plurality of initial interference signals;
judging the initial interference signals to obtain a plurality of interference signals;
obtaining guide vectors of a plurality of subarray-level interference directions according to the plurality of interference signals;
obtaining a constraint matrix according to the guide vectors of the plurality of subarray-level interference directions;
obtaining a steering vector of a subarray level target direction according to the beam direction and the subarray level scanning steering vector;
and obtaining a self-adaptive zero-adaptive conformal anti-interference weight according to the constraint matrix and the guide vector of the subarray level target direction.
4. Direction finding and anti-interference system based on FPGA and multicore DSP hardware architecture, its characterized in that includes:
the analog-to-digital converter is used for acquiring an analog input signal and converting the analog input signal into a digital input signal;
the FPGA is used for carrying out digital down-conversion operation on the digital signal to obtain a baseband signal; the device is also used for carrying out amplitude-phase error correction on the baseband signal to obtain a corrected signal; and is used for carrying on the subarray synthesis to the said corrected signal and getting M pieces of subarray level data, M > 0;
the DSP is used for processing the sub-array level data of the plurality of paths to obtain a self-adaptive zero-fitting conformal anti-interference weight;
and after the DSP obtains the self-adaptive zero-preserving anti-interference weight, the FPGA is also used for weighting the corrected signal according to the self-adaptive zero-preserving anti-interference weight to realize interference suppression.
5. The direction-finding and anti-interference system based on the FPGA and multi-core DSP hardware architecture as claimed in claim 4, wherein the DSP is specifically configured to pre-store subarray-level scan steering vectors; the M-dimensional covariance matrix calculation module is used for performing covariance matrix calculation on the M paths of subarray-level data to obtain an M-dimensional covariance matrix; the characteristic value decomposition is carried out on the M dimensional covariance matrix to obtain M number of characteristic values and a characteristic vector corresponding to each characteristic value; the M characteristic values are used for obtaining a plurality of large characteristic values; the interference number is obtained according to the large characteristic values; the noise subspace is obtained according to the characteristic vectors corresponding to the large characteristic values and the characteristic values; the system comprises a DSP, a sub-array level scanning guide vector, a noise subspace and a plurality of kernel parallel search channels, wherein the noise subspace and the sub-array level scanning guide vector are used for searching interference signals in a space domain by using a plurality of kernels to obtain a plurality of initial interference signals; the system is used for judging the initial interference signals to obtain a plurality of interference signals; the guiding vectors are used for obtaining a plurality of subarray-level interference directions according to the plurality of interference signals; the constraint matrix is obtained according to the guide vectors of the plurality of subarray-level interference directions; the steering vector used for obtaining the target direction of the subarray level according to the beam direction and the subarray level scanning steering vector; and the adaptive zero-adaptive conformal anti-interference weight value is obtained according to the constraint matrix and the guide vector of the subarray level target direction.
6. The direction-finding and interference rejection system based on FPGA and multi-core DSP hardware architecture according to claim 4, wherein the FPGA employs FPGAXC7VX 690T.
7. The direction-finding and anti-interference system based on the FPGA and multi-core DSP hardware architecture of claim 4, wherein the DSP employs an 8-core TMS320C6678 DSP.
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