CN111294085B

CN111294085B - Implementation method using UTP on 2D5 or 5Gbase-T1

Info

Publication number: CN111294085B
Application number: CN202010043394.4A
Authority: CN
Inventors: 谢海春; 杨梁
Original assignee: Tianjin Ronghui Microelectronics Technology Co ltd
Current assignee: Tianjin Ronghui Microelectronics Technology Co ltd
Priority date: 2020-01-15
Filing date: 2020-01-15
Publication date: 2021-06-18
Anticipated expiration: 2040-01-15
Also published as: CN111294085A

Abstract

The invention discloses a realization method for using UTP on 2D5 or 5Gbase-T1, which comprises a multi-core artificial intelligence automatic driving processor, a structural driving instruction heterogeneous processor with a 5G base band, a TSN exchange processor, a main ECCUs module, a power supply, a radar, a camera, two PoDL modules and a plurality of 2D5G/5Gbase-T1 double-engine PHY modules, wherein the multi-core artificial intelligence automatic driving processor is electrically connected with the structural driving instruction heterogeneous processor with the 5G base band, and the multi-core artificial intelligence automatic driving processor is electrically connected with the plurality of 2D5G/5Gbase-T1 double-engine PHY modules. The power consumption of the invention is far lower than that of the common IEEE802.3ch Ethernet PHY, the heat dissipation and ESD cost can be greatly reduced, the UTP non-shielding wire can be used for achieving the purpose of transmitting to 5Gbps, the design difficulty can be reduced, the production cost and the maintenance cost can be greatly reduced, the invention is suitable for the data transmission of the laser radar and the camera of automatic driving, and the data and the electric energy can be transmitted simultaneously.

Description

Implementation method using UTP on 2D5 or 5Gbase-T1

Technical Field

The invention relates to the technical field of automatic driving of automobiles, in particular to a method for realizing UTP (unified transport protocol) on 2D5 or 5 Gbase-T1.

Background

Various wire cables are arranged on the automobile, one cable can reach more than 1500 meters, and the defects caused by various cables can be increased by 2-3 times along with the increase of advanced driving assistance and automatic driving:

1. custom connectors bring high development and production costs;

2. the structure layout is difficult and can not be standardized;

3. weight (the protected cable accounts for 20-30% of the vehicle weight);

therefore, the IEEE introduced the vehicle ethernet, and many international manufacturers follow the vehicle ethernet, and recognize that the vehicle ethernet is the core of the next generation of automobile data network due to the data processing problem of the automatic driving.

IEEE has established a series of transceiver standards for cable problems, where data is transmitted and received simultaneously over a pair of twisted pairs, as follows:

1. ieee802.cg:10 base-T1, namely, implementing simultaneous transmission and reception of 10M data on a pair of unshielded twisted pairs;

2. the IEEE802.3bw is 100Baset-T1, namely 100M data is simultaneously transmitted and received on a pair of unshielded twisted pair wires;

3. 1000Baset-T1, namely simultaneously transmitting and receiving 1000M data on a pair of unshielded twisted pair wires;

4. IEEE802.3cg 2D5/5/10Gbase-T1, namely, the simultaneous transmission and reception of 2D5/5/10G data is realized on a pair of shielded twisted pairs.

In automotive cables, from the standpoint of production costs and maintenance costs: unshielded line < optical cable < shielded line, from the structural design difficulty: unshielded wire < fiber optic cable < shielded wire, in short, shielded wire is not desired to be applied on the car; in order to save cables, the vehicle uses the PoDL to transmit electricity, the PoDL multiplexes electricity and data signals onto a pair of twisted pairs, and the production cost and maintenance cost of the shielded wires are much higher than those of the optical cables.

At present, the only chipset capable of transmitting 2D5Gb ethernet through a single Unshielded Twisted Pair (UTP) with almost zero delay is provided, but the design difficulty is high, the maintenance cost and the production cost are high, how to reduce the design difficulty and greatly reduce the production cost and the maintenance cost is a problem to be solved urgently, so an implementation method using the UTP on 2D5 or 5Gbase-T1 is designed to solve the above problems.

Disclosure of Invention

The invention aims to solve the defects in the prior art and provides a realization method for using UTP on 2D5 or 5 Gbase-T1.

In order to achieve the purpose, the invention adopts the following technical scheme:

the realization method of UTP used on 2D5 or 5Gbase-T1 comprises a multi-core artificial intelligence automatic driving processor, a structural driving instruction heterogeneous processor with a 5G baseband, a TSN exchange processor, a main ECCUs module, a power supply, a radar and a camera, two PoDL modules and a plurality of 2D5G/5Gbase-T1 double-engine PHY modules, wherein the multi-core artificial intelligence automatic driving processor is electrically connected with the structural driving instruction heterogeneous processor with the 5G baseband, the multi-core artificial intelligence automatic driving processor is electrically connected with the plurality of 2D5G/5Gbase-T1 double-engine PHY modules, the two 2D5G/5Gbase-T1 double-engine PHY modules are respectively electrically connected with the two PoDL modules, the two PoDL modules are electrically connected with the radar and the camera, the power supply is electrically connected with the two PoDL modules, the structured running command heterogeneous processor with the 5G baseband is electrically connected with the TSN exchange processor, and the TSN exchange processor is electrically connected with the main ECCUs module.

Preferably, the multi-core artificial intelligence automatic driving processor is connected with 2D5G/5Gbase-T1 double-engine PHY module and the structured driving instruction heterogeneous processor with 5G baseband through 2D5G/5GSERDES links, and the structured driving instruction heterogeneous processor with 5G baseband is connected with the TSN exchange processor through 2D5G/5GSERDES links.

Preferably, the 2D5G/5Gbase-T1 dual-engine PHY module is connected with the PoDL module through a 2D5G/5Gbase-T1 plate link.

Preferably, two PoDL modules are connected with the radar and the camera through a 2D5G/5Gbase-T1 external link.

Preferably, the TSN switch processor is connected to a 1000base-T1 external link between the master ECCUs module.

Preferably, the multi-core artificial intelligence autopilot processor comprises a 2D5/5G MAC module, the 2D5/5G MAC module comprises a data sending time management main controller, an MAC sending module, an MAC receiving module, a buffer module with a time trigger, a time control protocol configuration eavesdropping module, a receiving timestamp learning module, a 2D5/5G MII interface and a 2D5/5G SERDES module, and the 2D5/5G SERDES module is connected with the PoDL module through a 1000base-T1 external link.

Preferably, the data sending time management main controller is electrically connected with the MAC sending module, the MAC sending module is electrically connected with the 2D5/5G MII interface and the 2D5/5GSERDES module, the 2D5/5G MII interface and the 2D5/5GSERDES module are electrically connected with the MAC receiving module, and the MAC receiving module is electrically connected with the data sending time management main controller.

Preferably, the data sending time management main controller is electrically connected with the receiving timestamp learning module with the time trigger sending buffer module, the sending buffer module with the time trigger sending buffer module is electrically connected with the MAC sending module, the AC sending module is electrically connected with the 2D5/5G MII interface and the 2D5/5G 3 rs module, the 2D5/5G MII interface and the 2D5/5G 5 s are electrically connected with the MAC receiving module, the MAC receiving module is electrically connected with the receiving timestamp learning module, the receiving timestamp learning module is electrically connected with the sending buffer module with the time trigger sending buffer module, and the time control protocol configuration eavesdropping module is electrically connected with the sending buffer module with the time trigger sending buffer module and is in bidirectional communication.

Compared with the prior art, the invention has the beneficial effects that:

the power consumption of the invention is far lower than that of the common IEEE802.3ch Ethernet PHY, the heat dissipation and ESD cost can be greatly reduced, the UTP non-shielding wire can be used for achieving the purpose of transmitting to 5Gbps, the design difficulty can be reduced, the production cost and the maintenance cost can be greatly reduced, the invention is suitable for the data transmission of the laser radar and the camera of automatic driving, and the data and the electric energy can be transmitted simultaneously.

Drawings

FIG. 1 is a schematic diagram of the structure of an automatically driven ECCU using UTP implementation on 2D5 or 5Gbase-T1 according to the present invention;

FIG. 2 is a diagram of data transmission before modification of the proposed implementation of UTP over 2D5 or 5 Gbase-T1;

FIG. 3 is a diagram of a data transmission modified by the UTP implementation method proposed in the present invention on 2D5 or 5 Gbase-T1;

FIG. 4 is a block diagram of an embodiment of the present invention before modification of the proposed implementation method using UTP on 2D5 or 5 Gbase-T1;

FIG. 5 is a block diagram of a modified embodiment of the proposed implementation of UTP on 2D5 or 5 Gbase-T1;

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.

Referring to fig. 1-5, the method for implementing UTP on 2D5 or 5Gbase-T1 includes a multi-core artificial intelligence autopilot processor, a structured driving instruction heterogeneous processor with a 5G baseband, a TSN switching processor, a main ECCUs module, a power supply, a radar, a camera, two PoDL modules, and a plurality of 2D5G/5Gbase-T1 dual-engine PHY modules, where the multi-core artificial intelligence autopilot processor is electrically connected to the structured driving instruction heterogeneous processor with the 5G baseband, and the multi-core artificial intelligence autopilot processor is connected to the 2D5G/5Gbase-T1 dual-engine PHY module and the structured driving instruction heterogeneous processor with the 5G baseband, and the structured driving instruction heterogeneous processor with the 5G baseband and the tsdes switching processor by 2D5G/5 gserlink links.

The multi-core artificial intelligence automatic driving processor is electrically connected with the 2D5G/5Gbase-T1 double-engine PHY modules, wherein the two 2D5G/5Gbase-T1 double-engine PHY modules are respectively electrically connected with the two PoDL modules, and the 2D5G/5Gbase-T1 double-engine PHY modules are connected with the PoDL modules through 2D5G/5Gbase-T1 plate links.

The two PoDL modules are electrically connected with the radar and the camera, and are connected with the radar and the camera through a 2D5G/5Gbase-T1 external link. The radar is a laser radar.

The power supply is electrically connected with the two PoDL modules, the structured running command heterogeneous processor with the 5G baseband is electrically connected with the TSN exchange processor, the TSN exchange processor is electrically connected with the main ECCUs module, the number of the main ECCUs modules is at least two, and the TSN exchange processor is connected with the main ECCUs module through a 1000base-T1 external link; ECCU (electronic central control Unit) in the vehicle only needs 2/4G bandwidth for the laser radar and the camera of automatic driving, and the requirement of adopting gigabit link between other ECCUs is satisfied.

As shown in fig. 2, for the camera, most of the data is downlink data with a particularly large amount and uplink data with a very small amount, the downlink data follows RTP or similar time control protocol and is relatively regular, and the uplink data is sent at irregular time, so that superposition is inevitable.

Because of the ieee802.3ch regulation, transmission and reception are performed simultaneously, which is the biggest technical difficulty of ieee802.3ch, it is necessary to superimpose the transmission data and the reception data, and the superimposed data must be "subtracted" from the transmitted data at the receiving end, which may result in:

1. this necessitates the use of a large number of equalizers using an ieee802.3ch compliant ethernet PHY; this makes the power consumption for supporting 802.3ch very high, and the temperature rise brings about a large heat dissipation and ESD cost.

2. The transmitted and received data may cross-talk with each other, making the equalization algorithm more complex and the SNR may be relatively poor.

Because of the characteristics of the camera and the laser radar in data transmission, in addition to the ieee802.3ch standard supported by the multi-core artificial intelligent automatic driving processor, a data model is established to solve the purposes that the external circuit transmission is long and UTP (unshielded twisted pair) can be used, wherein the downlink data is up to 2Gbps or 4Gbps, and the actual transmission rate is 2D5Gbps/4Gbps, and because the camera and the radar both comply with time protocol (such as RTP) data, a gap must be formed between a data packet and a data packet, as shown in fig. 3; in the application of a camera or a laser radar which mainly uses unilateral flow; in addition to supporting standard ieee802.3ch, a transmit-transmit non-overlap mode is enabled, which results in very high SNR and turns off many digital equalizers, achieving transmission over UTP to distances of around 15 meters with low power consumption.

For this reason, the following assumptions are made:

1. the flow of the quantity of the downlink data is less than 80% of the maximum flow of the communication channel;

2. the downlink data follows RTP protocol or time control protocol with similar function, and is sent according to the specified length of the timestamp (the length of the data packet is consistent), so that enough gaps are ensured;

3. the amount of upstream data is very small and if there is no configuration or signaling data in the gap, one heartbeat data is sent. The heartbeat, configuration and signaling time contains time stamps and can be used for end-to-end time pairing (IEEE1588V 2);

4. inserting an uplink data interval between downlink transmission data;

5. the uplink data and the downlink data have enough interval, and oscillation and reflection signals do not influence the SNR of the data.

The receiving and sending equalizer is designed in Ethernet PHY of IEEE802.3ch, and a logic switch is designed, so that some equalizers can be closed or simpler equalizers can be used; in the 2D5/5G MAC of the camera or the laser radar opposite end (the multi-core manual automatic driving processor in the above figure), the following specific implementation is added to the management of the data transmission time, as shown in fig. 4:

the multi-core artificial intelligence automatic driving processor comprises a 2D5/5G MAC module, the 2D5/5G MAC module comprises a data sending time management main controller, an MAC sending module, an MAC receiving module, a sending buffer module with a time trigger, a time control protocol configuration eavesdropping module, a receiving timestamp learning module, a 2D5/5G MII interface and a 2D5/5G SERDES module, and the 2D5/5G SERDES module is connected with the PoDL module through a 1000base-T1 external link.

The data sending time management main controller is electrically connected with the MAC sending module, the MAC sending module is electrically connected with the 2D5/5G MII interface and the 2D5/5G SERDS module, the 2D5/5G MII interface and the 2D5/5G SERDS module are electrically connected with the MAC receiving module, and the MAC receiving module is electrically connected with the data sending time management main controller.

The data sending time management main controller is electrically connected with the receiving timestamp learning module with the time trigger sending buffer module, the sending buffer module with the time trigger sending buffer module is electrically connected with the MAC sending module, the AC sending module is electrically connected with the 2D5/5G MII interface and the 2D5/5G SERDES module, the 2D5/5G MII interface and the 2D5/5G SERDES module are electrically connected with the MAC receiving module, the MAC receiving module is electrically connected with the receiving timestamp learning module, the receiving timestamp learning module is electrically connected with the sending buffer module with the time trigger, and the time control protocol configuration eavesdropping module is electrically connected with the sending buffer module with the time trigger sending buffer module and is in bidirectional intercommunication.

In the invention, before modification, the MAC sends the data to be sent at any time; after modification, the data will not be sent directly to the MAC sending module, but to a buffer with a time trigger; the transmitted message of RTP time configuration or similar protocol configuration is copied to a time control eavesdropping module for configuration analysis, and the analyzed data is fed back to a buffer zone with a time trigger for controlling the transmission time of the data; a receiving timestamp learning module is added at a receiving end and used for analyzing the gap time of a received message and sending data to a buffer area with a time trigger and used for controlling the sending time of the data; after modification, the data transmission is strictly controlled in the middle of the data receiving gap, so that the data on the 2D5/5Gbase-T1 can not be overlapped, the power consumption is far lower than the common IEEE802.3ch Ethernet PHY, the heat dissipation and ESD cost can be greatly reduced, the purpose of transmitting the data to the 5Gbps can be achieved by using a UTP non-shielding wire, the design difficulty can be reduced, the production cost and the maintenance cost are greatly reduced, the method is suitable for data transmission of the laser radar and the camera of automatic driving, and the data and the electric energy can be transmitted simultaneously.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.

Claims

1. The method for realizing UTP on 2D5 or 5Gbase-T1 comprises a multi-core artificial intelligence automatic driving processor, a structured driving instruction heterogeneous processor with a 5G baseband, a TSN exchange processor, a main ECCUs module, a power supply, a radar, a camera, two PoDL modules and a plurality of 2D5G/5Gbase-T1 double-engine PHY modules, and is characterized in that the multi-core artificial intelligence automatic driving processor is electrically connected with the structured driving instruction heterogeneous processor with the 5G baseband, the multi-core artificial intelligence automatic driving processor is electrically connected with the plurality of 2D5G/5Gbase-T1 double-engine PHY modules, wherein the two 2D5G/5Gbase-T1 double-engine PHY modules are respectively electrically connected with the two PoDL modules, the two PoDL modules are electrically connected with the radar and the camera, the power supply is electrically connected with the two PoDL modules, the structured running command heterogeneous processor with the 5G baseband is electrically connected with the TSN exchange processor, and the TSN exchange processor is electrically connected with the main ECCUs module; the multi-core artificial intelligence automatic driving processor is connected with 2D5G/5GSERDES links between the 2D5G/5Gbase-T1 double-engine PHY module and the structural driving instruction heterogeneous processor with the 5G base band, and between the structural driving instruction heterogeneous processor with the 5G base band and the TSN exchange processor; the 2D5G/5Gbase-T1 double-engine PHY module is connected with the PoDL module through a 2D5G/5Gbase-T1 plate link; the two PoDL modules are connected with the radar and the camera through a 2D5G/5Gbase-T1 external link; a 1000base-T1 external link connection between the TSN switch processor and the main ECCUs module; the multi-core artificial intelligence automatic driving processor comprises a 2D5/5G MAC module, the 2D5/5G MAC module comprises a data sending time management main controller, an MAC sending module, an MAC receiving module, a sending buffer module with a time trigger, a time control protocol configuration eavesdropping module, a receiving timestamp learning module, a 2D5/5G MII interface and a 2D5/5G SERDES module, and the 2D5/5G SERDES module is connected with a PoDL module through a 1000base-T1 external link; the data sending time management main controller is electrically connected with the MAC sending module, the MAC sending module is electrically connected with the 2D5/5G MII interface and the 2D5/5G SERD module, the 2D5/5G MII interface and the 2D5/5G SERD module are electrically connected with the MAC receiving module, and the MAC receiving module is electrically connected with the data sending time management main controller; the data sending time management main controller is electrically connected with the receiving timestamp learning module with the time trigger sending buffer module, the sending buffer module with the time trigger sending buffer module is electrically connected with the MAC sending module, the AC sending module is electrically connected with the 2D5/5G MII interface and the 2D5/5GSERDES module, the 2D5/5G MII interface and the 2D5/5GSERDES module are electrically connected with the MAC receiving module, the MAC receiving module is electrically connected with the receiving timestamp learning module, the receiving timestamp learning module is electrically connected with the sending buffer module with the time trigger sending buffer module, and the time control protocol configuration eavesdropping module is electrically connected with the sending buffer module with the time trigger sending buffer module and is in bidirectional intercommunication.