CN111293668A

CN111293668A - Protection circuit for preventing single event from burning solid power controller

Info

Publication number: CN111293668A
Application number: CN201811496902.3A
Authority: CN
Inventors: 万波
Original assignee: Shanghai Aviation Electric Co Ltd
Current assignee: Shanghai Aviation Electric Co Ltd
Priority date: 2018-12-07
Filing date: 2018-12-07
Publication date: 2020-06-16

Abstract

The invention discloses a protection circuit for preventing a solid-state power controller from being burnt by single particles, which comprises a power supply input end, a power supply output end and a power supply output end, wherein the power supply input end is used for providing power supply voltage Vcc; the circuit comprises a resistor R1, a resistor R2, a voltage regulator tube Z1, an NPN triode T1 and an NPN triode T2, wherein a collector of the triode T1 and a first end of the resistor R2 both receive power supply voltage Vcc from a power supply input end, an emitter of the triode T1 is connected with a first end of the resistor R1, a second end of the resistor R1 is connected with a positive electrode of the voltage regulator tube Z1, a second end of the resistor R2 is respectively connected with a base of the triode T1, a negative electrode of the voltage regulator tube Z1 and a collector of the triode T2, an emitter of the triode T2 is grounded, and a second end of the resistor R1 is used for providing output voltage Vout. The invention has the beneficial effects that: the current consumed by the SSPC channel microprocessor does not exceed a preset value during normal operation by using negative feedback current limiting of the transistor T1.

Description

Protection circuit for preventing single event from burning solid power controller

Technical Field

The invention relates to a protection circuit for preventing a solid-state power controller from being burnt by single particles.

Background

The single event effect refers to the deposition of charges on the traces of individual energetic particles as they pass through the sensitive region of a microelectronic device, which are collected by the device electrodes, causing a change in the logic state of the device or device damage. The single event effect causes the stored information to be overturned and locked, and the transient disturbance of voltage and current, and in severe cases, the single event effect causes the breakdown of gate oxide and even the burning of devices.

The single-particle burnout is a severe consequence of the single-particle effect, and is caused by the instantaneous large current generated when high-energy particles bombard a microelectronic device, which can cause the permanent damage of the device. For SSPCs, it can result in permanent failure of the channel, causing power to the load to be interrupted.

The biggest difference between single event burnout and soft faults such as single event latchup or single event upset is that the latter can restore the normal operation of the SSPC channel by power-on reset, and once the former happens, the channel is permanently disabled. Therefore, hard failures, like single event burnouts, are prevented before the failure occurs.

Disclosure of Invention

The invention aims to solve the technical problem of single event burnout of a microprocessor and provides a novel protection circuit for preventing a solid state power controller from being burnt out by single events.

In order to achieve the purpose, the technical scheme of the invention is as follows: a protection circuit for preventing a solid state power controller from being burnt by single particles comprises,

a power supply input terminal for supplying a power supply voltage Vcc;

a resistor R1, a resistor R2, a regulator tube Z1, an NPN triode T1 and an NPN triode T2, wherein a collector of the triode T1 and a first end of the resistor R2 both receive a power supply voltage Vcc from a power supply input end, an emitter of the triode T1 is connected with a first end of the resistor R1, a second end of the resistor R1 is connected with an anode of the regulator tube Z1, a second end of the resistor R2 is respectively connected with a base of the triode T1, a cathode of the regulator tube Z1 and a collector of the triode T2, an emitter of the triode T2 is grounded, and a second end of the resistor R1 is used for providing an output voltage Vout;

the comparator is provided with a non-inverting input end, an inverting input end and an output end, the non-inverting input end of the comparator is used for receiving the output voltage Vout from the second end of the first resistor, the inverting input end of the comparator is used for receiving the reference voltage Vref provided by the outside, and if the output voltage Vout is lower than the reference voltage Vref, the output end of the comparator provides a short circuit control signal;

the D trigger is provided with a data input end, a data latch output end and a control end, the data input end of the D trigger is used for receiving power supply voltage Vcc from the power supply input end, the control end of the D trigger is connected with the output end of the comparator, the data latch output end of the D trigger is connected with the base electrode of the triode T2, when the control end of the D trigger receives a short-circuit control signal from the output end of the comparator, the data latch output end of the D trigger provides a short-circuit alarm signal, and the short-circuit alarm signal is at a high level, so that the triode T2 is conducted; and the number of the first and second groups,

and the linear power supply LD0 is used for receiving the output voltage Vout from the second end of the resistor R1 and supplying power to the SSPC channel microprocessor uP1 according to the output voltage Vout.

As a preferable scheme of the protection circuit for preventing the solid-state power controller from being burnt by the single event, the D flip-flop further has a reset terminal, and the reset terminal of the D flip-flop is used for receiving a channel reset signal from the main control uP 2.

Compared with the prior art, the invention has the beneficial effects that: (1) the negative feedback current limiting of the triode T1 is utilized, so that the current consumed by the SSPC channel microprocessor does not exceed a preset value during normal working; (2) if a precursor of single-particle burnout occurs, instantaneous large current is caused, when the output voltage Vout is pulled down instantaneously, when the output voltage Vout is lower than the reference voltage Vref, the output end of the comparator provides a short-circuit control signal to signal the D trigger to provide a short-circuit control signal, so that the triode T2 is switched on, the base of the triode T1 is pulled down, and at the moment, the power supply of the SSPC channel microprocessor uP1 is cut off, thereby avoiding the possibility that the SSPC channel microprocessor uP1 is burned down by the large current.

In addition to the technical problems addressed by the present invention, the technical features constituting the technical solutions, and the advantageous effects brought by the technical features of the technical solutions described above, other technical problems solved by the present invention, other technical features included in the technical solutions, and advantageous effects brought by the technical features will be described in further detail with reference to the accompanying drawings.

Drawings

Fig. 1 is a schematic circuit diagram according to an embodiment of the invention.

Fig. 2 is a schematic structural diagram of an embodiment of the present invention.

FIG. 3 is a flow chart illustrating the use of an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail below with reference to specific embodiments and drawings. Here, the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

Referring to fig. 1, a protection circuit for preventing a solid state power controller from being burnt by a single event is shown, which is applied to a single-power or multi-power airplane. The protection circuit comprises a first protection circuit and a second protection circuit,

a power supply input for providing a power supply voltage Vcc.

The resistor R1, the resistor R2, the voltage regulator Z1, the NPN transistor T1, the NPN transistor T2, and the collector of the transistor T1 and the first end of the resistor R2 all receive the power supply voltage Vcc from the power supply input end. The emitter of the transistor T1 is connected to the first terminal of the resistor R1. The second end of the resistor R1 is connected to the anode of the stabilivolt Z1. The second end of the resistor R2 is connected to the base of the transistor T1, the negative electrode of the regulator tube Z1, and the collector of the transistor T2, respectively. The emitter of transistor T2 is connected to ground. The second terminal of the resistor R1 is used to provide the output voltage Vout. The negative feedback current limiting of the triode T1 is utilized, so that the current consumed by the SSPC channel microprocessor uP1 does not exceed a preset value during normal operation.

The comparator is provided with a non-inverting input end, an inverting input end and an output end. The non-inverting input terminal of the comparator is used for receiving the output voltage Vout from the second terminal of the first resistor. The inverting input of the comparator is used for receiving an externally provided reference voltage Vref. The reference voltage Vref is a preset value. During normal operation, the output voltage Vout should be less than the reference voltage Vref. If the output voltage Vout is lower than the reference voltage Vref, it indicates that a single event burnout may occur, and the output terminal of the comparator provides a short-circuit control signal (in this embodiment, the short-circuit control signal is at a high level) to be processed by the system.

The D flip-flop is provided with a data input end, a data latch output end, a control end and a reset end. The data input of the D flip-flop is used to receive the supply voltage Vcc from the supply input. The control end of the D trigger is connected with the output end of the comparator. The data latch output end of the D trigger is connected with the base of the triode T2. The reset terminal of the D flip-flop is used for receiving a reset signal of the master microprocessor uP 2. When the control terminal of the D flip-flop receives the short circuit control signal from the output terminal of the comparator, the data latch output terminal of the D flip-flop provides a short circuit alarm signal (in this embodiment, the short circuit alarm signal is at a high level).

The linear power supply LD0 is for receiving the output voltage Vout from the second terminal of the resistor R1. The linear power supply LD0 supplies power and/or a RESET signal to the SSPC channel microprocessor uP1 depending on the output voltage Vout.

If the single-particle bombardment state is achieved, a transient large current appears in the SSPC channel microprocessor uP1, and the voltage of the output voltage Vout is pulled down when the precursor is burnt. When the output voltage Vout is lower than the reference voltage Vref, the output terminal of the comparator provides a short circuit control signal. The control end CP of the D trigger is raised, the data latch output end outputs a short-circuit alarm signal, the triode T2 is conducted, the base electrode of the triode T1 is pulled low, at the moment, the power supply of the SSPC channel microprocessor uP1 is cut off, and therefore the possibility that the SSPC channel microprocessor uP1 is burnt by large current is avoided.

Please refer to fig. 2, which includes 3 parts, namely, the master uP2, the protection circuit, and the SSPC channel uP 1.

Referring to fig. 3, after the master processor uP2 detects a short alarm signal from the protection circuit, it delays for 500ms before attempting to reset the D flip-flop to power uP the uP 1. If the single-particle bombardment is finished at the moment, the SSPC channel can be electrified again to work, and the load power supply can be recovered. Otherwise, uP2 will block the reset signal, and in the ground maintenance state, after finding out the accident reason, the SSPC channel can resume normal operation.

In addition, in the aspect of circuit design, the SSPC channel microprocessor reset circuit is further arranged in the circuit, and the specific method is that a short-circuit signal is detected through a main control processor of an SSPC board card, and after the signal is detected and is delayed for a certain time, a short-circuit latch of the SSPC channel is reset, and a power supply loop of the SSPC channel microprocessor is closed again. If the single-particle bombardment is finished at the moment, the SSPC channel can resume normal work, and the load power supply can be resumed.

The foregoing merely represents embodiments of the present invention, which are described in some detail and detail, and therefore should not be construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A protection circuit for preventing a solid state power controller from being burnt by single particles is characterized by comprising,

a power supply input terminal for supplying a power supply voltage Vcc;

2. The protection circuit of claim 1, wherein the D flip-flop further has a reset terminal, and the reset terminal of the D flip-flop is used for receiving a channel reset signal from the master uP 2.