CN111289799B

CN111289799B - GaN device dynamic on-resistance measuring circuit

Info

Publication number: CN111289799B
Application number: CN202010139474.XA
Authority: CN
Inventors: 周琦; 刘熙; 叶星宁; 陈涛; 李佳; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2020-03-03
Filing date: 2020-03-03
Publication date: 2021-01-08
Anticipated expiration: 2040-03-03
Also published as: CN111289799A

Abstract

The invention belongs to the technical field of electronic circuits, and relates to a GaN device dynamic on-resistance measuring circuit. According to the invention, based on the closely related dynamic characteristics in GaN application, the test circuit comprises a drive circuit, a soft-hard switch conversion circuit and a clamping circuit; the drive circuit takes ADuM4223 as a core; the switch conversion circuit comprises two high-voltage power devices, a load inductor and a diode playing a protection role; the clamp circuit adopts a mode of combining a current mirror and a diode to improve the measurement accuracy, and the dynamic on-resistance can be obtained by dividing the on-voltage measured by the clamp circuit by the current in the circuit. The testing method can measure the dynamic on-resistance of the device in two different switching processes in real time, and avoids the problem of inaccurate measuring result caused by defect recovery within several seconds after the device stops working.

Description

GaN device dynamic on-resistance measuring circuit

Technical Field

The invention belongs to the technical field of electronic circuits, and relates to a GaN device dynamic on-resistance measuring circuit.

Background

With the rapid development of society and the continuous progress of science and technology, semiconductor technology has become one of the high technologies which have the most influence on our lives. The core device of the switching power supply widely used for modern electronic products is a power semiconductor device, the most commonly used power semiconductor device at present mainly comprises a Si-based device, but due to parasitic parameters, the switching loss and the driving loss of the Si-based high-voltage and high-current device are more remarkable after the frequency is increased to MHz level, and the requirements of the society on energy conservation, emission reduction and environmental protection are improved, so that the Si-based device cannot meet the requirements of people on the electric energy conversion efficiency of power electronic devices. Due to the excellent characteristics of large forbidden band width, high breakdown electric field, high electron mobility and the like, the GaN device is very suitable for power electronic devices with high temperature, high frequency, high power and high breakdown voltage.

In a switch-mode power conversion circuit, GaN devices are continuously switched in an off state and an on state, resulting in device reliability problems. When in an off state, high voltage is applied between the drain electrode and the substrate, between the drain electrode and the source electrode and between the drain electrode and the grid electrode of the GaN device, so that failure mechanisms such as trap and time-dependent breakdown are caused; when the device is in an on state, the gate voltage is forward biased, and the high gate voltage enables the device to generate a trap or a leakage channel; in the semi-on state, the generation of hot electrons or lattice defects degrades device performance due to the presence of high voltage, high current conditions.

The dynamic on-resistance of GaN is one of the very important parameters in commercial GaN devices, and in the on-process, the increase of the dynamic resistance of GaN HEMT causes the significant increase of system loss, which further affects heat dissipation and finally affects the reliability of the system, so that research on the dynamic on-resistance is imperative, and the influence of the on-resistance change on the on-performance in practical application also needs to be urgently examined. In the on-resistance test stage of an actual device, the traditional circuit can not realize real-time measurement, and due to the lag of test time, part of defects can be recovered, so that the judgment of the on-resistance change of the GaN device in the actual switch operation is wrong, and the GaN device has serious reliability problem.

Disclosure of Invention

The invention aims to provide a dynamic on-resistance measuring circuit, which realizes the measurement of the voltage at two ends of a GaN device by combining a current source and a diode, a minimum resistor is connected in series in the circuit to obtain the current flowing through the GaN device, the on-resistance of the device in the switching process can be directly obtained by ohm's law, and the problems of measuring precision and incapability of obtaining real-time data of the on-resistance in the switching process are effectively solved.

The technical scheme adopted by the invention for solving the technical problems is as follows: a dynamic on-resistance measurement circuit comprising: the driving circuit comprises a driving unit, a soft-hard switch conversion unit and a clamping circuit unit, wherein a pin 15 of the driving unit is connected with an R6 in parallel through a resistor R7 and a diode D7 which are connected in series to serve as the input of a grid electrode of a tube U2 in the soft-hard switch circuit, a pin 16 of the driving unit is connected with an R8 in parallel through a resistor R9 and a diode D8 which are connected in series to serve as the input of a grid electrode of a tube U3 in the soft-hard switch circuit, a source electrode of a tube U2 in the soft-hard switch circuit is connected with a drain electrode of a tube U3 in the next stage to serve as the input of the clamping circuit.

Specifically, drive circuit is the accurate half-bridge driver of isolated, and the driver chip model is ADuM4223, and 16 total pins provide two drive channel A and B of keeping apart, are respectively: the pin 1 is an input voltage VIA of a driving channel A, is connected with a function generator to input square waves, is grounded through two resistors R1 and R2 which are connected in parallel, and is in parallel relation with the function generator; the pin 2 is an input voltage VIB of a driving channel B, is connected with a function generator to input square waves, is grounded through two resistors R3 and R4 which are connected in parallel, and is in parallel relation with the function generator;

pins

3 and 8 are VDD1 and VDD2 pins, respectively, are connected with a power supply VDD, and are connected with a pin 4 through a capacitor C5, and the capacitor and the power supply are in parallel connection; pin 5 is DISABLE, the control output is restored to the input state after the set time, and the control output is grounded through a resistor R5; the

pins

7, 12, 6 and 13 are all empty pins; the pin 10 is the power supply voltage of the driving channel A, is connected with a power supply VDDA, is connected with a pin 14 through two shunt capacitors C3 and C4 which are connected in parallel, and the capacitors and the power supply are in parallel relation; the pin 11 is the power supply voltage of the driving channel B, is connected with a power supply VDDB, is connected with the pin 9 through two shunt capacitors C1 and C2 which are connected in parallel, and the capacitors and the power supply are in parallel relation; pins 4, 14, 9 are GND1, GNDA, GNDB, respectively, connected to ground GND1 of VDD1 and VDD2 power supplies, VDDA power ground GNDA and VDDB power ground GNDB, respectively; the pin 16 is an output pin VOA of the driving channel A, and is connected to the soft-hard switch conversion unit through a circuit which is formed by connecting a resistor R7 and a diode D7 in series and then connecting the resistor R6 in parallel; the pin 15 is an output pin VOB of the driving channel B, and is connected to the soft-hard switch conversion unit through a circuit which is formed by connecting a resistor R9 and a diode D8 in series and then connecting the resistor R8 in parallel;

the soft and hard switch conversion unit adopts two enhancement type GaN transistors as main bodies, namely a first enhancement type GaN transistor and a second enhancement type GaN transistor respectively, and a source electrode of the first enhancement type GaN transistor is connected with a drain electrode of the second enhancement type GaN transistor to be used as an input end of the clamping circuit; the grid of the first enhancement mode GaN transistor is connected with a circuit formed by connecting a resistor R7 with a diode D7 in series and then connecting the resistor R6 in parallel, and the grid of the second enhancement mode GaN transistor is connected with a circuit formed by connecting a resistor R9 with a diode D8 in series and then connecting the resistor R8 in parallel; the drain of the first enhancement mode GaN transistor is connected with one end of the capacitor groups C6, C7, C8, C9 and C10 which are connected in parallel and one end of the inductor L, and is simultaneously connected with the anode of a power supply V1, and the cathode of the power supply V1 is connected with the other end of the capacitor groups C6, C7, C8, C9 and C10 which are connected in parallel; the drain electrode of the second enhancement mode GaN transistor and the other end of the inductor L are connected with one end of a switch, the other end of the switch is connected with one ends of the capacitor groups C11, C12, C13 and C14 which are connected in parallel and the anode of the power supply V2, and the cathode of the power supply V2 is connected with the other ends of the capacitor groups C11, C12, C13 and C14 which are connected in parallel; the negative electrode of the power supply V1 and the negative electrode of the power supply V2 are connected with one end of the slide rheostat R11, and the other end of the slide rheostat R11 is grounded with GNDB after passing through the resistor R10; the grid electrode of the first enhancement mode GaN transistor is also connected with the cathode of the diode D9, and the anode of the diode D9 is grounded GNDA; the grid electrode of the second enhancement mode GaN transistor is also connected with the cathode of the diode D10, and the anode of the diode D10 is grounded GNDB;

the ratio of V2/V1 may determine the duty cycle;

the clamping circuit comprises diodes D1, D2, D3, D4, D5 and D6, PNP silicon double transistors T1 and T2 and a resistor R12; the cathode of the D1 is connected with the connection point of the source electrode of the first enhancement type GaN transistor and the drain electrode of the second enhancement type GaN transistor, and the cathode of the D2 is connected with the cathode of the power supply V2; the anode of the diode D3 is connected with the anode of the diode D1, the cathode of the diode D3 is connected with the anode of the diode D4, the cathode of the diode D4 is connected with the anode of the diode D5, the cathode of the diode D5 is connected with the diode D6, the cathode of the diode D6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with the anode of the diode D2; the anode of the diode D3 is connected with the pin 1 of the PNP silicon double transistor T1, the pin 2 of the PNP silicon double transistor T1 is connected with the cathode of the diode D6, the pin 3 of the PNP silicon double transistor T1 is connected with the pin 1 of the PNP silicon double transistor T2, the pin 4 of the PNP silicon double transistor T1 is connected with the pin 2 of the PNP silicon double transistor T2, the pins 3 and 4 of the PNP silicon double transistor T2 are connected and connected with a 10V power supply, the anode of the diode D2 is connected with the ground GNDB, and the dynamic on-resistance of the device can be obtained by dividing the current in the circuit by the on-state voltage measured by using a clamping circuit;

the soft and hard switching conversion of the soft and hard switching conversion unit is as follows:

when the switch is turned on, the circuit is in a hard switch mode, at the moment, a VIA pin 1 of the driving circuit is connected with a low level, a VIB pin 2 of the driving circuit is connected with a 5V square wave, a pin 10 outputs the low level, namely, a grid electrode of the first enhancement type GaN transistor is connected with the low level, and the first enhancement type GaN transistor is not turned on; the pin 11 outputs a 5V square wave, and the on-off state of the second enhancement type GaN transistor is switched along with the level of the square wave of the pin 11;

when the switch is turned off, the circuit is in a soft switching mode, at the moment, a VIA pin 1 of the driving circuit is connected with a 5V square wave signal different from a VIB, a VIB pin 2 of the driving circuit is connected with a 5V square wave, the on-off state of the first enhancement type GaN transistor is switched along with the level of the square wave of a pin 10, and the on-off state of the second enhancement type GaN transistor is switched along with the level of the square wave of a pin 11.

T2 and T3 are double transistors formed by connecting two PNP tube gates, and the diodes D3, D4, D5 and D6 are all the same diodes.

The invention has the beneficial effects that:

(1) the invention realizes the soft-hard switch conversion circuit, can be converted simply by opening and closing the switch, and can better research the influence of the switch state on the device through the circuit.

(2) The invention uses the clamping circuit of combining the diode and the transistor, the circuit measurement delay and the peak value are obviously improved, and the obtained result has higher accuracy.

(3) The invention can adjust the duty ratio, and can apply pressure of different time to diversify the testing process.

Drawings

Fig. 1 is a schematic view of a driving unit according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a soft-hard switching unit according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a clamp unit according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a dynamic on-resistance measurement circuit according to an embodiment of the invention.

FIG. 5 is a waveform diagram illustrating operation of an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present invention are described in detail below with reference to the accompanying drawings.

The embodiment of the invention provides a dynamic on-resistance measuring circuit, which comprises: the circuit comprises a driving unit, a soft-hard switch conversion unit and a clamping circuit unit. The pin 15 of the driving unit is connected in parallel with the R6 through a resistor R7 and a diode D7 which are connected in series to serve as the input of the gate of the tube U2 in the soft-hard switching circuit, the pin 16 of the driving unit is connected in parallel with the R8 through a resistor R9 and a diode D8 which are connected in series to serve as the input of the gate of the tube U3 in the soft-hard switching circuit, the source of the tube U2 in the soft-hard switching circuit is connected with the drain of the tube U3 in the next stage to serve as the input of the clamping circuit, and is connected with the cathode of the diode D1.

As shown in fig. 1, the driving unit is used to provide suitable gate voltages for gates of upper and lower transistors of the soft and hard switching circuit, and the driving unit adopts an isolated precision half-bridge driver of type ADuM4223, and has 16 pins in total, and provides two isolated driving channels a and B.

The input voltage VIA of a driving channel A is taken as a pin 1 of the driver, the input square wave is connected with a function generator and grounded through two parallel resistors R1 and R2, the resistors and the function generator are in parallel connection, the input voltage VIB of a driving channel B is taken as a pin 2, the input square wave is connected with the function generator and grounded through two parallel resistors R3 and R4, and the resistors and the function generator are in parallel connection.

Pins

3 and 8 are pins VDD1 and VDD2, respectively, and are connected with a power supply VDD, the pins are connected with a pin 4 through a capacitor C5, the capacitor and the power supply are in parallel connection, a pin 5 is DISABLE, the pin controls the time after which the output is recovered to an input state, the pin is grounded through a resistor R5,

pins

7, 12, 6 and 13 are pins NC1, NC2, NC3 and NC4, respectively, and can be disconnected, the pins 4, 14 and 9 are GND1, GNDA and GNDB, respectively, and are connected with ground GND1 of the power supplies VDD1 and VDD2, and the ground GNDA of the VDDA power supply and the ground GNDB of the VDDB power supply.

The pin 11 is the supply voltage of the driving channel B, is connected with a power supply VDDB, is connected with a pin 9 through two shunt capacitors C1 and C2 which are connected in parallel, the capacitor and the power supply are in parallel, the pin 16 is the supply voltage of the driving channel A, is connected with the power supply VDDA, is connected with a pin 14 through two shunt capacitors C3 and C4 which are connected in parallel, the capacitor and the power supply are in parallel, the pin 16 is an output pin VOA of the driving channel A, is connected in series with a diode D7 through a resistor R7 and then connected in parallel with a resistor R6 to a grid of a next stage U2, the pin 10 is an output pin VOB of the driving channel B, is connected in series with a diode D8 through a resistor R9 and then connected in parallel with a resistor R8 to a.

As shown in fig. 2, the soft-hard switching unit mainly uses two GaN devices U2 and U3, and both U2 and U3 are enhancement GaN transistors. The source of U2 is connected with the drain of U3 as the input end of the next stage, the drain of U2 is connected with the upper ends of capacitor groups C6, C7, C8, C9 and C10 which are connected in parallel, the upper end of an inductor L and the anode of a power supply V1, the cathode of the power supply V1 is connected with the lower ends of capacitor groups C6, C7, C8, C9 and C10 which are connected in parallel, the drain of a GaN device U3 is connected with a switch S, the right end of the switch is connected with the cathode of a diode D1 of the next cell, the gate of a diode D2 is connected with the upper end of a diode D9, the lower end of the diode D9 is connected with ground GNDA, the gate of U3 is connected with the upper end of a diode D10, the lower end of a diode D10 is connected with ground GNDB, the lower ends of capacitor groups C6, C7, C8, C9 and C10 and the lower ends of capacitor groups C11 and the varistor 11 which are connected with the cathode of a power supply V2, the capacitor group C11, the other end of the resistor 36. Diodes D9 and D10 act as a protection circuit, and the duty cycle can be derived from V2/V1.

As shown in fig. 3, the clamp circuit includes 6 diodes, 2 PNP silicon double transistors and 1 resistor, the anode of diode D3 is connected to the anode of diode D1, the cathode of diode D3 is connected to the anode of diode D4, the cathode of diode D4 is connected to the anode of diode D5, the cathode of diode D5 is connected to diode D6, the cathode of diode D6 is connected to one end of resistor R12, the other end of resistor R12 is connected to the anode of diode D2, the anode of diode D3 is connected to pin 1 of double transistor T1, pin 2 of double transistor T1 is connected to the cathode of diode D6, pin 3 is connected to pin 1 of double transistor T2, pin 4 is connected to pin 2 of double transistor T2,

pins

2 and 3 and 4 of double transistor T are connected to the 10V power supply, and the anode of diode D2 is connected to ground GNDB.

The working principle and process of the half-bridge circuit dc-dc protection circuit provided by the embodiment of the present invention are described in detail below with reference to fig. 4:

in the embodiment of the invention, ADuM4223 is used as a driving chip to provide a proper grid signal for the soft and hard switch conversion circuit, the soft and hard switch conversion circuit realizes the soft and hard switch conversion by the on and off of the switch, when the switch is on, the circuit is a hard switch circuit, and when the switch is off, the circuit is a soft switch circuit. The clamping circuit adopts a mode of combining a diode and a transistor, when the voltage at two ends of the clamping circuit connected with the upper stage is higher than the series voltage of four diodes D3, D4, D5 and D6, the voltage at two ends of the clamping circuit is equal to the series voltage of the diodes, and if the voltage at two ends of the clamping circuit is lower than the series voltage of the four diodes, the voltage at two ends of the clamping circuit is equal to the output voltage of the circuit at the upper stage, namely equal to the breakover voltage.

When the switch is on, the circuit is in hard switching mode. At this time, a VIA pin 1 of the U1 is connected with a low level, a VIB pin of the U1 is connected with a 5V square wave, the VOA outputs the low level, a grid electrode of the U2 is connected with the VOA which is the low level, the U2 is not turned on, the VOB outputs the 5V square wave, a grid electrode of the U3 is connected with the VOB, and the on-off state is switched along with the level of the square wave. When the U3 is turned on, the VDS of the U3 drops to a small conduction voltage, the current iDS gradually rises, when the U3 is turned off, the VDS of the U3 rises to the voltage applied at the drain terminal, the iDS is reduced to 0, the U3 is turned on again, the VDS drops to a small conduction voltage again, and the current iDS continues to rise on the basis of the last rise.

When the switch is closed, the circuit is in a soft switching mode. At this time, a VIA pin 1 of the U1 is connected with a 5V square wave signal different from VIB, a VIB pin of the U1 is connected with a 5V square wave, the VOA outputs low level, a gate of the U2 is connected with the VOA to be low level, the on-off state of the U2 is switched along with the level of the square wave of the VOA, and the on-off state of the U3 is switched along with the level of the square wave. When U2 is turned on, U3 is turned off, the VDS of U3 is equal to the voltage applied by the drain, when U2 is turned off, U3 is turned off, the VDS of U3 drops to a small conduction voltage during this period, iDS takes a negative value, when U2 is turned off, U3 is turned on, the VDS of U3 keeps a small conduction voltage, during this period, iDS rises slowly, when U2 is turned off, U3 is turned off, the VDS of U3 rises to the voltage applied at both ends, iDS drops to 0, when U2 is turned on again, U3 is turned off, the VDS of U3 is equal to the voltage applied by the drain, current iDS is 0, when U2 and U3 are turned off again at the same time, the VDS of U3 drops to a small conduction voltage during this period, and iDS takes a negative value.

The above waveform conversion can be converted into a waveform as shown in fig. 5.

The voltage of VDS (VDS) (M) measured by the oscilloscope is divided by the current in the circuit to obtain the dynamic on-resistance, the voltage of two ends of R10 measured by the oscilloscope is used for the current in the circuit, and the current flowing through R10 is obtained through ohm's law, namely the current in the circuit.

Claims

1. A GaN device dynamic on-resistance measuring circuit comprises a driving circuit, a soft and hard switch conversion unit and a clamping circuit; the method is characterized in that:

the drive circuit is the accurate half-bridge driver of isolated, and the driver chip model is ADuM4223, and 16 total pins provide two drive channel A and B of keeping apart, do respectively: the pin 1 is an input voltage VIA of a driving channel A, is connected with a function generator to input square waves, is grounded through two resistors R1 and R2 which are connected in parallel, and is in parallel relation with the function generator; the pin 2 is an input voltage VIB of a driving channel B, is connected with a function generator to input square waves, is grounded through two resistors R3 and R4 which are connected in parallel, and is in parallel relation with the function generator; pins 3 and 8 are VDD1 and VDD2 pins, respectively, are connected with a power supply VDD, and are connected with a pin 4 through a capacitor C5, and the capacitor and the power supply are in parallel connection; pin 5 is DISABLE, the control output is restored to the input state after the set time, and the control output is grounded through a resistor R5; the pins 7, 12, 6 and 13 are all empty pins; the pin 10 is the power supply voltage of the driving channel A, is connected with a power supply VDDA, is connected with a pin 14 through two shunt capacitors C3 and C4 which are connected in parallel, and the capacitors and the power supply are in parallel relation; the pin 11 is the power supply voltage of the driving channel B, is connected with a power supply VDDB, is connected with the pin 9 through two shunt capacitors C1 and C2 which are connected in parallel, and the capacitors and the power supply are in parallel relation; pins 4, 14, 9 are GND1, GNDA, GNDB, respectively, connected to ground GND1 of VDD1 and VDD2 power supplies, VDDA power ground GNDA and VDDB power ground GNDB, respectively; the pin 16 is an output pin VOA of the driving channel A, and is connected to the soft-hard switch conversion unit through a circuit which is formed by connecting a resistor R7 and a diode D7 in series and then connecting the resistor R6 in parallel; the pin 15 is an output pin VOB of the driving channel B, and is connected to the soft-hard switch conversion unit through a circuit which is formed by connecting a resistor R9 and a diode D8 in series and then connecting the resistor R8 in parallel;

the clamping circuit comprises diodes D1, D2, D3, D4, D5 and D6, PNP silicon double transistors T1 and T2 and a resistor R12; the cathode of the D1 is connected with the connection point of the source electrode of the first enhancement type GaN transistor and the drain electrode of the second enhancement type GaN transistor, and the cathode of the D2 is connected with the cathode of the power supply V2; the anode of the diode D3 is connected with the anode of the diode D1, the cathode of the diode D3 is connected with the anode of the diode D4, the cathode of the diode D4 is connected with the anode of the diode D5, the cathode of the diode D5 is connected with the diode D6, the cathode of the diode D6 is connected with one end of a resistor R12, and the other end of the resistor R12 is connected with the anode of the diode D2; the anode of the diode D3 is connected with a pin 1 of a PNP silicon double transistor T1, a pin 2 of a PNP silicon double transistor T1 is connected with the cathode of the diode D6, a pin 3 of the PNP silicon double transistor T1 is connected with a pin 1 of a PNP silicon double transistor T2, a pin 4 of a PNP silicon double transistor T1 is connected with a pin 2 of the PNP silicon double transistor T2, pins 3 and 4 of the PNP silicon double transistor T2 are connected with a 10V power supply, and the anode of the diode D2 is connected to the ground GNDB; the dynamic on-resistance of the device can be obtained by dividing the on-voltage measured by the clamping circuit by the current in the circuit;

when the switch is turned on, the circuit is in a hard switch mode, at the moment, a VIA pin 1 of the driving circuit is connected with a low level, a VIB pin 2 of the driving circuit is connected with a 5V square wave, a power supply VDDA outputs the low level to a pin 10, namely, a grid electrode of the first enhancement type GaN transistor is connected with the low level, and the first enhancement type GaN transistor is not turned on; the power supply VDDB outputs 5V square waves to the pin 11, and the on-off state of the second enhancement type GaN transistor is switched along with the level of the square waves of the pin 11;