CN111277268A - Switched capacitor integrator and control method thereof - Google Patents
Switched capacitor integrator and control method thereof Download PDFInfo
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- CN111277268A CN111277268A CN201811478222.9A CN201811478222A CN111277268A CN 111277268 A CN111277268 A CN 111277268A CN 201811478222 A CN201811478222 A CN 201811478222A CN 111277268 A CN111277268 A CN 111277268A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/126—Multi-rate systems, i.e. adaptive to different fixed sampling rates
Abstract
The invention discloses a switched capacitor integrator, which comprises: the sampling circuit is used for sampling external input according to a clock signal and the integrating capacitor is connected between the inverting input end and the output end of the operational amplifier; it is characterized by also comprising: the first reset switch is connected between the sampling circuit and the inverting input end of the operational amplifier, and the second reset switch is connected with the integrating capacitor in parallel; the reset control circuit is used for controlling the on-off of the first reset switch and the second reset switch; when the switched capacitor integrator enters a working state, the reset control circuit controls the first reset switch to be switched off and the second reset switch to be switched on for a preset time, and then controls the first reset switch to be switched on and the second reset switch to be switched off. The invention also discloses a control method of the switched capacitor integrator.
Description
Technical Field
The present invention relates to the field of integrated circuit technology. And more particularly, to a switched capacitor integrator and a control method thereof.
Background
Switched capacitor integrators are widely used in the field of integrated circuits. In particular, switched capacitor integrators are widely used as basic modules in integrated circuits such as switched capacitor filters and sampling and amplifying circuits.
A typical switched capacitor application in an integrated circuit is shown in fig. 1. Fig. 1(a) shows an in-phase switched capacitor integrator, and fig. 1(b) shows an inverted switched capacitor integrator. The input signal is sampled by a clock signal control switch and the sampled signal is input into an operational amplifier to complete integration, and a common-mode signal is connected to the positive-phase input end of the operational amplifier. In the initial state before sampling the input signal, no direct current feedback exists, and no alternating current signal is sent to the feedback capacitor C2 for alternating current feedback, so that the amplifier is in an open loop state, the function of the comparator is shown, and the output static voltage of the amplifier is the power supply voltage. When the circuit begins to sample the input signal, the signal is sent through C1 to C2 and ac feedback begins to build. At this point, the output voltage of the amplifier begins to drop from the supply voltage back to the operating voltage. This settling time is typically long due to factors such as the size of the capacitor in the switched capacitor circuit, the switching frequency, and the amplifier output current.
As can be seen from the operational output response diagram of the prior art switched capacitor integrator circuit shown in FIG. 2, after the circuit starts to operate, the output signal of the conventional switched capacitor integrator circuit needs a long time to stabilize, and the stabilization time includes two stages, ① charges the inverting input terminal of the amplifier until the quiescent voltage reaches the common mode voltage Vcm, ②, then the output quiescent voltage of the amplifier drops back from the power supply voltage and gradually stabilizes at the common mode voltage Vcm.
Therefore, it is desirable to provide a new switched capacitor integrator circuit and a control method thereof, which can improve the self-operation response speed.
Disclosure of Invention
The invention aims to provide a novel switched capacitor integrator circuit which can improve the self working response speed.
In order to achieve the purpose, the invention adopts the following technical scheme:
one aspect provides a switched capacitor integrator, comprising: the sampling circuit is used for sampling external input according to a clock signal and the integrating capacitor is connected between the inverting input end and the output end of the operational amplifier; further comprising:
the first reset switch is connected between the sampling circuit and the inverting input end of the operational amplifier, and the second reset switch is connected with the integrating capacitor in parallel; and
the reset control circuit is used for controlling the on-off of the first reset switch and the second reset switch;
when the switched capacitor integrator enters a working state, the reset control circuit controls the first reset switch to be switched off and the second reset switch to be switched on for a preset time, and then controls the first reset switch to be switched on and the second reset switch to be switched off.
Preferably, the switched capacitor integrator further comprises: a clock circuit that provides a clock signal to the sampling circuit; and the enabling circuit provides enabling signals for the clock circuit and the reset control circuit so as to control the switched capacitor integrator to be in a working state or a non-working state.
Preferably, the sampling circuit comprises a sampling capacitor and a sampling switch, the sampling switch comprises a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch,
one end of the first sampling switch is connected with one end of the sampling capacitor, and the other end of the first sampling switch is connected with the external input; one end of the second sampling switch is connected with the other end of the first sampling capacitor, and the other end of the second sampling switch is connected with the first reset switch; one end of the third sampling switch is connected with the common end of the first sampling switch and the sampling capacitor, one end of the fourth sampling switch is connected with the common end of the sampling capacitor and the second sampling switch, the other end of the third sampling switch and the other end of the fourth sampling switch are grounded,
the clock circuit outputs two first clock signals and two second clock signals to the sampling switch, and the first clock signals and the second clock signals are two non-overlapped clock signals, so that the switched capacitor integrator serves as an in-phase switched capacitor integrator or an anti-phase switched capacitor integrator.
Preferably, the clock circuit inputs a first clock signal to the first sampling switch and the fourth sampling switch respectively and inputs a second clock signal to the second sampling switch and the third sampling switch respectively, so that the switched capacitor integrator serves as an in-phase switched capacitor integrator; alternatively, the first and second electrodes may be,
the clock circuit respectively inputs a first clock signal to the first sampling switch and the second sampling switch and respectively inputs a second clock signal to the third sampling switch and the fourth sampling switch, so that the switched capacitor integrator is used as an inverse switched capacitor integrator.
Another aspect of the present application provides a method of controlling a switched capacitor integrator, the method including:
outputting a clock signal to the sampling circuit to cause the sampling circuit to perform sampling on an external input according to the clock signal;
control signals are output to the first reset switch and the second reset switch to control the on-off of the first reset switch and the second reset switch,
when the switched capacitor integrator enters a working state, control signals are respectively output to the first reset switch and the second reset switch, so that the first reset switch is switched on and the second reset switch is switched off after the first reset switch is switched off and the second reset switch is switched on for a preset time.
Preferably, the method further comprises: and the switch capacitor integrator is controlled to be in a working state or a non-working state by sending enable signals to the clock circuit and the reset control circuit.
Preferably, the sampling circuit comprises a sampling capacitor and a sampling switch, the sampling switch comprises a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch,
the method further comprises the following steps: the switched capacitor integrator is used as an in-phase switched capacitor integrator or an anti-phase switched capacitor integrator by inputting two first clock signals and two second clock signals into the sampling circuit, wherein the first clock signals are complementary with the second clock signals.
Preferably, the sampling circuit comprises a sampling capacitor, a first sampling switch, a second sampling switch, a third sampling switch and a fourth sampling switch, and
when the sampling circuit is connected with the following structure: one end of the first sampling switch is connected with one end of the sampling capacitor, and the other end of the first sampling switch is connected with the external input; one end of the second sampling switch is connected with the other end of the sampling capacitor, and the other end of the second sampling switch is connected with the first reset switch; one end of the third sampling switch is connected with the common end of the first sampling switch and the sampling capacitor, one end of the fourth sampling switch is connected with the common end of the sampling capacitor and the second sampling switch, the other end of the third sampling switch and the other end of the fourth sampling switch are grounded,
inputting a first clock signal to the first sampling switch and the fourth sampling switch and inputting a second clock signal complementary to the first clock signal to the second sampling switch and the third sampling switch, so that the integrator serves as an in-phase switched capacitor integrator; or
The first clock signal is input to the first sampling switch and the second clock signal complementary to the first clock signal is input to the third sampling switch and the fourth sampling switch, so that the integrator functions as an inverted switched capacitor integrator.
The invention has the following beneficial effects:
the technical scheme of the invention provides a novel switched capacitor integrator circuit and a control method thereof, which can improve the self working response speed.
Drawings
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings;
FIGS. 1(a) and 1(b) are schematic circuit diagrams of prior art switched capacitor integrators;
FIG. 2 is a graph of the operational output response of a prior art switched capacitor integrator;
FIG. 3 is a schematic circuit diagram of a switched capacitor integrator in accordance with an embodiment of the present invention in the form of an in-phase switched capacitor integrator;
FIG. 4 is a schematic circuit diagram of a switched capacitor integrator in the form of an inverting switched capacitor integrator, according to an embodiment of the present invention;
FIG. 5 is an exemplary signal timing diagram of a method of controlling a switched capacitor integrator in accordance with the present invention; and
fig. 6 is a comparison of the output operational response of a switched capacitor integrator in accordance with an embodiment of the present invention and the prior art switched capacitor integrator shown in fig. 1.
Detailed Description
In order to more clearly illustrate the invention, the invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
In order to more clearly illustrate the invention, the invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
It should be understood that the ordinal numbers first, second, etc. described in the specification are for clarity of description only and are not intended to limit the order of elements, parts, or components, etc., i.e., a description of a first element, part, or component and a second element, part, or component may also refer to a second element, part, or component and the first element, part, or component.
Referring to fig. 3 and 4, fig. 3 and 4 respectively show a switched capacitor integrator 10 (collectively indicated by 10 in the specification when the in-phase switched capacitor integrator and the anti-phase switched capacitor integrator are not distinguished), according to the present invention, wherein fig. 3 is an exemplary in-phase switched capacitor integrator 10-1, fig. 4 is an exemplary anti-phase switched capacitor integrator 10-2, and hereinafter the switched capacitor integrators are each indicated by reference numeral 10 when no distinction is made.
The switched capacitor integrator 10 according to the present application includes a sampling circuit 101, an integrating capacitor C2, first and second reset switches W5 and W6, a clock circuit, and a reset control circuit. The sampling circuit 101 samples an external input according to a clock signal output by the clock circuit, the integrating capacitor C2 is connected between an inverting input terminal and an output terminal of the operational amplifier circuit OP1, and a non-inverting input terminal of the operational amplifier circuit OP1 is connected to a common mode voltage Vcm. The first reset switch W5 is connected in series between the sampling circuit 101 and the integrating capacitor, as shown with reference to fig. 3 and 4, i.e., the first reset switch W5 is connected between the sampling circuit 101 and the inverting input terminal of the operational amplifier OP 1. The second reset switch W6 is connected between the inverting terminal and the output terminal of the operational amplifier, i.e., the second reset switch W6 is connected in parallel with the integrating capacitor C2. The reset control circuit performs control by outputting a reset signal to the first reset switch W5 and the second reset switch W6 to control the on and off thereof.
Specifically, the state of the switched capacitor integrator 10 is divided into an operating state and a non-operating state, and the reset control circuit performs control of the first reset switch W5 and the second reset switch W6 when the switched capacitor integrator 10 is in the operating state. When the switched capacitor integrator 10 is in an operating state, the reset control circuit outputs reset control signals Res1 and Res2 to the first reset switch W5 and the second reset switch W6, so that after the first reset switch W5 is turned off and the second reset switch W6 is turned on for a set time period, reset control signals Res1 and Res2 with opposite levels are respectively output to the first reset switch W5 and the second reset switch W6, so that the first reset switch W5 is turned on and the second reset switch W6 is turned off. The preset time period t may be set to 1ms in the present application, but is not limited thereto. It can be understood that, with the improvement of chip performance, under the condition that the chip response speed can be achieved, the preset time t should be set as short as possible, as long as the operational amplifier OP1 forms a dc negative feedback circuit, so that the value of the output terminal output is equal to the common mode voltage Vcm input at the positive terminal of the operational amplifier OP1 through feedback.
The exemplary switched capacitor integrator 10 according to the present application may further include a clock circuit and an enable circuit. In this case, the enable circuit generates the output signal Ao as enable signals Ci and Bi to the clock circuit and the reset control circuit by inputting the signal EN to the enable circuit, thereby controlling the switched capacitor integrator 10 to enter the operating state. Therefore, by providing the switched capacitor integrator 10 with an enable circuit, the switched capacitor can be controlled to be in an operating state or a non-operating state. When the enable circuit inputs the enable signals Ci and Bi to the clock circuit and the reset control circuit, the clock circuit and the reset control circuit are enabled to generate clock signals Φ 1 and Φ 2 and reset control signals Res1 and Res2, respectively, and control is performed on the sampling circuit 101, the first bit switch W5, and the second reset switch W6.
The above-described structural relationship of the present application will be specifically described below with reference to fig. 3 and 4.
The sampling circuit 101 includes a sampling capacitor C1, a first sampling switch W1, a second sampling switch W2, a third sampling switch W3, and a fourth sampling switch W4.
One end of the first sampling switch W1 is connected to the external Input signal Input, and the other end of the first sampling switch W1 is connected to one end of the sampling capacitor C1; one end of the second sampling switch W2 is connected with the other end of the sampling switch C1, and the other end of the second sampling switch W2 is connected with the first reset switch W5; one end of the third sampling switch W3 is connected to the common terminal of the first sampling switch W1 and the sampling capacitor C1, and the other end of the third sampling switch W3 is grounded, preferably, may be connected to an ac ground; one end of the fourth sampling switch W4 is connected to the common terminal of the second sampling switch W2 and the sampling switch C1, and the other end of the fourth sampling switch W4 is grounded, preferably, may be connected to an ac ground.
The clock circuit has two outputs Co1 and Co2 that output two non-overlapping clock signals Φ 1 and Φ 2, which, as will be appreciated by those skilled in the art, ensures that the two clocks are not high at the same time. In the non-inverting switched capacitor integrator, as shown in fig. 3, a clock signal Φ 1 output from Co1 is input to the first sampling switch W1 and the fourth sampling capacitor W4, and a clock signal Φ 2 output from Co2 is input to the second sampling switch W2 and the third sampling switch W3. In the inverting switched capacitor integrator 10-2, the clock signal Φ 1 output from the Co1 is input to the first sampling switch W1 and the second sampling switch W2, and the clock signal Φ 2 output from the Co2 is input to the third sampling switch W3 and the fourth sampling switch W4.
The reset control circuit has two output terminals Bo1 and Bo2, a reset control signal Res1 output by Bo1 controls the first reset switch W5, and a reset control signal Res2 output by Bo2 controls the second reset switch W6.
The structural principle and control method of the switched capacitor integrator 10 of the present application are further described below with reference to an exemplary signal timing diagram of the control method of the switched capacitor integrator 10 according to the present invention shown in fig. 5.
The timing diagrams of the signals of EN, Bo1, Bo2, Co1 and Co2 are shown in FIG. 5. Wherein the operating phase of the exemplary signal timing diagram in fig. 5 corresponds to the operating state of the switched capacitor integrator 10, the beginning of the operating phase comprising a reset phase of a predetermined time.
As shown in fig. 5, when the signal EN is high, the switched capacitor integrator 10 enters an operating state, and when the signal EN is low, the switched capacitor integrator 10 is in a non-operating state. Those skilled in the art will appreciate that this is merely exemplary, and for convenience of the following description, the technical solution of the present application may also set the signal EN to be opposite to the example in fig. 5 as needed, that is, the switched capacitor integrator 10 enters the working state when it is set as the signal EN is low, and the switched capacitor integrator 10 enters the non-working state when the signal EN is high. Or a pulse signal that sets the signal EN to a certain level as needed.
The description is continued with fig. 5 as an example.
An initial stage: in the initial state, no signal EN is fed, and the reset control circuit and the clock circuit controlled by the enable circuit do not work. At this time, the outputs of the clock circuit and the reset control circuit are both low.
When the signal EN is high, the switched capacitor integrator 10 is in an operating state in which the clock circuit starts operating and outputs two non-overlapping clock signals Φ 1 and Φ 2, and the reset control circuit starts performing control and causes the switched capacitor integrator 10 to include a reset phase, which may be preset to a duration t, as shown in fig. 5.
In the reset phase: the reset control circuit generates reset control signals Res1 and Res2 having a time length t (a preset time length). In this embodiment, the preset time t may be set to 1 ms. It can be understood that, as the performance of the chip increases, the preset time period t should be set as short as possible under the condition that the response speed of the chip can be reached. The output terminal Bo1 outputs a low level signal Res1, and the output terminal Bo2 generates a high level signal Res 2. At this stage, the first sampling switch W1, the second sampling switch W2, the third sampling switch W3, and the fourth sampling switch W4 are turned on or off under the control of the clock signals Φ 1 and Φ 2, and the sampling capacitor C1 samples the external Input signal Input. Thus, in the reset phase, the sampling circuit 101 samples the external input according to the clock signal. However, at this stage, the first reset switch W5 is turned off under the control of the reset control signal Res1, and the sampling result of the sampling capacitor C1 is not fed to the inverting input terminal of the operational amplifier OP 1. Meanwhile, the second reset switch W6 is closed, so that the inverting input terminal and the output terminal of the operational amplifier OP1 are short-circuited, the operational amplifier OP1 forms a unity gain negative feedback, and the static voltage terminal output by the operational amplifier OP1 is rapidly set at the common mode voltage Vcm according to the virtual short principle of the negative feedback of the operational amplifier OP 1.
When the switched capacitor integrator 10 is in the operating state, after the enable control circuit controls the first reset switch W5 to be turned off and the second reset switch W6 to be turned on for the preset time period t, control is performed such that the reset control signal Res1 becomes high level and the reset control signal Res2 becomes low level, and this state is maintained until the switched capacitor integrator 10 stops operating. At this stage, under the control of enable control signals Res1 and Res2, the second reset switch W6 is turned off and the first reset switch W5 is turned on, and the data sampled by the sampling capacitor C1 is sent to C2 and the operational amplifier OP1 for integration.
Since the quiescent voltage at the output of the operational amplifier OP1 is already set at the common mode voltage Vcm at the beginning of the operational phase, no extra time is needed to stabilize. And the preset time t can be very short, and the response speed of the circuit is improved. As can be seen from fig. 6, the response time of the switched capacitor integrator of the present invention is greatly reduced. Therefore, the technical scheme of the application improves the response speed of the switched capacitor integrator.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.
Claims (8)
1. A switched capacitor integrator, comprising:
the sampling circuit is used for sampling external input according to a clock signal and the integrating capacitor is connected between the inverting input end and the output end of the operational amplifier;
it is characterized by also comprising:
the first reset switch is connected between the sampling circuit and the inverting input end of the operational amplifier, and the second reset switch is connected with the integrating capacitor in parallel; and
the reset control circuit is used for controlling the on-off of the first reset switch and the second reset switch;
when the switched capacitor integrator enters a working state, the reset control circuit controls the first reset switch to be switched off and the second reset switch to be switched on for a preset time, and then controls the first reset switch to be switched on and the second reset switch to be switched off.
2. The switched-capacitor integrator of claim 1, further comprising:
a clock circuit that provides a clock signal to the sampling circuit; and
and the enabling circuit provides enabling signals to the clock circuit and the reset control circuit so as to control the switched capacitor integrator to be in the working state or the non-working state.
3. The switched-capacitor integrator of claim 1 or 2, wherein the sampling circuit comprises a sampling capacitor and sampling switches, the sampling switches comprising a first sampling switch, a second sampling switch, a third sampling switch, and a fourth sampling switch,
one end of the first sampling switch is connected with one end of the sampling capacitor, and the other end of the first sampling switch is connected with the external input; one end of the second sampling switch is connected with the other end of the sampling capacitor, and the other end of the second sampling switch is connected with the first reset switch; one end of the third sampling switch is connected with the common end of the first sampling switch and the sampling capacitor, one end of the fourth sampling switch is connected with the common end of the sampling capacitor and the second sampling switch, the other end of the third sampling switch and the other end of the fourth sampling switch are grounded,
the clock circuit outputs two first clock signals and two second clock signals to the sampling switch, and the first clock signals and the second clock signals are two non-overlapped clock signals, so that the switched capacitor integrator is used as an in-phase switched capacitor integrator or an anti-phase switched capacitor integrator.
4. The switched-capacitor integrator of claim 3,
the clock circuit respectively inputs a first clock signal to the first sampling switch and the fourth sampling switch and respectively inputs a second clock signal to the second sampling switch and the third sampling switch, so that the switched capacitor integrator is used as an in-phase switched capacitor integrator; alternatively, the first and second electrodes may be,
the clock circuit inputs a first clock signal to the first sampling switch and the second sampling switch respectively and inputs a second clock signal to the third sampling switch and the fourth sampling switch respectively, so that the switched capacitor integrator serves as an inverse switched capacitor integrator.
5. A method of controlling a switched capacitor integrator as claimed in any one of claims 1 to 4,
outputting a clock signal to the sampling circuit to cause the sampling circuit to perform sampling on an external input according to the clock signal;
control signals are output to the first reset switch and the second reset switch to control the on-off of the first reset switch and the second reset switch,
when the switched capacitor integrator enters a working state, control signals are respectively output to the first reset switch and the second reset switch, so that after the first reset switch is turned off and the second reset switch is turned on for a preset time, the first reset switch is turned on and the second reset switch is turned off.
6. The control method of claim 5, wherein the method further comprises:
and controlling the switched capacitor integrator to be in the working state or the non-working state by sending enable signals to the clock circuit and the reset control circuit.
7. The control method of claim 6, wherein the sampling circuit comprises a sampling capacitor and sampling switches, the sampling switches comprise a first sampling switch, a second sampling switch, a third sampling switch, and a fourth sampling switch,
the method further comprises the following steps: and inputting two first clock signals and two second clock signals into the sampling circuit to enable the switched capacitor integrator to be used as an in-phase switched capacitor integrator or an anti-phase switched capacitor integrator, wherein the first clock signals and the second clock signals are two non-overlapped clock signals.
8. The control method of claim 7, wherein the sampling circuit comprises a sampling capacitor, a first sampling switch, a second sampling switch, a third sampling switch, a fourth sampling switch, and
when the sampling circuit is connected in the following structure: one end of the first sampling switch is connected with one end of the sampling capacitor, and the other end of the first sampling switch is connected with the external input; one end of the second sampling switch is connected with the other end of the sampling capacitor, and the other end of the second sampling switch is connected with the first reset switch; one end of the third sampling switch is connected with the common end of the first sampling switch and the sampling capacitor, one end of the fourth sampling switch is connected with the common end of the sampling capacitor and the second sampling switch, the other end of the third sampling switch and the other end of the fourth sampling switch are grounded,
inputting a first clock signal to the first sampling switch and the fourth sampling switch and a second clock signal, which is non-overlapped with the first clock signal, to the second sampling switch and the third sampling switch, so that the integrator functions as an in-phase switched capacitor integrator; or
Inputting a first clock signal to the first sampling switch and the second sampling switch and a second clock signal complementary to the first clock signal to the third sampling switch and the fourth sampling switch, so that the integrator functions as an inverted switched capacitor integrator.
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Effective date of registration: 20210429 Address after: No.180-6, Linghu Avenue, Taihu International Science and Technology Park, Xinwu District, Wuxi City, Jiangsu Province, 214135 Applicant after: China Resources micro integrated circuit (Wuxi) Co., Ltd Address before: 518040 8a, block a, Tianxiang building, Tian'an Digital City, Futian District, Shenzhen City, Guangdong Province Applicant before: CHINA RESOURCES SEMICONDUCTOR (SHENZHEN) Co.,Ltd. |