CN111277149B - Capacitor voltage optimization control method for modular multilevel converter - Google Patents
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/36—Arrangements for transfer of electric power between ac networks via a high-tension dc link
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/0074—Plural converter units whose inputs are connected in series
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/60—Arrangements for transfer of electric power between AC networks or generators via a high voltage DC link [HVCD]
Abstract
The invention provides a capacitance-voltage optimization control method of a modular multilevel converter, which is characterized in that the capacitor voltages of submodules are sequenced based on a multipath balance merging sequencing algorithm of a patrician tree, and the comparison times of single sequencing are optimized, so that the defect that the calculation amount of the existing algorithm is large is overcome, then the maximum voltage deviation ratio among the submodules is introduced, the capacitor-voltage sequencing frequency and the calculation amount of the submodules are further reduced, and the control performance meets the requirement of MMC capacitor-voltage balance.
Description
Technical Field
The invention relates to the technical field of flexible direct current transmission, in particular to a capacitor voltage optimization control method of a modular multilevel converter.
Background
Modular Multilevel Converter (MMC) is a new voltage source type converter topology proposed by professor r.marquart of army university in united nations, germany.
Compared with the traditional multi-level topological structure, the modular multi-level converter has the advantages of high modularization, low system loss, easiness in realizing high-voltage multi-level output, back-to-back power conversion, high reliability and the like, and wins a wide market.
The capacitor voltage balance control of the pin modular multilevel converter system is the primary condition for popularizing the flexible direct current transmission technology of the voltage source converter. The unbalance of the capacitance voltage on the MMC direct current side can cause irregular bridge arm current and the disorder of switching-in and switching-out of the sub-modules, and the sub-module switch devices are burnt when the condition is serious, so that the stability of the power grid side is influenced.
When the MMC is applied to the high-voltage field, the traditional method is simple in principle and easy to realize, but the switching frequency is too high, and the calculation amount is large. When the voltage level is improved, the output of the level number is increased, the number of the sub-modules is increased rapidly, hundreds of sub-modules are required to be connected in series, the sequencing operation amount of the traditional method is exponentially increased, a large amount of processor resources are occupied, and the switching of a switching device is too frequent. Therefore, research on optimization of the MMC capacitor voltage balance control algorithm is needed.
Disclosure of Invention
The invention aims to provide a capacitor voltage optimization control method of a modular multilevel converter, which is based on a multipath balance merging and sorting algorithm of a patrician tree, reduces the merging and comparing times and improves the efficiency of the merging algorithm.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows: a capacitor voltage optimization control method for a modular multilevel converter comprises the following steps:
s1, supposing that the quantity of sub-modules of each bridge arm of the MMC is K, and calculating to obtain the quantity N of sub-modules required to be put into the bridge arm at present through a multi-path balance merging and sorting algorithm based on a patrician tree;
s2, a multi-path balanced merging and sorting method based on the patrician tree is adopted, the first element of each path in the K path merging forms a patrician tree, the node at the top is stored as a final winner, after the minimum value is output, the value of the leaf node at the bottom is only updated, the node is continuously compared with the elements represented by the parent nodes of the node, the patrician is left in the parent nodes, the winner continues to perform upward comparison, and the rest is repeated, so that the merging operation of the K path is finally completed;
s3, aiming at a single sorting process, a re-sorting optimization merging sorting process is not needed, the ordered capacitor voltage is divided into an input group T and a cut-out group R, the two groups are ordered at the moment, the capacitor voltage of the input sub-module is changed after the next period, and the positive and negative of the changed voltage are determined by the current direction of the bridge arm;
s4, sampling the capacitor voltage of the sub-modules in the input group and the bridge arm current in real time, calculating the number N of the sub-modules required to be input according to the sampling value, comparing the number M of the sub-modules in the previous period, and judging whether the capacitor voltage sequence of the sub-modules in the current control period needs to be sequenced or not;
s5, when M = N, calculating voltage deviation proportion and performing reordering judgment according to the direction of bridge arm current;
if the sorting is not needed, keeping the output pulse unchanged according to the existing sorting result;
when the merging operation needs to be executed, traversing the capacitor voltage in the period, correcting the capacitor voltage and waiting for new sequencing;
and S6, outputting the trigger pulse of the current submodule control period according to the current input quantity of the submodules, the bridge arm current and the sequencing result.
In step S2 of the capacitor voltage optimization control method of the modular multilevel converter, a sequencing interval is divided into a plurality of equal cells, then the cells are sequenced in parallel, and finally all the sequenced cells are merged into an ordered sequence by a merging method.
In the capacitor voltage optimization control method of the modular multilevel converter, the sequencing interval is divided into 2 K And (4) a small interval.
In step S5 of the capacitor voltage optimization control method of the modular multilevel converter, when the bridge arm current is positive, the sub-modules are put in according to the ascending order, the capacitor voltage of the put-in module rises after a period of operation, and the voltage rise deviation ratio at the moment is U1% when the maximum capacitor voltage in K modules is exceeded;
when the bridge arm current is negative, the submodules are put into the group in a descending order, after a period of operation, the capacitor voltage of the submodules put into the group is reduced, and when the minimum capacitor voltage of the K modules is lower than the minimum capacitor voltage of the K modules, the voltage at the moment is reduced by a deviation proportion U2%;
and when M is not equal to N, keeping the output pulse unchanged according to the existing sorting result.
Compared with the existing MMC capacitor voltage balance control method, the optimization control method has the following beneficial effects: the method adopts a patroller tree multi-path balance merging and sorting algorithm with optimal comprehensive performance, has stable time complexity and is not influenced by data chaos. The merge sort has a plurality of recursive calls which do not have an "overlap subproblem" and can be performed without interference. And a multi-path balance merging and sorting framework is adopted to solve a plurality of subproblems in parallel, so that the operation speed can be further improved.
The maximum voltage deviation proportion value is beneficial to avoiding repeated sequencing in a sampling period of voltage micro-change of the MMC control system, the calculation amount of the algorithm can be greatly reduced, and the switching trigger frequency is reduced.
The method has the advantages that the patricial tree is selected to realize multi-path balanced merging and sorting to carry out MMC voltage-sharing sorting aiming at the problems of multiple sorting times, large computation amount, high switch triggering frequency and the like of the traditional sorting algorithm, the switching device input and output times are greatly improved according to the characteristics of an MMC control system, the computation amount of a processor is relieved, the algorithm execution efficiency is high, the stable algorithm time complexity is realized, and the method can be applied to a modular multilevel system with a plurality of submodules.
Drawings
Fig. 1 is a schematic diagram of the topology of the modular multilevel converter of the present invention.
Fig. 2 is a schematic diagram of a topological half-bridge submodule structure of the modular multilevel converter according to the invention.
FIG. 3 is a schematic flow diagram of the process of the present invention.
FIG. 4 is a flow chart of the serial merge sort algorithm.
FIG. 5 is a flow chart of a multi-way balanced merge sort algorithm.
Detailed Description
The technical solution adopted by the present invention will be further explained with reference to the schematic drawings.
Fig. 1 and fig. 2 are schematic diagrams of a modular multilevel converter topology and a submodule half-bridge topology according to the present invention, respectively. In the figure, an MMC is connected to a direct current bus in a parallel mode, the MMC is composed of six three-phase bridge arms, and each phase of bridge arm is formed by connecting a plurality of submodules with the same parameters in series with an inductor. Each sub-module consists of two diodes, two IGBTs and an energy storage capacitor. When the sub-module is in the running state of the upper pipe, the controller selects to access the energy storage capacitor; on the contrary, when the sub-module is in a lower tube running state, the controller selects to switch off the energy storage capacitor. The number of the sub-modules of each phase of upper and lower bridge arms in the same period is unchanged. The number of inputs and outputs of the sub-modules is controlled to output a desired multi-level waveform.
For a modular multilevel converter system, the capacitor voltage balance control is a primary condition for obtaining a desired output multilevel waveform. The unbalance of MMC direct current side capacitance voltage can cause that bridge arm current is irregular and submodule pieces are thrown into and cut out disorderly, burn submodule piece switching device when serious, cause the influence to electric wire netting side stability.
The present invention is described in detail below with reference to fig. 3-5.
Referring to fig. 3, a method for optimally controlling the capacitor voltage of a modular multilevel converter is as follows: assuming that the number of the submodules of each bridge arm of the MMC is K, calculating to obtain the number N of the submodules required to be input by the bridge arm at present through a multipath balance merging and sorting algorithm based on an patroller tree. The method comprises the steps of firstly dividing a sub-number array of K elements to be sorted into two sub-number arrays with basically equal node numbers, then sorting each sub-number array, and finally combining the two sorted sub-number arrays into one number array. In the period of sorting the sub-number sequence, the sub-number sequence can be decomposed into two sub-number sequences with the same node number, when the sub-number sequence is small enough, other methods such as insertion sorting can be adopted to sort the sub-number sequence, then merging operation is carried out on the sorted sub-number sequences, and finally the whole table is sorted. The sorting method is a serial merging sorting algorithm, and the flow chart of the algorithm is shown in FIG. 4.
The parallel merging method is adopted, and because the merging and sorting of each data interval is independent, no dependency relationship exists. Therefore, merge sort is a sort algorithm that is easily parallelized. The scheme is that the sorting interval is divided into a plurality of equal small intervals, then the small intervals are sorted in parallel, and finally all the sorted small intervals are merged into an ordered sequence by a merging method. Since the merging is layer-by-layer upward, the interval needs to be divided into 2 k-th order cell intervals, so that the 2 k-th order cell intervals can be merged into 2 k-1 order cell intervals when merging in the first period. Therefore, the k rounds are merged into an ordered large interval, the problem is solved by multi-path balance, and the speed can be further improved. The flow chart of the multi-path balanced merging and sorting algorithm is shown in FIG. 4.
For parallel merging, the influence on the overall performance is to select a K value in K path balanced merging, namely, the aim of reducing merging times is achieved by increasing the K value in the K path balanced merging so as to improve the efficiency of the algorithm. However, if the K value is increased without restriction, the time for internal merging increases, and the number of comparisons increases.
The invention provides a multi-path balanced merging and sorting algorithm based on a patrinia tree, which solves the dilemma of the existing merging technology and ensures that the internal merging efficiency of the K value cannot be influenced. In the loser tree, the father node records the losers of the game played by the left and right child nodes, and the winner takes part in the next round of game.
The method for realizing multi-path balanced merging of the patrician tree comprises the following steps: the first element of each path in the K-path merging is constructed into an patroller tree, taking a 5-path merged patroller tree as an example, the top node is stored as the final winner, after the minimum value is output, the value of the comparison leaf node at the bottom is only needed to be updated, the node is continuously compared with the elements represented by the parent nodes of the node, the patroller is left in the parent nodes, and the winner continues to compare upwards. And analogizing in turn, and finally completing the merging operation of the K paths.
The present invention proposes optimizing the merge sort process without reordering for a single sort process.
And dividing the ordered capacitor voltage into an input group T and a cut-out group R, wherein the two groups are ordered at the moment, the capacitor voltage of the input submodule is changed after the next period, and the positive voltage and the negative voltage of the changed voltage are determined by the current direction of the bridge arm. After a period of operation, the overall voltage value has changed, but the two groups of the input group T and the cut-out group R are still in an ordered sequence.
Sampling the capacitor voltage of the sub-modules in the input group and the bridge arm current in real time, calculating the number N of the sub-modules required to be input according to the sampling value, comparing the number M of the sub-modules in the previous period, and judging whether the sub-module capacitor voltage sequence of the current control period needs to be sequenced or not.
And when M = N, performing voltage deviation proportion calculation and reordering judgment according to the direction of the bridge arm current. When the bridge arm current is positive, the submodules are put into the group in an ascending order, the capacitor voltage of the submodules put into the group is increased after a period of operation, and the voltage increase deviation ratio at the moment is U1% when the maximum capacitor voltage in the K modules is exceeded; and when the bridge arm current is negative, the submodules are put into the group in a descending order, after a period of operation, the capacitor voltage of the submodules put into the group is reduced, and when the minimum capacitor voltage of the K modules is lower than the minimum capacitor voltage of the K modules, the voltage at the moment is reduced by a deviation proportion U2%.
When M is not equal to N, keeping the output pulse unchanged according to the existing sequencing result; when the merging operation needs to be executed, the capacitor voltage in the period is traversed, and correction is carried out until the new sequence is obtained.
And outputting the trigger pulse of the current submodule control period according to the current input quantity of the submodules, the bridge arm current and the sequencing result.
According to the actual MMC engineering application, the deviation rate of the capacitor voltage of the neutron module of each phase of bridge arm is lower than 5%, and the MMC can work normally. The method has the advantages that whether reordering is needed or not is judged by utilizing the capacitor voltage deviation rate of the sub-module in each phase of bridge arm, the switching-in and switching-out times of the switching device are improved, the calculated amount of a processor is relieved, and the algorithm execution efficiency is high.
The invention provides a capacitor voltage optimization control method of a modular multilevel converter, aiming at the problems of more sorting times, large operation amount, high switch triggering frequency and the like of the traditional sorting algorithm, the control system selects a multi-path balance merging sorting algorithm based on an patroller tree to carry out MMC voltage-sharing sorting, and the comparison times after the patroller tree is introduced are irrelevant to K, so that the merging and comparison times are reduced, and the efficiency of the merging algorithm is improved. According to the characteristics of the MMC control system, the used maximum voltage deviation proportion value is beneficial to the MMC control system to avoid repeated sequencing in the sampling period of voltage micro-change, the calculation amount of an algorithm can be greatly reduced, and the switching trigger frequency is reduced. The switching device switching-in and switching-out times are greatly improved, the calculated amount of a processor is relieved, the algorithm execution efficiency is high, the algorithm time complexity is stable, and the method can be applied to a modular multilevel system with a large number of sub-modules.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (4)
1. A capacitor voltage optimization control method of a modular multilevel converter is characterized by comprising the following steps:
s1, supposing that the number of sub-modules of each bridge arm of the MMC is K, calculating to obtain the number N of the sub-modules required to be put into the bridge arm at present through a multi-path balance merging and sorting algorithm based on an patroller tree;
s2, adopting a multi-path balanced merging and sorting method based on an patroller tree to enable the first element of each path in the K path merging to form an patroller tree, storing the node at the top as a final winner, outputting the minimum value, updating the value of the comparison leaf node at the bottom, enabling the node to be continuously compared with the elements represented by the parent nodes of the node, enabling the patroller to remain in the parent nodes, continuing upward comparison by the winner, and so on to finally complete the merging operation of the K path;
s3, aiming at a single sorting process, a re-sorting optimization merging sorting process is not needed, the ordered capacitor voltage is divided into an input group T and a cut-out group R, the two groups are ordered at the moment, the capacitor voltage of the input sub-module is changed after the next period, and the positive and negative of the changed voltage are determined by the current direction of the bridge arm;
s4, sampling capacitor voltage of the sub-modules in the input group and bridge arm current in real time, calculating the number N of sub-modules required to be input according to the sampling value, comparing the number M of the sub-modules in the previous period, and judging whether the sub-module capacitor voltage sequence of the current control period needs to be sequenced or not;
s5, when M = N, calculating voltage deviation proportion and performing reordering judgment according to the direction of bridge arm current;
if the sorting is not needed, keeping the output pulse unchanged according to the existing sorting result;
when the merging operation needs to be executed, traversing the capacitor voltage in the period, correcting the capacitor voltage and waiting for new sequencing;
and S6, outputting the trigger pulse of the current submodule control period according to the current input quantity of the submodules, the bridge arm current and the sequencing result.
2. The capacitor voltage optimization control method of the modular multilevel converter according to claim 1, wherein in the step S2, the sorting interval is divided into a plurality of equal cells, then the cells are sorted in parallel, and finally all the sorted cells are merged into an ordered sequence by a merging method.
3. The capacitor voltage optimization control method of modular multilevel converter according to claim 2, wherein the sorting interval is divided into 2 K And (4) a small interval.
4. The capacitor voltage optimization control method of the modular multilevel converter according to claim 2, wherein in the step S5, when the bridge arm current is positive, the sub-modules are put in ascending order, after a period of operation, the capacitor voltage of the put-in group module rises, and when the maximum capacitor voltage in the K modules exceeds the maximum capacitor voltage, the voltage rise deviation ratio at the moment is U1%;
when the bridge arm current is negative, the submodules are put into the group in a descending order, after a period of operation, the capacitor voltage of the submodules put into the group is reduced, and when the minimum capacitor voltage of the K modules is lower than the minimum capacitor voltage of the K modules, the voltage at the moment is reduced by a deviation proportion U2%;
and when M is not equal to N, keeping the output pulse unchanged according to the existing sorting result.
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