CN111276499B - Display substrate, preparation method thereof and display device - Google Patents

Display substrate, preparation method thereof and display device Download PDF

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Publication number
CN111276499B
CN111276499B CN202010224210.4A CN202010224210A CN111276499B CN 111276499 B CN111276499 B CN 111276499B CN 202010224210 A CN202010224210 A CN 202010224210A CN 111276499 B CN111276499 B CN 111276499B
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substrate
layer
hole
display
thin film
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CN111276499A (en
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刘宁
刘军
程磊磊
李广耀
周斌
闫梁臣
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The embodiment of the invention provides a substrate for display, a preparation method thereof and a display device, relates to the technical field of display, and can solve the problem that more manufacturing processes are needed when the substrate for display is manufactured; the insulating layer is provided with a first via hole; the surface of the flat layer far away from the insulating layer is provided with a groove, a second through hole is formed in the portion, located below the groove, of the flat layer, and the first through hole is communicated with the second through hole.

Description

Display substrate, preparation method thereof and display device
Technical Field
The application relates to the technical field of display, in particular to a substrate for display, a preparation method of the substrate and a display device.
Background
A top gate TFT (Thin Film Transistor) has a short channel, so that an on-state current Ion thereof can be effectively increased, thereby significantly improving a display effect and effectively reducing power consumption. In addition, since the overlap area between the gate and the source/drain of the top gate TFT is small, the parasitic capacitance generated is small, and the possibility of occurrence of defects such as GDS is reduced. The top gate type TFT has been receiving more and more attention because of its remarkable advantages as described above.
Disclosure of Invention
The embodiment of the application adopts the following technical scheme:
in a first aspect, a substrate for display includes: the device comprises a substrate, an insulating layer arranged on the substrate, and a flat layer arranged on one side of the insulating layer far away from the substrate; the insulating layer is provided with a first via hole; the surface of the flat layer far away from the insulating layer is provided with a groove, a second through hole is formed in the portion, located below the groove, of the flat layer, and the first through hole is communicated with the second through hole.
In some embodiments, the substrate for display further comprises: a thin film transistor disposed between the substrate and the insulating layer; the first polar plate is arranged on the bottom surface of the groove, and the second polar plate is arranged on one side, close to the substrate, of the insulating layer; the first polar plate penetrates through the second through hole and the first through hole to be electrically connected with the first pole of the thin film transistor, and the second polar plate is electrically connected with the grid of the thin film transistor; wherein the first plate and the second plate form two plates of a capacitor.
In some embodiments, the depth of the groove is 80% to 95% of the thickness of the planar layer.
In some embodiments, an orthographic projection of the second via on the substrate proximate an edge of the substrate is inward of an orthographic projection of the first via on the substrate distal from an edge of the substrate.
In some embodiments, an orthographic projection of the edge of the second via hole near the substrate on the substrate coincides with an orthographic projection of the edge of the first via hole far from the substrate on the substrate.
In some embodiments, the substrate for display further comprises: an electrode, and a color filter layer disposed between the insulating layer and the planarization layer; the electrode is connected with the first polar plate, the same layer of the electrode is made of the same material, and the color filter layer comprises a filter pattern; the orthographic projection of the electrode on the substrate and the orthographic projection of one of the filtering patterns on the substrate have an overlapping area.
In some embodiments, the substrate for display further comprises: a metal pattern disposed between the substrate and the thin film transistor; an orthographic projection of an active layer of the thin film transistor on the substrate is within an orthographic projection of the metal pattern on the substrate; the metal pattern is electrically connected to a first electrode of the thin film transistor, and the metal pattern and the second electrode have an overlapping area.
In a second aspect, a display device is provided, which includes the above display substrate.
In a third aspect, a method for preparing a substrate for display is provided, including: sequentially forming a first film and a second film on the substrate, the second film including a positive type photosensitizer; carrying out mask exposure and development on the second film to form a groove on the surface of the second film far away from the first film, and forming a second through hole at the part under the groove of the second film to obtain a flat layer; and etching the part of the first film exposed by the second via hole to form an insulating layer with a first via hole.
In some embodiments, the method of making further comprises: after the insulating layer is formed, ashing treatment is performed on the planarization layer to obtain a treated planarization layer.
The embodiment of the invention provides a substrate for display, a preparation method thereof and a display device, wherein the substrate for display comprises a substrate, an insulating layer arranged on the substrate, and a flat layer arranged on one side of the insulating layer, which is far away from the substrate, wherein the flat layer comprises a positive photosensitive agent; the insulating layer is provided with a first via hole; the flat layer is provided with a groove on the surface far away from the insulating layer, a second through hole is arranged in the portion, located below the groove, of the flat layer, and the first through hole is communicated with the second through hole. In the embodiment of the invention, the flat layer comprises the positive photosensitive agent, so that the flat layer not only has the function of flattening, but also has the function of photoresist, when the first through hole is formed on the insulating layer, a layer of photoresist does not need to be coated on the insulating layer, and the groove, the first through hole and the second through hole can be formed through a one-time composition process, so that a one-time mask exposure process can be reduced, namely, the manufacturing process is simplified.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an lcd panel according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electroluminescent display panel according to an embodiment of the present invention;
fig. 4 is a first schematic structural diagram of a substrate for display according to an embodiment of the present invention;
fig. 5 is a second schematic structural diagram of a substrate for display according to an embodiment of the present invention;
FIG. 6 is an enlarged schematic view of portion A in FIG. 5 according to an embodiment of the present invention;
fig. 7 is a third schematic structural diagram of a substrate for display according to an embodiment of the present invention;
FIG. 8 is an enlarged view of portion B of FIG. 7 according to the present invention;
fig. 9 is a schematic flow chart of a method for manufacturing a substrate for display according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a mask exposure process performed on a second film according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a structure for forming a planarization layer according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of a structure for forming an insulating layer according to an embodiment of the present invention;
fig. 13 is a schematic diagram of a planar layer structure after a forming process according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Embodiments of the present invention provide a Display device, which is not limited to the type of the Display device, and may be a Liquid Crystal Display (LCD) device or an electroluminescence Display device. In the case that the display device is an electroluminescent display device, the electroluminescent display device may be an Organic Light-Emitting display device (OLED) or a Quantum Dot electroluminescent display device (QLED).
In addition, the display device provided in the embodiment of the present invention may be any product or component having a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, and a navigator, which is not limited in this respect.
As shown in fig. 1, the main structure of the display device includes a frame 1, a cover plate 2, a display panel 3, and other components such as a circuit board 4. In the case where the display device is a liquid crystal display device, the display device further includes a backlight assembly. Here, the display panel 3 may be a flexible display panel or a rigid display panel. In the case where the display panel 3 is a flexible display panel, the display device is a flexible display device.
The longitudinal section of the frame 1 is U-shaped, the display panel 3, the circuit board 4 and other accessories are all arranged in the frame 1, the circuit board 4 is arranged below the display panel 3 (namely, the back surface, the surface deviating from the display surface of the display panel 3), and the cover plate 2 is arranged on one side of the display panel 3 far away from the circuit board 4. In the case where the display device is a liquid crystal display device including a backlight assembly, the backlight assembly is disposed between the display panel 3 and the circuit board 4.
In the case where the display device is a liquid crystal display device, the display panel 3 is a liquid crystal display panel. In some embodiments, as shown in fig. 2, the display panel 3 includes a substrate 30 for display and a liquid crystal layer 31 provided on the substrate 30 for display; the display substrate 30 includes the Color filter layer 301 provided on the substrate 300, and in this case, the display substrate 30 is an Array substrate, which may also be referred to as a Color filter on Array (COA) substrate.
In the case where the display device is an electroluminescence display device, the display panel 3 is an electroluminescence display panel. As shown in fig. 3, the display panel 3 includes a display substrate 30 and an encapsulating layer 32 for encapsulating the display substrate 30. Here, the encapsulation layer 32 may be an encapsulation film or an encapsulation substrate. In some embodiments, as shown in fig. 3, the display substrate 30 includes a color filter layer 301 disposed on a substrate 300, in which case the display device is a bottom emission type display device.
The embodiment of the invention also provides a display substrate 30, which can be applied to the display device. As shown in fig. 4, the display substrate 30 includes a substrate 300, an insulating layer 302 provided on the substrate 300, and a planarization layer 303 provided on a side of the insulating layer 302 remote from the substrate 300, the planarization layer 303 including a positive-working photosensitive agent. The insulating layer 302 is provided with a first through hole 3021, the surface of the flat layer 303 far away from the insulating layer 302 is provided with a groove 3031, a second through hole 3032 is arranged in the part, located at the lower part of the groove 3031, of the flat layer 303, and the first through hole 3021 and the second through hole 3032 are communicated.
Here, the material of the insulating layer 302 may be an organic material or an inorganic material. The organic material is not limited, and may be, for example, PMMA (Polymethyl methacrylate). The inorganic material is not limited, and may be one or more of SiNx (silicon nitride), siOx (silicon oxide), or SiOxNy (silicon oxynitride), for example.
As shown in fig. 4, a portion of the region defined in the planarization layer 303 for the recess 3031 has a certain depth in the thickness direction of the planarization layer 303 and a certain thickness on the surface thereof close to the insulating layer 302.
In the embodiment of the present invention, the planarization layer 303 includes a Resin (Resin) in addition to the positive type photosensitive agent. The resin is not limited to the resin, and the planarizing layer 303 can have a planarizing effect. In some embodiments, the resin may be, for example, an organosiloxane resin, which may provide good planarization of the planarization layer 303 due to its good leveling properties.
It should be understood that since the planarization layer 303 includes a positive type photosensitive agent, when performing mask exposure, the planarization layer 303 is exposed in the region where the recess 3031 is to be formed and the region where the second via hole 3032 is to be formed (i.e., light can be irradiated through the clear region on the mask plate), and the remaining region is shielded (i.e., shielded by the non-clear region on the mask plate), and as can be seen with reference to fig. 3, the depth of the recess 3031 formed in the planarization layer 303 is smaller than the depth of the second via hole 3032 formed, so that half exposure is performed in the region where the recess 3031 is to be formed, and full exposure is performed in the region where the second via hole 3032 is to be formed; after development, the exposed regions are developed away (i.e., forming the recesses 3031 and the second vias 3032), and the unexposed regions remain. The recess 3031 and the second via 3032 can be formed by exposing and developing through a mask once, and then the insulating layer 302 is subjected to an etching process to form the first via 3021, i.e., the recess 3031, the first via 3021 and the second via 3032 can be formed by a patterning process once.
On this basis, the positive-working sensitizer is not limited. The positive sensitizer is a photoacid generator, and may be, for example, tert-butylphenyl iodonium salt perfluorooctane sulfonate (TBI-PFOS), triphenylsulfonium perfluorobutane sulfonate (TPS-PFBS), or the like. Examples of the resin include Polyethylene (PE), polyvinyl chloride (PVC), polystyrene (PS), polypropylene (PP), and ABS resin (ABC). Further, the solvent may be, for example, any one or a combination of ethylene glycol monoacetate, ethylene glycol methyl ether acetate, N-methylpyrrole, propylene glycol, ethylene glycol alkyl ether acetate, propylene glycol monomethyl ether acetate, ethoxyethyl acetate, dimethoxyacetaldehyde, propylene glycol methyl ether acetate, ethyl 3-ethoxypropionate, propylene glycol methyl ether (PM), and ethylene glycol ethyl acetate. The embodiment of the invention is not limited to this.
Based on the above, since the planarization layer 303 includes the positive type photosensitive agent in the embodiment of the present invention, that is, the planarization layer 303 not only has the planarization function, but also has the function of the photoresist, when the first via 3021 is formed on the insulating layer 302, a layer of photoresist does not need to be coated on the insulating layer 302, and the recess 3031, the first via 3021 and the second via 3032 can be formed through a single patterning process, so that a Mask exposure (Mask) process can be reduced, that is, the manufacturing process can be simplified.
In some embodiments, as shown in fig. 5, the display substrate 30 further includes a thin film transistor 304 disposed between the substrate 300 and the insulating layer 302, a first plate 305 disposed on the bottom surface of the recess 3031, and a second plate 306 disposed on the insulating layer 302 on the side close to the substrate 300; the first electrode plate 305 penetrates through the second via 3032 and the first via 3021 to be electrically connected to the first electrode 3041 of the thin film transistor 304, and the second electrode plate 306 is electrically connected to the gate 3042 of the thin film transistor 304; wherein the first plate 305 and the second plate 306 constitute the two plates of the capacitor.
The first electrode 3041 is not limited, and the first electrode 3041 may be a source or a drain. It is to be understood that the thin film transistor 304 further includes a second electrode 3043, and in the case where the first electrode 3041 is a source electrode, the second electrode 3043 is a drain electrode; in the case where the first electrode 3041 is a drain, the second electrode 3043 is a source.
As shown in fig. 5, the source and drain are insulated from each other. The material of the source and drain electrodes is not limited. The material of the source and drain may be copper-based metal, for example, copper (Cu), copper molybdenum alloy (Cu/Mo), copper titanium alloy (Cu/Ti), copper molybdenum titanium alloy (Cu/Mo/Ti), copper molybdenum tungsten alloy (Cu/Mo/W), copper molybdenum niobium alloy (Cu/Mo/Nb), etc.; alternatively, the metal may be a chromium-based metal, such as a chromium-molybdenum alloy (Cr/Mo), a chromium-titanium alloy (Cr/Ti), a chromium-molybdenum-titanium alloy (Cr/Mo/Ti), etc., or other suitable materials, which is not limited in this respect.
It should be noted that, when the first plate 305 and the second plate 306 form two plates of a capacitor, the larger the facing area between the two plates is, the smaller the distance between the two plates is, i.e., the larger the capacitance formed by the capacitor is.
In some embodiments, the depth of the recess 3031 is 80% to 95% of the thickness of the planarization layer 303.
Here, the depth of the recess 3031 may be, for example, 80%, 85%, 90%, 95% of the thickness of the planarization layer 303.
In the embodiment of the present invention, since the depth of the groove 3031 is 80% to 95% of the thickness of the planarization layer 303, that is, the thickness of the planarization layer 303 located inside the groove 3031 is 5% to 20% of the thickness of the planarization layer 303 located outside the groove 3031, that is, the distance between the first electrode plate 305 and the second electrode plate 306 is small, the capacitance formed by the first electrode plate 305 and the second electrode plate 306 can be relatively large, and the second electrode plate 306 is electrically connected to the gate 3042 of the thin film transistor 304, so that the capacitance finally loaded on the thin film transistor 304 is relatively large, and the brightness of light emitted by the light emitting layer can be ensured.
Considering that if the depth of the recess 3031 is set to be deeper, for example, the depth of the recess 3031 is 95% of the thickness of the planarization layer 303, that is, the thickness of the planarization layer 303 located inside the recess 3031 is 5% of the thickness of the planarization layer 303 located outside the recess 3031, so that the thickness of the planarization layer 303 located inside the recess 3031 is too thin, further causing the lower surface of the first plate 305 to be uneven, that is, the lower surface of the first plate 305 to be uneven, and when the lower surface of the first plate 305 is uneven, the facing area of the first plate 305 and the second plate 306 is affected, that is, the distance between the first plate 305 and the second plate 306 is affected, and the capacitance of the capacitor is further affected, thereby affecting the brightness of the light emitted by the light emitting layer. If the depth of the recess 3031 is set to be shallow, for example, the depth of the recess 3031 is 80% of the thickness of the flat layer 303, that is, the thickness of the flat layer 303 located in the recess 3031 is 20% of the thickness of the flat layer 303 located outside the recess 3031, the thickness of the flat layer 303 located in the recess 3031 is too thick, that is, the facing areas of the first plate 305 and the second plate 306 are reduced, the distance between the first plate 305 and the second plate 306 is increased, and thus the capacitance generated by the capacitor is reduced, and finally the brightness of the light emitted by the light emitting layer is reduced. Based on this, in some embodiments, the depth of the recess 3031 is 90% of the thickness of the planar layer 303, i.e., the thickness of the planar layer 303 located within the recess 3031 is 10% of the thickness of the planar layer 303 located outside the recess 3031.
As shown in fig. 5, the thin film transistor 304 further includes an active layer 3044 and an interlayer dielectric layer 3045 disposed between the first electrode 3041, the second electrode 3043 and the active layer 3044. The active layer 3044 includes a first conductor region 3044a, a second conductor region 3044b, and a channel region 3044c between the first conductor region 3044a and the second conductor region 3044 b. As shown in fig. 5, a first electrode 3041 is connected to the first conductor region 3044a through a via of an interlayer dielectric layer 3045, and a second electrode 3043 is connected to the second conductor region 3044b through a via of an interlayer dielectric layer 3045.
In some embodiments, the first pole 3041 is a source, and the first conductor region 3044a can also be referred to as a source region; the second electrode 3043 is a drain, and the second conductive region 3044b can also be referred to as a drain region. In other embodiments, the first electrode 3041 is a drain, and the first conductive region 3044a can also be referred to as a drain region; the second electrode 3043 is a source and the second conductor region 3044b can also be referred to as a source region.
As shown in fig. 5, the thin film transistor 304 further includes a gate insulating layer 3046 disposed between the active layer 3044 and the gate electrode 3042.
Here, the material of the gate insulating layer 3046 may be, for example, silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (Al 2O 3), aluminum nitride (AlN), or other suitable materials. In addition, the gate insulating layer 3046 may be formed by a physical Vapor Deposition method, a Chemical Vapor Deposition method (CVD for short), or a coating method.
In some embodiments, as shown in fig. 5, the substrate for display 30 further includes an electrode 307 and a color filter layer 301 disposed between the insulating layer 302 and the planarization layer 303, the color filter layer 301 including a plurality of filter patterns. The electrode 307 is connected to the first plate 305, and has the same material layer, and an orthogonal projection of the electrode 307 on the substrate 300 and an orthogonal projection of a filter pattern on the substrate 300 have an overlapping region.
It is to be understood that, in the case where the substrate 30 for display is applied to the liquid crystal display panel described above, the electrode 307 may be, for example, a pixel electrode; in the case where the display substrate 30 is applied to the above-described electroluminescence display panel, the electrode 307 may be, for example, an anode or a cathode.
In the embodiment of the present invention, the electrode 307 is connected to the first electrode plate 305 and is made of the same material as the first electrode plate 305, so that the electrode 307 and the first electrode plate 305 can be formed at the same time and electrically connected to the first electrode 3041 of the thin film transistor 304 through the first via 3021 and the second via 3032.
As shown in fig. 4, 5, and 6, fig. 6 is an enlarged schematic view of a portion a in fig. 5. The orthographic projection of the second via 3032 on the substrate 300 near the edge of the substrate 300 is within the orthographic projection of the first via 3021 on the substrate 300 away from the edge of the substrate 300.
As can be seen from fig. 4 and 6, the edge of the second via 3032 has a convex portion relative to the edge of the first via 3021, that is, the aperture of the second via 3032 is smaller than that of the first via 3021, so that the electrode 307 and the first plate 305 can be overlapped on the planarization layer 303 through the first via 3021 and the second via 3032, and therefore, the smooth connection between the electrode 307 and the first plate 305 and the first pole 3041 of the thin film transistor 304 can be ensured.
As shown in fig. 7 and 8, fig. 8 is an enlarged schematic view of a portion B in fig. 7. An orthographic projection of the edge of the second via 3032 near the substrate 300 on the substrate 300 coincides with an orthographic projection of the edge of the first via 3021 far from the substrate 300 on the substrate 300.
As can be seen from fig. 8, the edges of the first via 3021 and the second via 3032 are relatively gentle, so that when the electrode 307 and the first plate 305 are overlapped on the planarization layer 303, the problem that the electrode 307 and the first plate 305 are broken at the edges of the first via 3021 and the second via 3032 can be avoided, and therefore, the smooth connection between the electrode 307 and the first plate 305 and the first pole 3041 of the thin film transistor 304 can be further ensured.
In some embodiments, as shown in fig. 5 and 7, the display substrate 30 further includes a metal pattern 308 disposed between the substrate 300 and the thin film transistor 304, the metal pattern 308 is electrically connected to the first electrode 3041 of the thin film transistor 304, the metal pattern 308 and the second electrode 306 have an overlapping region, and an orthographic projection of the active layer 3044 of the thin film transistor 304 on the substrate 300 is within an orthographic projection of the metal pattern 308 on the substrate 300.
Here, the overlapping region between the metal pattern 308 and the second plate 306 may be a partial overlap between the metal pattern 308 and the second plate 306; it is also possible that the metal pattern 308 entirely overlaps the second plate 306.
In the case where the metal pattern 308 and the second plate 306 are all overlapped, for example, the orthographic projection of the second plate 306 on the substrate 300 is within the orthographic projection of the active layer 3044 on the substrate, and since the orthographic projection of the active layer 3044 on the substrate 300 is within the orthographic projection of the metal pattern 308 on the substrate 300, the orthographic projection of the second plate 306 on the substrate 300 can be made within the orthographic projection of the metal pattern 308 on the substrate 300.
The material of the metal pattern 308 is not limited. The material of the metal pattern 308 may be, for example, an opaque metal or alloy such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mu), or the like.
In addition, in the embodiment of the present invention, a metal pattern 308 covers the active layer 3044 of the thin film transistor 304 in a sub-pixel, and at this time, a metal pattern 308 is electrically connected to the first electrode 3041 of the thin film transistor 304 in a sub-pixel; alternatively, one metal pattern 308 may cover the active layer 3044 of the tft 304 in one pixel, and at this time, one metal pattern 308 is electrically connected to the first electrode 3041 of the tft 304 in one pixel, that is, the first electrodes 3041 of the tfts 304 in one pixel share one metal pattern 308.
In the case where one metal pattern 308 covers the active layer 3044 of the thin film transistor 304 within one pixel, the first electrodes 3041 of the thin film transistors 304 within one pixel share one metal pattern 308, so that the metal patterns 308 within one pixel can be formed at the same time, thereby simplifying the manufacturing process.
Since the active layer 3044 of the thin film transistor 304 is made of a semiconductor material, and the performance of the semiconductor material is unstable after being exposed to light (e.g., ambient light), the thin film transistor 304 may generate a negative drift, that is, the threshold voltage of the thin film transistor 304 may change, thereby affecting the operating performance of the thin film transistor 304. In the embodiment of the present invention, since the orthographic projection of the active layer 3044 of the thin film transistor 304 on the substrate 300 is within the orthographic projection of the metal pattern 308 on the substrate 300, that is, the metal pattern 308 covers the active layer 3044 of the thin film transistor 304, the active layer 3044 can be prevented from being affected by light, so as to improve the stability of the thin film transistor 304 and improve the working performance of the thin film transistor 304. And the metal pattern 308 is electrically connected to the first electrode 3041 of the thin film transistor 304, and the metal pattern 308 and the second electrode 306 have an overlapping region, so that a capacitance can be generated between the metal pattern 308 and the second electrode 306, and thus the capacitor can have a larger capacitance, and further the brightness of light emitted by the light emitting layer can be ensured.
Note that, in order to prevent the metal pattern 308 from contacting the first conductor region 3044a and the second conductor region 3044b of the active layer 3044 to cause a short circuit, in some embodiments, the display substrate 30 further includes a buffer layer 309 disposed on the metal pattern 308. On one hand, the buffer layer 309 may planarize the metal pattern 308; on the other hand, the buffer layer 309 may prevent the metal pattern 308 from contacting the active layer 3044.
The embodiment of the invention also provides a preparation method of the substrate 30 for display, which can be used for preparing the substrate 30 for display. As shown in fig. 9, the method for manufacturing the substrate 30 for display includes:
s100, a first thin film 20 and a second thin film 21 are sequentially formed on a substrate 300, the first thin film 21 including a positive type photosensitizer.
In the embodiment of the present invention, before forming the first thin film 20 and the second thin film 30, the method for manufacturing the display substrate 30 further includes: a patterned metal pattern 308, a buffer layer 309, an active layer 3044 and a complete thin film transistor 304 are sequentially deposited and patterned on the substrate 300. Here, the method of forming the complete tft 304 can follow the prior art, and is not described in detail here.
For example, it may further include: the color filter layer 301 is formed, i.e., a plurality of filter patterns of different colors are formed.
In the case where the material of the first thin film 20 is an organic material, the first thin film 20 and the second thin film 21 may be formed by an Ink Jet Printer (IJP). In the case where the material of the first thin film 20 is an inorganic material, the first thin film 20 may be formed by a chemical vapor deposition method, and the second thin film 21 may be formed by an inkjet printing process. Alternatively, the first film 20 and the second film 21 may be formed by coating.
S101, mask exposing and developing the second film 21 to form a recess 3031 on the surface of the second film 21 away from the first film 20, and form a second via 3032 in the portion of the second film 21 under the recess 3031, so as to obtain the planarization layer 303.
As shown in fig. 10, since the planarization layer 303 includes a positive type photosensitive agent, when the second thin film 21 is mask-exposed, a half exposure is performed in a region where the recess 3031 needs to be formed, and a full exposure is performed in a region where the second via 3032 needs to be formed. After the mask exposure, the second film 21 is subjected to a developing process, and as shown in fig. 11, the fully exposed region of the second film 21 is entirely removed by development, and about 90% of the half-exposed region is removed by development, thereby forming a recess 3031 and a second via 3032.
Note that, half exposure is used in a region where the groove 3031 needs to be formed, and when half exposure is performed, the transmittance of the mask blank is inversely proportional to the thickness of the bottom of the groove 3031, that is, when the thickness of the bottom of the groove 3031 is 5% to 20% of the thickness of the planarization layer 303, the transmittance of the mask blank is 80% to 95%.
S102, the portion of the first film 20 exposed by the second via 3032 is etched to form an insulating layer 302 having a first via 3021.
As shown in fig. 12, the first film 20 is subjected to an etching process (HF wet etching) to form a first via hole 3021. Here, an edge of the second via 3032 has a protrusion with respect to an edge of the first via 3021.
In some embodiments, as illustrated in fig. 9, the method of preparing the substrate 30 for display further includes;
s103, after the insulating layer 302 is formed, ashing treatment is performed on the flat layer 303 to obtain a treated flat layer 303.
As shown in fig. 13, the surface of the recess 3031 can be made more flat by performing a slight Ashing (Ashing) process on the planarization layer 303, and the edge of the second via 3032 protruding relative to the first via 3021 (i.e., the Tip angle of the second via 3032) can be eliminated, so that the problem of the electrode 307 and the first plate 305 breaking at the edge of the first via 3021 and the second via 3032 can be avoided, and the smooth connection between the electrode 307 and the first plate 305 and the first pole 3041 of the thin film transistor 304 can be further ensured.
In the embodiment of the present invention, since the planarization layer 303 includes the positive type photosensitive agent, a half exposure process (Halftone mask) is combined with the HF wet etching process, so that a mask exposure process can be reduced, the recess 3031, the first via 3021, and the second via 3032 can be conveniently formed, and the manufacturing process is simplified.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (9)

1. A substrate for display, comprising:
a substrate;
an insulating layer disposed on the substrate, the insulating layer having a first via;
the flat layer is arranged on one side, far away from the substrate, of the insulating layer and comprises a positive-working photosensitizer, a groove is formed in the surface, far away from the insulating layer, of the flat layer, a second through hole is formed in the portion, located below the groove, of the flat layer, and the first through hole is communicated with the second through hole;
a thin film transistor disposed between the substrate and the insulating layer;
the first polar plate is arranged on the bottom surface of the groove, penetrates through the second through hole and the first through hole and is electrically connected with the first pole of the thin film transistor;
the second polar plate is arranged on one side, close to the substrate, of the insulating layer and is electrically connected with the grid electrode of the thin film transistor;
wherein the first plate and the second plate form two plates of a capacitor.
2. The substrate for display use according to claim 1,
the depth of the groove is 80% -95% of the thickness of the flat layer.
3. The substrate for display use according to claim 1,
an orthographic projection of the second via on the substrate near the edge of the substrate is within an orthographic projection of the first via on the substrate away from the edge of the substrate.
4. The substrate for display use according to claim 3,
the orthographic projection of the edge of the second through hole close to the substrate on the substrate is coincident with the orthographic projection of the edge of the first through hole far away from the substrate on the substrate.
5. The substrate for display according to claim 1, further comprising:
an electrode; the electrode is connected with the first polar plate and is made of the same material on the same layer;
and a color filter layer disposed between the insulating layer and the planarization layer; the color filter layer includes a plurality of filter patterns;
the orthographic projection of the electrode on the substrate and the orthographic projection of one of the filter patterns on the substrate have an overlapping region.
6. The substrate for display use according to claim 1, further comprising:
a metal pattern disposed between the substrate and the thin film transistor;
an orthographic projection of an active layer of the thin film transistor on the substrate is within an orthographic projection of the metal pattern on the substrate;
the metal pattern is electrically connected to a first electrode of the thin film transistor, and the metal pattern and the second electrode have an overlapping area.
7. A display device comprising the substrate for display according to any one of claims 1 to 6.
8. A method for manufacturing a substrate for display, comprising:
sequentially forming a first film and a second film on a substrate, the second film including a positive type photosensitizer;
carrying out mask exposure and development on the second film to form a groove on the surface of the second film far away from the first film, and forming a second through hole at the part under the groove of the second film to obtain a flat layer;
etching the part, exposed by the second through hole, of the first film to form an insulating layer with a first through hole; wherein the content of the first and second substances,
the display substrate includes:
a thin film transistor disposed between the substrate and the insulating layer;
the first polar plate is arranged on the bottom surface of the groove, penetrates through the second through hole and the first through hole and is electrically connected with the first pole of the thin film transistor;
the second polar plate is arranged on one side, close to the substrate, of the insulating layer and is electrically connected with the grid electrode of the thin film transistor;
wherein the first plate and the second plate form two plates of a capacitor.
9. The method of claim 8, further comprising:
after the insulating layer is formed, ashing treatment is performed on the flat layer to obtain a treated flat layer.
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