CN111276483A - Three-dimensional memory and manufacturing method thereof - Google Patents

Three-dimensional memory and manufacturing method thereof Download PDF

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Publication number
CN111276483A
CN111276483A CN202010033322.1A CN202010033322A CN111276483A CN 111276483 A CN111276483 A CN 111276483A CN 202010033322 A CN202010033322 A CN 202010033322A CN 111276483 A CN111276483 A CN 111276483A
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layer
sub
channel hole
dch
etching
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CN111276483B (en
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吴建忠
刘佳
易汉威
高毅
王猛
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Abstract

The invention provides a three-dimensional memory and a manufacturing method thereof. The method comprises the following steps: providing a substrate structure; the base structure at least comprises: a substrate, a stacked structure on the substrate, a storage Channel Hole (CH) and a Dummy Channel Hole (DCH) penetrating the stacked structure and extending to the substrate, a conductive connection layer at the bottom of the CH and DCH, and a memory material layer at the sidewalls of the CH and DCH and the top surface of the conductive connection layer; the stacking structure comprises at least two layers of sub-stacking structures; the stacking structure is formed by utilizing the manufactured sub-stacking structure, and a sub-channel hole of the formed sub-stacking structure penetrates through the sub-stacking structure; filling the first material in the DCH; performing first etching to remove the memory material layer covering the top surface of the conductive connecting layer at the bottom of the CH; wherein, in the first etching process, the etching action on the memory material layer positioned on the side wall of the DCH and the top surface of the conductive connecting layer at the bottom of the DCH is avoided by consuming the first material; the first material is removed.

Description

Three-dimensional memory and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a manufacturing method thereof.
Background
The three-dimensional memory solves the limitation caused by a two-dimensional or planar flash memory by vertically stacking a plurality of layers of data storage units, supports the accommodation of higher storage capacity in a smaller space, and further effectively reduces the cost and the energy consumption. The control gate of the related art three-dimensional memory is generally formed through a gate last process. The gate last process is a process in which the stack layer formed initially includes a plurality of sacrificial layers arranged at intervals, the sacrificial layers are removed in the subsequent process, and the original space of the sacrificial layers is filled with a gate dielectric (such as metal or polysilicon). In the process of forming a control gate of a three-dimensional memory by using a gate last process, when a sacrificial layer is removed and a gate dielectric is not filled, the whole device is supported by a Channel Hole (CH) (here, CH is mainly used for storing data, and for clarity of description, CH is hereinafter referred to as a storage Channel Hole), but as the number of data storage units vertically stacked in height of the conventional three-dimensional memory increases, and as the size of a Channel through Hole is gradually reduced, the supporting force of the CH after the sacrificial layer is removed is insufficient, which easily causes collapse of the whole structure and loss.
In order to solve the problem of collapse of the whole structure after the sacrificial layer is removed, a virtual Channel Hole (DCH) for supporting is created. In the related art, the DCH and the CH only function differently, and the manufacturing processes of the DCH and the CH are completely the same, and the structures are also completely the same.
However, in the subsequent process, the DCH has a risk of leakage.
Disclosure of Invention
In order to solve the related technical problems, embodiments of the present invention provide a three-dimensional memory and a method for manufacturing the same, which can reduce the risk of DCH leakage in the subsequent process.
The embodiment of the invention provides a method for manufacturing a three-dimensional memory, which comprises the following steps:
providing a substrate structure; the base structure comprises at least: a substrate, a stacked structure on the substrate, a CH and a DCH penetrating the stacked structure and extending to the substrate, a conductive connection layer at the bottom of the CH and the DCH, and a memory material layer at the side wall of the CH and the DCH and the top surface of the conductive connection layer; the stacked structure comprises at least two sub-stacked structures; the stacking structure is formed by utilizing a manufactured sub-stacking structure, and a sub-channel hole of the formed sub-stacking structure penetrates through the sub-stacking structure;
filling a first material in the DCH;
performing first etching to remove the memory material layer covering the top surface of the conductive connecting layer at the bottom of the CH; wherein, in a first etching process, an etching effect on the memory material layer on the side wall of the DCH and the top surface of the conductive connection layer at the bottom of the DCH is avoided by consuming the first material;
removing the first material.
In the above scheme, the first material includes a photoresist.
In the foregoing solution, before the DCH is filled with the first material, the method further includes:
forming a barrier layer; the barrier layer covers at least top surfaces of the CH and the DCH;
performing second etching to remove the barrier layer covering the top surface of the DCH;
after filling the first material in the DCH, the method further comprises:
a third etch is performed to remove the barrier layer overlying the top surface of the CH.
In the foregoing aspect, after forming the barrier layer, the method further includes:
coating a photoresist material on the barrier layer;
and removing the photoresist material on the top surface of the DCH so as to expose the barrier layer on the top surface of the DCH for carrying out second etching.
In the above scheme, the barrier layer includes a first thin film layer and a second thin film layer; wherein the material of the first thin film layer comprises amorphous carbon ACL; the material of the second thin film layer comprises silicon oxynitride.
In the above scheme, the step of performing the first etching includes:
performing first etching by adopting a first dry etching process; wherein the first dry etching is performed by a fluorine source of an etching gas.
In the above scheme, the step of removing the first material includes:
removing the first material by adopting a second dry etching process; wherein the second dry etching is performed by an oxygen source of an etching gas.
An embodiment of the present invention further provides a three-dimensional memory, including:
a substrate;
a stack structure on the top surface of the substrate; the stacked structure comprises at least two sub-stacked structures; the stacking structure is formed by utilizing a manufactured sub-stacking structure, and a sub-channel hole of the formed sub-stacking structure penetrates through the sub-stacking structure;
CH and DCH passing through the stacked structure and extending to the substrate;
a conductive connection layer at the bottom of the CH and the DCH;
a memory material layer; the memory material layer covers the sidewall of the CH and covers the sidewall of the DCH and the top surface of the conductive connection layer at the bottom of the DCH.
In the above scheme, the sub-stacking structure includes a plurality of first material layers and second material layers arranged at intervals, and sub-channel holes penetrating through the first material layers and the second material layers; and the sub-channel holes in the at least two layers of sub-stacked structures are communicated.
In the above scheme, the memory material layer includes a blocking dielectric layer, a storage dielectric layer, a tunneling dielectric layer, and a channel layer, which are sequentially disposed along a radially inward direction of the CH.
The embodiment of the invention provides a three-dimensional memory and a manufacturing method thereof, wherein a substrate structure is provided; the base structure comprises at least a substrate; a stacked structure on a substrate; a CH and a DCH penetrating the stacked structure and extending to the substrate, a conductive connection layer at a bottom of the CH and the DCH, and a memory material layer at sidewalls of the CH and the DCH and a top surface of the conductive connection layer; the stacked structure comprises at least two sub-stacked structures; the stacking structure is formed by utilizing a manufactured sub-stacking structure, and a sub-channel hole of the formed sub-stacking structure penetrates through the sub-stacking structure; filling a first material in the DCH; performing first etching to remove the memory material layer covering the top surface of the conductive connecting layer at the bottom of the CH; wherein, in a first etching process, an etching effect on the memory material layer on the side wall of the DCH and the top surface of the conductive connection layer at the bottom of the DCH is avoided by consuming the first material; removing the first material. In the embodiment of the invention, before the CH and the DCH are subjected to etching process treatment together, the DCH is filled with materials, and the etching effect on the memory material layer positioned on the side wall of the DCH and the top surface of the conductive connecting layer at the bottom of the DCH is avoided by consuming the filling materials, so that the etching process only generates the etching effect on the memory material layer positioned on the top surface of the conductive connecting layer at the bottom of the CH, the memory material layer on the side wall of the DCH can be further ensured not to be damaged, and the electric leakage caused by the conduction of the polycrystalline silicon filled in the DCH and the gate dielectric filled in the stacked structure in the subsequent processing procedure is avoided. Therefore, the risk of DCH electric leakage in the subsequent manufacturing process can be reduced.
Drawings
FIG. 1a is a first schematic view of the shapes of CH and DCH according to the embodiment of the invention;
fig. 1b is a first schematic diagram of a SONO film structure after SONO etching process is performed on the CH and the DCH in accordance with the embodiment of the present invention;
FIG. 2a is a second schematic view of the shapes of CH and DCH according to the embodiment of the invention;
fig. 2b is a schematic diagram of a SONO film structure after SONO etching process processing is performed on the CH and the DCH in the embodiment of the present invention;
FIG. 3 is a schematic flow chart illustrating an implementation of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention;
FIGS. 4a-4d are schematic process diagrams of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention;
fig. 5a to 5f are schematic diagrams of an implementation process for filling the first material in the DCH according to the present invention;
fig. 6a to 6d are schematic diagrams illustrating an implementation process of removing a barrier layer on top of CH according to an embodiment of the present invention.
Description of reference numerals:
30-a base structure; 310-a substrate; 320-a stacked structure; 3201-a first material layer; 3202-a second material layer; 330-CH; 340-DCH; 350-a conductive connection layer; 360-a layer of memory material; 31-a first material; 32-a barrier layer; 321-a first thin film layer; 322-second film layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the following describes specific technical solutions of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention.
In the related art, the three-dimensional memory includes a plurality of CHs and DCHs, and the process of forming the CHs and the DCHs includes: forming a stacked structure on a substrate; the stacked structure comprises a plurality of first material layers (also called as sacrificial layers) and second material layers (also called as insulating layers) which are arranged at intervals; forming CH and DCH in the stacked layers, respectively; wherein the CH and DCH pass through the stack structure and extend to the substrate; forming a conductive connection layer (also referred to as an "epitaxial layer") at the bottom of the CH and DCH; forming a multi-layer thin film structure (also referred to as "memory material layer") such as a SONO thin film structure on the sidewalls of the CH and DCH and the top surface of the conductive connection layer at the bottom of the CH and DCH; and then, etching the multilayer thin film structure on the top surfaces of the conductive connection layers at the bottoms of the CH and the DCH (when the multilayer thin film structure is a SONO thin film structure, the etching is a SONO etching process, that is, removing the silicon Oxide (OX), the silicon nitride (SiN), the silicon Oxide (OX), and the amorphous silicon (Si) thin film layer on the top surfaces of the conductive connection layers at the bottoms of the CH and the DCH by etching so as to conduct the channel layers in the CH and the DCH and the conductive connection layers in the subsequent process, so as to expose the conductive connection layers at the bottoms of the CH and the DCH through the multilayer thin film structure. In the subsequent process, the CH and the DCH are filled with channel medium, and then the subsequent manufacturing of Contact holes (contacts) and leads (plugs) is performed. For simplicity of description, the SONO thin film structure and the SONO etching process are described as examples below.
In the above process of forming CH and DCH in the stacked layer, deep hole etching is required. In order to solve the problem that deep hole etching is difficult due to the fact that the number of layers of a memory is too high, in some embodiments, a sub-stacking structure with a certain number of stacking layers, such as 64 layers, is etched to form sub-channel holes penetrating through the sub-stacking structure, then a plurality of layers of sub-stacking structures are stacked, and when the sub-stacking structures are stacked, it is ensured that the sub-channel holes in each sub-stacking structure in the plurality of layers of sub-stacking structures are aligned and connected; these aligned connected sub-channel holes form the CH and the DCH. The formed CH and DCH are as shown in FIG. 1, two layers of sub-stacking structures are stacked to form a 128-layer stacking structure, and sub-channel holes in the two layers of sub-stacking structures are aligned; meanwhile, the sidewall of the sub-channel hole formed by the actual etching process is not an ideal vertical profile, but a profile with a large top dimension and a small bottom dimension, so that the finally formed CH and DCH have a profile with a large top dimension, a middle (where two layers of sub-stacked structures are stacked) dimension changed from small to large, and a small bottom dimension as shown in fig. 1 a. At this time, when the CH and the DCH are subjected to the SONO etching process together, the structure of the conductive connection layer passing through the SONO film structure and exposing the CH and the bottom of the DCH is shown in fig. 1b, and the SONO film structure on the sidewall of the DCH is normal.
However, in practical applications, in order to ensure the complete alignment of the sub-channel holes in the CH during the stacking of the two sub-stacked structures, the accuracy of the alignment of the sub-channel holes in the DCH is sacrificed, so that the topography in the DCH is often the topography as shown in fig. 2a, i.e. the stacking position of the two sub-stacked structures in the DCH is shifted to the right compared to the complete alignment. Meanwhile, in practical applications, there may be a situation that the DCH topography is distorted (expressed as Distortion in english) and alignment of circuit patterns of each layer is required in photolithography (expressed as Overlay, abbreviated as OVL) is poor, which further increases the DCH topography deviation compared with the DCH topography in fig. 1 a. At this time, when the CH and the DCH are subjected to the SONO etching process together, a structure that the CH and the conductive connection layer at the bottom of the DCH are exposed through the SONO film structure is obtained as shown in fig. 2b, and the SONO film structure where the DCH side wall is located at the overlapping position of the two sub-stacked structures (english expression is Joint side wall) is damaged.
When the SONO film structure of the side wall of the DCH positioned at the superposition position of the two sub-stacking structures is damaged, in the subsequent manufacturing process, the polycrystalline silicon filled in the DCH is conducted with the grid medium filled after the sacrificial layer in the stacking structure is removed, and because the inside of the DCH has a structure consistent with the DH, the grid medium filled in each layer in the stacking structure is connected, namely the polycrystalline silicon at the superposition position of the two sub-stacking structures in the DCH is conducted with the grid medium at the superposition position of the two sub-stacking structures in the DH, at the moment, when voltage is applied to the grid medium at the superposition position of the two sub-stacking structures in the DH, the crystalline silicon in the DCH is also electrified, so that the phenomenon of electric leakage occurs.
Based on this, in various embodiments of the present invention, before the CH and the DCH are subjected to the etching process, the DCH is filled with a material, and the etching action on the memory material layer located on the sidewall of the DCH and the top surface of the conductive connection layer at the bottom of the DCH is avoided by consuming the filling material, so that the etching process only generates the etching action on the memory material layer located on the top surface of the conductive connection layer at the bottom of the CH, and thus the memory material layer on the sidewall of the DCH can be ensured not to be damaged, and the leakage caused by the conduction between the polysilicon filled in the DCH and the gate dielectric filled in the stack structure in the subsequent process is avoided. Therefore, the risk of DCH electric leakage in the subsequent manufacturing process can be reduced.
An embodiment of the invention provides a method for manufacturing a three-dimensional memory, and fig. 3 is a flow chart illustrating the method for manufacturing the three-dimensional memory according to the invention. As shown in fig. 3, the method comprises the steps of:
step 301: providing a substrate structure; the base structure comprises at least a substrate; a stacked structure on a substrate; a CH and a DCH penetrating the stacked structure and extending to the substrate, a conductive connection layer at the bottom of the CH and the DCH, and a memory material layer at the side wall of the CH and the DCH and the top surface of the conductive connection layer; the stacked structure comprises at least two sub-stacked structures; the stacking structure is formed by utilizing a manufactured sub-stacking structure, and a sub-channel hole of the formed sub-stacking structure penetrates through the sub-stacking structure;
step 302: filling a first material in the DCH 340;
step 303: performing first etching to remove the memory material layer covering the top surface of the conductive connecting layer at the bottom of the CH; wherein, in a first etching process, an etching effect on the memory material layer on the side wall of the DCH and the top surface of the conductive connection layer at the bottom of the DCH is avoided by consuming the first material;
step 304: removing the first material.
Fig. 4a-4d are schematic process diagrams illustrating a method for fabricating a three-dimensional memory according to an embodiment of the invention. A method of forming the semiconductor structure of the present embodiment is described below in conjunction with fig. 3 and 4a-4 d.
In step 301, as shown in fig. 4a, the base structure 30 at least includes a substrate 310, a stacked structure 320, a CH 330, a DCH340, a conductive connection layer 350, and a memory material layer 360; wherein:
the substrate 310 may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.
The stacked structure 320 is located on the substrate 310, and the stacked structure 320 includes at least two sub-stacked structures (only two are shown in FIG. 4 a)A layer); the sub-stacked structure includes a plurality of first material layers 3201 and 3202 arranged at intervals and sub-channel holes penetrating the first material layers 3201 and 3202; and the sub-channel holes in the at least two sub-stacked structures are connected. The first material layer 3201 may be a sacrificial layer, and may be formed of, for example, one of an oxide layer, a nitride layer, a silicon carbide layer, a silicon layer, and a silicon germanium layer; the second material layer 3202 may be a dielectric layer, the material of which includes but is not limited to silicon oxide, silicon nitride layer, silicon oxynitride, and other high dielectric constant (high-k) dielectric layers; in the subsequent process, the sacrificial layer may be removed, and a gate metal material is filled at the removed position to form a gate layer, wherein the gate layer material includes, for example, metal tungsten (W). In one embodiment, the first material layer 3201 may be formed of silicon nitride (SiN); the second material layer 322 may be made of silicon oxide (SiO)2) The stack structure 3202 thus formed is a nitride-oxide (NO) stack. In practical applications, the first material Layer 3201 and the second material Layer 3202 may be formed by Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or the like; here, the first material layer 3201 and the second material layer 3202 may have the same thickness as each other, or may have different thicknesses from each other.
Meanwhile, in the stack structure 320, a CH 330 and a DCH340 are also formed through the stack structure 320 and extend to the substrate 310. Here, the CH 330 and the DCH340 are formed after the sub-channel holes in each of the at least two sub-stack structures are communicated. In an embodiment, the manufacturing process of the stack structure 320 and the CH 330 and the DCH340 may include: forming a first stacked structure on a substrate 310; forming a first sub-channel hole penetrating through the first stacked structure; forming a sacrificial layer on the surface of the first stacked structure and in the first sub-channel hole; forming a first dielectric layer on the surface of the sacrificial layer; forming a second stacking structure on the surface of the first dielectric layer; forming a second sub-channel hole penetrating the second stacked structure, wherein the second sub-channel hole and the second sub-channel hole; and after the second through hole is formed, removing the first medium and the sacrificial layer in the first through hole. In practical applications, the channel hole may be formed by dry etching. The above-mentioned mode of forming CH 330 and DCH340 replaces once through-hole etching on the whole thickness equal to the sum of the first stacked structure and the second stacked structure through twice etching, forms the first sub-channel hole penetrating the first stacked structure and the second sub-channel through-hole penetrating the second stacked structure, respectively, and reduces the process difficulty of once forming CH 330 and DCH 340. In practical applications, when the number of layers of the sub-stacked structure is greater than two, the above method may be repeated to continue the stacking up on the second stacked structure.
The conductive connection layer 350 is used to electrically connect the channel layers in the CH 330 and DCH340 with the well region in the substrate 310. In practical applications, the conductive connection layer 350 may be formed by means of epitaxial Growth (SEG), and the material of the conductive connection layer may include: monocrystalline silicon.
The memory material layer 360 is a multi-layer thin film structure, such as a SONO thin film structure, formed on the sidewalls of the CH 330 and the DCH340 and the top surface of the conductive connection layer 350. The SONO thin film structure comprises four layers of thin films, specifically comprises a blocking dielectric layer, a storage dielectric layer, a tunneling dielectric layer and a channel layer which are sequentially stacked along the radial direction of a through hole; wherein the blocking dielectric layer is used for blocking the outflow of charges in the storage layer, and the material can be silicon Oxide (OX); the storage medium is used for capturing and storing charges, and the material can be silicon nitride (SiN); the tunneling dielectric layer is used for generating electric charges, and the material can be silicon Oxide (OX); the channel layer material may be an amorphous silicon (Si) thin film layer. In practice, the memory material layer 360 may be formed by CVD, ALD, or the like.
Although an exemplary method of forming a base structure is described herein, it will be appreciated that one or more steps may be omitted from the formation of such a base structure. For example, in practical applications, various well regions may be formed in the substrate 30 as needed; and generating a corresponding mask layer before etching.
In step 302, the first material 31 is used to avoid etching of the memory material layer on the sidewalls of the DCH340 and the top surface of the conductive connection layer at the bottom of the DCH340 by consuming the filled first material during the first etching process, and the first material needs to be removed after the etching is completed. The first material may therefore be chosen to be an easily filled and easily removed material, such as a photoresist.
Based on this, in some embodiments, the first material comprises a photoresist.
Next, the implementation of step 302, i.e. filling the first material 31 in the DCH340, according to an embodiment of the present invention, will be described with reference to fig. 5a-5 f.
Fig. 5a shows the provided base structure. Since this padding is for DCH340 only, the top of CH 330 needs to be covered before padding to block the padding of CH 330 together.
Based on this, in some embodiments, before filling the first material in the DCH340, the method further comprises:
forming a barrier layer 32; the barrier layer covers at least the top surfaces of the CH 330 and DCH 340;
performing a second etching to remove the barrier layer 32 covering the top surface of the DCH 340;
after filling the first material 31 in the DCH340, the method further comprises:
a third etch is performed to remove the barrier layer 32 overlying the top surface of the DCH 340.
Next, referring to fig. 5b, a barrier layer 32 is formed on top of CH 330 and DCH 340. Since the barrier layer is formed on the top surface of the hole structure, in practical application, a first thin film layer, such as ACL, which can shield the hole structure can be formed by using a material with a relatively high growth rate, and then a flat second thin film layer can be formed on the first thin film layer. Moreover, the etching selectivity of the etching gas to the second thin film layer 322 and the photoresist material subsequently coated on the barrier layer 32 (here, the etching selectivity refers to the ratio of the etching rate of one material to that of another material under the same etching condition) is significantly different, such as silicon oxynitride.
Based on this, in some embodiments, the barrier layer 32 includes a first thin film layer 321 and a second thin film layer 322; wherein the material of the first film layer 321 comprises ACL; the material of the second thin film layer 322 includes silicon oxynitride.
In practical applications, the first thin film layer 321 and the second thin film layer 322 may be formed by CVD or ALD.
Wherein, in some embodiments, after forming the barrier layer 32, the method further comprises:
coating a photoresist material on the barrier layer 32;
the photoresist on the top surface of the DCH340 is removed to expose the barrier layer 32 on the top surface of the DCH340 for the second etching.
Referring to fig. 5c, a photoresist material, such as photoresist, is coated on the barrier layer 32, and then the photoresist material on the top surface of the DCH340 is removed by developing or the like, so as to expose the barrier layer 32 on the top surface of the DCH340, so as to remove the barrier layer 32 on the top surface of the DCH340 by etching.
Next, referring to fig. 5d, a second etching is performed to remove the barrier layer 32 covering the top surface of the DCH 340. In practical application, the step of performing the second etching includes: performing second etching by adopting a dry etching process; wherein the dry etching process is performed using an etching gas containing a fluorine source, more particularly using a fluorine source in the etching gas. In some embodiments, the dry etching may be plasma etching, and the etching gas may be CF4Etc., or other etching gases known in the art that may be used to etch the second membrane layer 322. It should be noted that, in the second etching, the etching selectivity of the etching gas to the second thin film layer 322 and the photoresist material is different, so as to ensure that the barrier layer 32 on top of the CH 330 may not be etched.
Next, referring to fig. 5e, the DCH340 is filled with the first material, and the height of the first material in the DCH340 after filling is the same as the height of the barrier layer 32 on top of the CH 330, and in practical applications, a small amount of the first material may also exist on the surface of the barrier layer 32 on top of the CH 330.
After the first material is filled in the DCH340, the barrier layer 32 on top of the CH 330 needs to be removed for the subsequent first etching.
Next, the implementation of removing the barrier layer 32 on top of the CH 330 in an embodiment of the invention is described with reference to fig. 6a-6 d.
Fig. 6a shows the structure after the first material has been filled in the DCH340, while a small amount of the first material is also present at the surface of the barrier layer 32 on top of the CH 330.
Next, referring to fig. 6b, the barrier layer 32 on top of the CH 330 is etched to remove the second thin film layer 322 in the barrier layer 32 on top of the CH 330. Here, in practical application, the step of performing the corresponding etching may be the same as the second etching described above. At this time, there may also be a slight loss of the first material filled in the DCH 340.
Next, referring to fig. 6c, the barrier layer 32 on top of the CH 330 is etched to remove the first thin film layer 321 in the barrier layer 32 on top of the CH 330. Here, in practical application, the step of performing the corresponding etching includes: etching by adopting a dry etching process; wherein the dry etching process is performed at a high temperature, such as 1000 ℃, using an etching gas containing an oxygen source, and more particularly using oxygen in the etching gas. It should be noted that, when the first material 31 is a photoresist, the etching gas containing the oxygen source also has an etching effect on the first material 31.
Based on this, the height of the first material filled in the DCH340 obtained in the step of removing the barrier layer 32 on top of the CH 330 is as shown in fig. 6d (or 5 f).
Here, the removal of the barrier layer 32 on top of the CH 330 is completed, while the filling of the first material in the DCH340 is also completed.
In step 203, as shown in fig. 4c, the first etching is aimed at: the memory material layer 360 on the top surface of the conductive connection layer 350 at the bottom of the CH 330 is removed to expose the conductive connection layer 350 at the bottom of the CH. At this time, due to the existence of the first material, the memory material layer 360 on the sidewall of the DCH340 (especially, the sidewall at the position where the two sub-stacked structures are stacked) and the top surface of the conductive connection layer 350 at the bottom of the DCH340 are not etched, i.e., the memory material layer 360 on the sidewall at the position where the DCH340 is stacked is well protected; in addition, the memory material layer 360 on the top surface of the conductive connection layer 350 at the bottom of the DCH340 is not etched and does not affect the supporting function of the DCH340 in the subsequent processes.
In practical application, the step of performing the first etching includes: performing first etching by adopting a dry etching process; wherein the dry etching process is performed using an etching gas containing a fluorine source, more particularly using a fluorine source in the etching gas. In some embodiments, the dry etching may be plasma etching, and the etching gas may be CF4Etc., or other etching gases known in the art that may be used to etch the memory material layer 360.
In step 204, as shown in fig. 4d, in practical application, the step of removing the first material 31 includes: removing by adopting a dry etching process; wherein the dry etching process is performed at a high temperature, such as 1000 ℃, using an etching gas containing an oxygen source, and more particularly using oxygen in the etching gas.
The manufacturing method of the three-dimensional memory provided by the embodiment of the invention comprises the steps of providing a substrate structure; the base structure comprises at least a substrate; a stacked structure on a substrate; a CH and a DCH penetrating the stacked structure and extending to the substrate, a conductive connection layer at a bottom of the CH and the DCH, and a memory material layer at sidewalls of the CH and the DCH and a top surface of the conductive connection layer; the stacked structure comprises at least two sub-stacked structures; the stacking structure is formed by utilizing a manufactured sub-stacking structure, and a sub-channel hole of the formed sub-stacking structure penetrates through the sub-stacking structure; filling a first material in the DCH; performing first etching to remove the memory material layer covering the top surface of the conductive connecting layer at the bottom of the CH; wherein, in a first etching process, an etching effect on the memory material layer on the side wall of the DCH and the top surface of the conductive connection layer at the bottom of the DCH is avoided by consuming the first material; removing the first material. In the embodiment of the invention, before the CH and the DCH are subjected to etching process treatment together, the DCH is filled with materials, and the etching effect on the memory material layer positioned on the side wall of the DCH and the top surface of the conductive connecting layer at the bottom of the DCH is avoided by consuming the filling materials, so that the etching process only generates the etching effect on the memory material layer positioned on the top surface of the conductive connecting layer at the bottom of the CH, the memory material layer on the side wall of the DCH can be further ensured not to be damaged, and the electric leakage caused by the conduction of the polycrystalline silicon filled in the DCH and the gate dielectric filled in the stacked structure in the subsequent processing procedure is avoided. Therefore, the risk of DCH electric leakage in the subsequent manufacturing process can be reduced.
Based on the above semiconductor forming method, an embodiment of the present invention further provides a memory, where the memory includes:
a substrate;
a stack structure on the top surface of the substrate; the stacked structure comprises at least two sub-stacked structures; the stacking structure is formed by utilizing a manufactured sub-stacking structure, and a sub-channel hole of the formed sub-stacking structure penetrates through the sub-stacking structure;
CH and DCH passing through the stacked structure and extending to the substrate;
a conductive connection layer at the bottom of the CH and the DCH;
a memory material layer; the memory material layer covers the sidewall of the CH and covers the sidewall of the DCH and the top surface of the conductive connection layer at the bottom of the DCH.
In some embodiments, the sub-stacking structure comprises a plurality of first material layers and second material layers which are arranged at intervals, and sub-channel holes which penetrate through the first material layers and the second material layers; and the sub-channel holes in the at least two layers of sub-stacked structures are communicated.
In some embodiments, the memory material layer includes a blocking dielectric layer, a storage dielectric layer, a tunneling dielectric layer, and a channel layer sequentially disposed along a radially inward direction of the CH.
It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.

Claims (10)

1. A method of fabricating a three-dimensional memory, the method comprising:
providing a substrate structure; the base structure comprises at least: the memory device comprises a substrate, a stacked structure, a storage channel hole, a virtual channel hole, a conductive connecting layer and a memory material layer, wherein the stacked structure is positioned on the substrate, the storage channel hole and the virtual channel hole penetrate through the stacked structure and extend to the substrate, the conductive connecting layer is positioned at the bottom of the storage channel hole and the virtual channel hole, and the memory material layer is positioned on the side wall of the storage channel hole and the virtual channel hole and the top surface of the conductive connecting layer; the stacked structure comprises at least two sub-stacked structures; the stacking structure is formed by utilizing a manufactured sub-stacking structure, and a sub-channel hole of the formed sub-stacking structure penetrates through the sub-stacking structure;
filling a first material in the dummy trench hole;
performing first etching to remove the memory material layer covering the top surface of the conductive connecting layer at the bottom of the storage channel hole; in the first etching process, the etching effect on the memory material layer positioned on the side wall of the virtual channel hole and the top surface of the conductive connecting layer at the bottom of the virtual channel hole is avoided by consuming the first material;
removing the first material.
2. The method of claim 1, wherein the first material comprises photoresist.
3. The method of claim 1,
before filling the dummy trench hole with the first material, the method further comprises:
forming a barrier layer; the barrier layer at least covers the top surfaces of the storage channel hole and the virtual channel hole;
performing second etching to remove the barrier layer covering the top surface of the virtual trench hole;
after filling the dummy trench hole with the first material, the method further includes:
and carrying out third etching to remove the barrier layer covering the top surface of the storage channel hole.
4. The method of claim 3, wherein after forming the barrier layer, the method further comprises:
coating a photoresist material on the barrier layer;
and removing the photoresist material on the top surface of the virtual channel hole so as to expose the barrier layer on the top surface of the virtual channel hole for second etching.
5. The method of claim 3, wherein the barrier layer comprises a first thin film layer and a second thin film layer; wherein the material of the first thin film layer comprises amorphous carbon ACL; the material of the second thin film layer comprises silicon oxynitride.
6. The method of claim 1, wherein the step of performing a first etch comprises:
performing first etching by adopting a first dry etching process; wherein the first dry etching is performed by a fluorine source of an etching gas.
7. The method of claim 1, wherein the step of removing the first material comprises:
removing the first material by adopting a second dry etching process; wherein the second dry etching is performed by an oxygen source of an etching gas.
8. A three-dimensional memory, comprising:
a substrate;
a stack structure on the top surface of the substrate; the stacked structure comprises at least two sub-stacked structures; the stacking structure is formed by utilizing a manufactured sub-stacking structure, and a sub-channel hole of the formed sub-stacking structure penetrates through the sub-stacking structure;
a storage channel hole and a dummy channel hole passing through the stacked structure and extending to the substrate;
the conductive connecting layer is positioned at the bottoms of the storage channel hole and the virtual channel hole;
a memory material layer; the memory material layer covers the side wall of the memory channel hole, the side wall of the virtual channel hole and the top surface of the conductive connecting layer at the bottom of the virtual channel hole.
9. The three-dimensional memory according to claim 8, wherein the sub-stack structure comprises a plurality of first material layers and second material layers arranged at intervals, and sub-channel holes penetrating through the first material layers and the second material layers; and the sub-channel holes in the at least two layers of sub-stacked structures are communicated.
10. The three-dimensional memory according to claim 8, wherein the memory material layer comprises a blocking dielectric layer, a storage dielectric layer, a tunneling dielectric layer, and a channel layer sequentially disposed along a radially inward direction of the storage channel hole.
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