CN1112750C - Reactive power compensator of aontactless switch - Google Patents

Reactive power compensator of aontactless switch Download PDF

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CN1112750C
CN1112750C CN 99109784 CN99109784A CN1112750C CN 1112750 C CN1112750 C CN 1112750C CN 99109784 CN99109784 CN 99109784 CN 99109784 A CN99109784 A CN 99109784A CN 1112750 C CN1112750 C CN 1112750C
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裴迪生
裴厚生
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Abstract

The present invention relates to a reactive power compensator with a contractless switch, which is composed of L-C series-connected filters, a switch electrical inductor and an electronic circuit control circuit, wherein the L-C series-connected filters with K times of harmonics are composed of electrical inductors and capacitors; the switch electrical inductor is composed of thyristors with the same specification by antiparallel connection. The present invention is characterized in that the switching inductance of the reactive power capacity of the components is switched by the contactless switch of the present invention, and the reactive power capacity is set according to a binary weight number; the reactive power capacity of the switching inductance in N branches in each phase is set according to 1, 2, 4, 8... 2<N-1>, and a plurality of groups of the L-C series-connecting filters are connected in parallel in each of the phases. The present invention is suitable for occasions with serious waveform distortion in supply voltage, or a load containing abundant harmonics, such as a single-phase welder group and an energy-saving lamp group. In the operational mode of a regional synchronous condenser, the present invention can be used in an electric network of 10kV or higher voltage level, not only hysteretic reactive power on the electric network, but also advance reactive power on the electric network can be compensated, and the present invention has the function of regulating a power factor in a region; simultaneously, with the utilization of the filtering function of the present invention, the voltage waveform in an accessing network point can be corrected for meeting the specification of international GB/T-14549-93.

Description

Reactive power compensator of aontactless switch
Technical field
The present invention relates to a kind of reactive power compensator of aontactless switch.
Background technology
The noncontacting switch of existing reactive power compensator of aontactless switch is triode thyristor (thyristor) or bidirectional thyristor (triac) without exception.In the world this class compensation arrangement general designation TVC (being Thyristor (or) Triac var compensator).Segmentation has two classes, the first kind is thyristor switch Electric capacity compensation device TSC (ThyristorSwitched Capacitor) series with the direct control compensation electric capacity of the noncontacting switch break-make of triode thyristor and diode inverse parallel composition, as the SVS equipment series by Chinese invention patent 89103959.7 and 89104223.7 and 89208932.6 supports, the single-phase figure of SVS series compensation arrangement as shown in Figure 1.SW is the noncontacting switch that triode thyristor and the inverse parallel of power electronics diode are formed.C 0, C 1C nFor reactive capability is pressed binary system flexible strategy 1,2,4 ... 2 nThe building-out capacitor that is provided with.Bucking-out system can provide altogether from 0 beginning, 1,2,3 ... 2 nTotally 2 N+1Individual compensation grade.Systemic resolution is 1/2 flexible strategy.The noncontacting switch thyristor triggers fixing constantly: when needs drop into certain grade of building-out capacitor, get final product at the thyristor of this grade of figure timberline voltage peak time trigger electric capacity noncontacting switch.In the time need not throwing certain grade of building-out capacitor, do not give noncontacting switch thyristor triggering signal, make electric capacity biasing on-Line Voltage positive peak wait for the triggering signal that next cycle is possible, drop into this grade building-out capacitor.Second class is the noncontacting switch phase shifting control compensating inductance electric current of forming with the triode thyristor inverse parallel, cause the inductance fundamental current adjustable, be the stepless adjustable scheme that goes up fixed compensation capacitor in parallel then of equivalent compensating inductance value, available english abbreviation FCTCR (Fixed Cap ThyristorControlled Reactor) expression.The single-phase figure of FCTCR compensation arrangement is shown in accompanying drawing two.SW is two antiparallel noncontacting switches of same model specification triode thyristor.The triggering of two thyristors is decided according to the variation of phase-shifted control signal by phase-shift trigger unit constantly.When corresponding moment that the phase shifting angle right-to-left moves to the full conducting of inductance as time zero: T in to figure 1Promptly be V 1Positive peak constantly, to T 2Promptly be V 1Negative peak constantly.Along with moving to right of trigger angle, T 1And T 2The conducting time zone shortens, and the inductive current effective value diminishes, and its effect is that the first-harmonic equivalent inductance is adjustable continuously.Phase-shifted control signal is by electric current, and voltage sensor signals obtains through computing.
The technical indicator that the TSC scheme reaches is:
1), switching capacitance does not have transient process, no harmonic wave;
2), every grid cyclic wave is adjusted each phase building-out capacitor switching value successively respectively;
3), right title load carries out asymmetry compensation;
4), compensation precision can reach three-phase activity coefficient 0.99.
The shortcoming of TSC scheme is the fierceness fluctuation that can not bear line voltage, and for example, a grid cyclic wave voltage fluctuation is more than 10%; Second shortcoming is that distortion has strict requirement to TSC to supply power voltage, if the supply power voltage harmonic wave surpasses 5%, particularly voltage peak is offset constantly above 0.5ms, just might damage thyristor noncontacting switch or building-out capacitor, the 3rd shortcoming, for example by the SVS series of prosperous electric equipment factory of Jiangsu power construction first engineering company production, though device itself can not provide harmonic wave to electrical network, itself does not have filter capacity device.
The technical indicator that the FCTCR scheme reaches is:
1), right title load carries out asymmetry compensation;
2), if necessary, can suitably dispose the installed capacity that fixed capacity and contactless phase shift trigger the control inductance, both can the hysteresis reactive power of load also can be compensated the leading reactive power of load; Compensation precision can reach three-phase activity coefficient 0.97 or higher.
3), per half grid cyclic wave adjusts once each phase offset respectively, promptly response speed is the twice of TSC scheme.Can prove that this is the high response speed of TVC compensation way, can not be faster.
4), can bear big mains ripple, have certain filter capacity.
The shortcoming of FCTCR is that device itself promptly is a powerful harmonic source.Be described as follows: when FCTCR promptly not only can compensate the hysteresis reactive power of load but also can compensate the leading reactive power of load as regional compensator, the installed capacity of controllable impedance was made as Q L, its rated current I LThe fixed capacity installed capacity is made as Q C, its rated current is made as I CAbove-mentioned Several Parameters must satisfy following relation: Q L=2Q C, I L=2I CBecause realizing the adjustable method of inductance is the phase shift triggering control of thyristor switch, make the inductance fundamental current be transferred to rated value I from 0 L, its phase shift range theoretical value is the 0-1/4 grid cyclic wave, promptly is 0-5ms concerning the 50Hz electrical network.In fact from 0 when moving to right to 2.9ms, the inductance fundamental current has dropped to 10%I LRegrettably, in phase shifting control inductance fundamental current, because inductive current more and more departs from sine wave, thereby the harmonic current composition becomes more and more heavier.
This process that the applicant has used the PSPICE software simulation, fundamental current that obtains and harmonic wave current relationship are as shown in the table, reference value I CBe the fixed capacity rated current:
Phase shifting angle ms 0 0.2 0.4 0.7
Inductance fundamental current per unit value I Lf/I C 200％ 182.8％ 165.2％ 140％
Inductance harmonic current per unit value I LH/I C 0％ 14.58％ 20.20％ 26.2％
1.0 1.2 1.5 1.9 2.3 2.8 3.2
117.6％ 103％ 82.6％ 58.8％ 39.2％ 21％ 11％
29.80％ 30.8％ 31％ 28.4％ 23.8％ 16.6％ 10.8％
Table 1: the relation that the controllable impedance electric current changes with phase shifting angle
By table 1 as seen, when phase shifting angle is 22 ° (1.22ms), I Lf/ I C=1, promptly adjustable inductance fundamental wave reactive power power Q 1With fixed capacity reactive power rated value Q CEquate that compensation arrangement does not afford redress to electrical network, but provide harmonic current up to electric capacity rated current 30% to electrical network.This is the inherent defect of this scheme.
The masterpiece of FCTCR is the compensation arrangement of famous ABB AB.This device has to be provided with powerful filtering system, harmonic wave that should the elimination load current, the harmonic wave of also wanting elimination device itself to produce.Even so, according to the field measurement of authoritative unit to the FCTCR device that is installed in Zhangjiagang, Jiangsu Province steel plant, its harmonic pollution to electrical network surpass unexpectedly the GB/T-14549-93 regulation feasible value 100% to 200%!
Summary of the invention
The technical problem to be solved in the present invention is exactly that the advantage that collects TSC and two kinds of schemes of FCTCR is abandoned the shortcoming of two schemes and proposed a FCTSR (being Fixed Cap Thyhistor Switched Reactor) scheme.
Reactive power compensation element and controller by thyristor contactless switch element, contactless switch element switching constitute.Controller is made of clock generator, signals collecting and treatment circuit, switching display circuit and switching power amplifier; Clock generator has two groups of outputs, and one group outputs to signals collecting and treatment circuit, and another group outputs to the switching power amplifier, controls the work tempo of aforementioned two circuit; Signals collecting and treatment circuit are handled the back to the load current signal that receives and are divided two-way output, and one the tunnel outputs to the switching display circuit, and another road outputs to the switching power amplifier, by the break-make of this circuit triggers thyristor contactless switch element.
The single-phase figure of FCTSR compensation arrangement is shown in accompanying drawing three.L among the figure FKAnd C FK(k=2,3 ... m) the L-C series filter of formation K subharmonic.SW K(k=0,1 ... n) be the inverse parallel of same model specification thyristor, to different k values, the right specification of thyristor may not be identical.The characteristics of this scheme are:
1), be provided with such as three times, five times,, be used for absorbing the harmonic current of load for seven times or also have the L-C series filter of other number of times (because of the load harmonic nature is decided).These series filters all are capacitives concerning fundamental frequency, can be equivalent in fixed compensation capacitor.So, do not establish special fixed compensation capacitor in the compensation arrangement, all electric capacity all have the function of compensating fundamental wave and harmonic wave inhibition concurrently.
2), switched inductors is set, by thyristor inverse parallel (or high pressure when for example 10kv is above, the inverse parallel Inversely Parallel Thyristor Strings of thyristor string) noncontacting switch control switching by flexible strategy.Switching is fixing constantly, occurs in the positive and negative peak values moment of supply power voltage.Like this, the electric current in the switched inductors is from the extremely zero sine-wave current that finishes of zero beginning, does not follow the generation of harmonic wave.Switched inductors is a delta-connection, and every have N branch road mutually, and N branch switch inductance is provided with its reactive power capacity by 1-2-4-8 binary system flexible strategy.Its switching is controlled in each two thyristor inverse parallel of route when low pressure (or with a Triac).When the regional compensator, whenever in the scheme be provided with 1,2,4,8 mutually ... the highest weight number is 2 N-1The switched inductors of-1 noncontacting switch control.For instance, if every phase four-way switch inductance, inductance reactive power capacity flexible strategy are respectively 1,2,4 and 7 so.All L-C filters of relative set equivalent capacitance reactive power capacity when first-harmonic also is 7.Like this, system can provide 15 compensation grades altogether :+7 ,+6 ,+5 ,+4 ,+3 ,+2 ,+1,0 ,-1 ,-2 ,-3 ,-4 ,-5 ,-6 ,-7 wherein symbol+expression is leading, i.e. building-out capacitor, symbol "-" expression hysteresis, i.e. compensating inductance.It is 1/2nd compensation grades that system divides the man's cap used in ancient times rate, has continued to use 89103959.7 the way that is provided with.
3) the, the 2nd) numerical value of N of mentioning in the item determines to the standard of the scvd (being shortcircuit voltage drop) of electrical network flicker (flicker) that according to Britain promptly 1/2nd of bucking-out system resolution corresponding reactive powers of compensation grade should connect 2% of site capacity of short circuit less than (equaling at the most) bucking-out system.The variation of the brightness of illumination that the mains ripple that the residue reactive power that can guarantee so not compensated causes causes is in the scope that the mankind's vision can be born.Be described as follows with a numerical example: certain is by bucking-out system supply power voltage 3 * 35kv, transformer capacity 25MVA, and it is 200MVA that bucking-out system connects the site capacity of short circuit, the maximum active power 16MW that loads, maximum reactive power 19MVar (hysteresis) loads
Press the scvd standard, 2% capacity of short circuit is 4MVA.In view of the above, the N of bucking-out system is chosen as 2, and all L-C filter power frequency equivalent capacitances are made as 3 * 6.3MVar, switched inductors total capacity 3 * 6.3MVar, and every phase two branch roads, flexible strategy are that 1 switched inductors capacity is 2.1MVar; Flexible strategy are that 2 switched inductors capacity is 4.2MVar.Four compensation grades can be arranged altogether:
0,3 * 2.1MVar, 3 * 4.2MVar and 3 * 6.3MVar.It is 1/2nd compensation grade, i.e. 3 * 1.05MVar＜4MVar that bucking-out system is divided the man's cap used in ancient times rate.Like this, promptly satisfy the scvd requirement.This moment, compensation precision was the three-phase activity coefficient after the compensation (leading or lag behind) and the natural power factor of load
Figure C9910978400091
The situation of L-C series filter is not described in detail in detail, but experienced power supply engineering teacher is very clear herein, to be used for being provided with its filter effect of L-C series filter can be very desirable to the electric capacity of 18.9MVar altogether.
On the other hand, though filter only when having harmonic wave to suppress, just be provided with, if just relatively " totally " for example squirrel-cage asynchronous motor and incandescent lighting of load itself is provided with powerful filter like this and remains necessity because:
Filter 1), is not set, and this 18.9MVar building-out capacitor also must be installed in the system; For the restriction switching current impacts, the inlet wire reactance must be set; The numerical value that has only changed the inlet wire reactance behind the L-C filter is set;
2), prior reason is, after building-out capacitor is distributed to each L-C filter, the circuit natural mode shape that bucking-out system and supply transformer short-circuit parameter are constituted moves on to kept away the most serious load harmonic frequency, as three times, five times, the seventh harmonic frequency, and make the filter effect of bucking-out system meet expectation.
The present invention can be used in 50Hz, on 60Hz and the 400Hz electrical network reactive load power (no matter be leading or lag behind) is compensated.The present invention itself can not produce any harmonic pollution electrical network.The present invention to the power supply grid power supply quality without any specific (special) requirements, for example, no matter how supply power voltage fluctuates, and what are all unrestricted for the supply power voltage harmonic content, all can be remedied to the regulation that meets GB GB/T14549-93 to the voltage waveform that connects the site after connecting this device.
Description of drawings
The single-phase figure of accompanying drawing 1:SVS series compensation arrangement
The single-phase figure of accompanying drawing 2:FCTCR compensation arrangement
The single-phase figure of accompanying drawing 3:FCTSR compensation arrangement
Accompanying drawing 4:FCTSR compensation device system schematic diagram
Accompanying drawing 5: control circuit light current power supply and clock generator
Accompanying drawing 6: load current signals collecting and Filtering Processing circuit
Accompanying drawing 7: with the clock waveform figure of relevant voltage homophase
Accompanying drawing 8: sampling logic oscillogram
Accompanying drawing 9: load character identification circuit
Accompanying drawing 10: three-phase load hysteresis recognition logic oscillogram
Accompanying drawing 11: the leading recognition logic oscillogram of three-phase load
Accompanying drawing 12:A/D change-over circuit
Accompanying drawing 13:Y/ Δ change-over circuit
Accompanying drawing 14: display circuit
Accompanying drawing 15: switching power amplifier level
The circuits for triggering of accompanying drawing 16:uv phase Lo noncontacting switch SWo
Accompanying drawing 17:uv phase SWo triggers switching and Lo current waveform
The circuits for triggering of the TSC working method noncontacting switch SWo of accompanying drawing 18:FCTSR
Accompanying drawing 19:uv phase SWo triggers switching and Co current waveform
Embodiment
The present invention is made of the reactive power compensation element and the controller of thyristor contactless switch element, contactless switch element switching.Noncontacting switch switching of the present invention is pressed the switched inductors of binary system flexible strategy setting member reactive power capacity, and the reactive power capacity of every phase N branch switch inductance is by 1,2,4,8 ... 2 N-1Be provided with; Every by some groups of parallel connections of L-C series filter, apparent load harmonic current frequency distribution and deciding, as secondary, three times, five times, seven is inferior; The capacity flexible strategy of L-C series filter first-harmonic equivalent capacitance should be 2 N-1, can provide flexible strategy from 0 beginning, 1,2 to 2 N-1 totally 2 NThe compensation grade of individual arithmetic series; Compensation arrangement resolution is 1/2nd flexible strategy; Every definite scvd standard of electrical network being glimmered according to Britain of propping up way N mutually, the residue reactive power that is not promptly compensated should meet site capacity of short circuit S less than equaling compensation arrangement at the most BC2 percent; / 2nd flexible strategy of resolution (three-phase) that are compensation arrangement should be less than equaling S at the most BC2 percent.When as regional compensator, the flexible strategy of switched inductors reactive power capacity are respectively 1,2 ... 2 N-1-1, all L-C series filters are 2 in mains frequency equivalent capacitance reactive power capacity flexible strategy N-1-1.
FCTSR compensation arrangement schematic diagram of the present invention as shown in Figure 4.The compensation major loop is noncontacting switch SW with identical shown in the accompanying drawing three among the figure 0, SW 1... SW nRepresent with general switch symbols.CS is a current sensor among the figure, can be passive type, as current transformer; Can be active formula also, as Hall element.CS 1Measure the mains side supply current.CS 2Metrophia compensation device electric current.The load current signal that the difference of two signals is promptly compensated.Load current signal and voltage signal are delivered to controller in the lump.Signal produces the corresponding noncontacting switch of switching signal triggering that needs through handling, and the offset current that the compensation major loop is sent satisfies the compensation rate of load current needs, makes from power supply and sees that load power factor is as far as possible near 1.00.Above task is finished by controller.
The controller that the present invention adopts is a kind of electronic circuit controller of the Y/ of having Δ translation operation function, is made of clock generator, signals collecting and treatment circuit, switching display circuit and switching power amplifier.
Clock generator adopts NOR gate circuit, comprise No. six square-wave generators, wherein three the tunnel is the phase voltage square-wave generator of the phase voltage homophase of input and three phase mains, its output is wire size 13,14,15 in accompanying drawing 5, three the tunnel is the line voltage square wave generator of the line voltage homophase of input and three phase mains in addition, and its output is wire size 10,11,12 in accompanying drawing 5; Line voltage square wave generator all has three tunnel outputs, and the phase voltage square-wave generator then all has two-way output; Mutually wherein a tunnel (correspondence be wire size 13) of phase voltage square-wave generator exported and all is input to buffer by XOR gate before wherein one tunnel output (for example wire size 10) of line voltage square wave generator and this line voltage neck, the output of its correspondence is wire size 25, all the other two buffer output wire sizes are respectively 26,27, each buffer divides three tunnel outputs, but the first via outputs to four ternary output registers of three chip selects arranged side by side of Y/ Δ change-over circuit in signals collecting and the treatment circuit and does the chip select of load line electric current A/D output and deposit control (referring to accompanying drawing 13 on the limit 25,26, article 27 3, control line), the second the tunnel directly triggers monostable circuit (in the present embodiment, the monostable output Q of wire size 25 triggerings is a wire size 280, and Q is non-to be 28; The monostable output Q of wire size 26 triggerings is a wire size 290, and Q is non-to be 29; The monostable output Q of wire size 27 triggerings is a wire size 300, Q is non-to be 30), Third Road triggers a monostable circuit (its output Q is a wire size 1890) that three-way voltage square wave generator is shared by one three input or door, the Q output of the monostable circuit that each directly triggers divides two-way, one tunnel corresponding four switchings that all output to Y/ Δ change-over circuit in signal acquisition circuit and the treatment circuit by one two input and door with the Q output of the shared monostable circuit of three-way voltage square wave generator are deposited control according to register do chip select, and (its corresponding wire size is 31,32,33), three input of another road to one or Men Jingsan the paraphase that directly trigger the Q output of monostable circuit output to Y/ Δ change-over circuit control EPROM addressing operation (its corresponding wire size is 999) in signals collecting and the treatment circuit, and two inputs in addition of described three inputs or door are two other Q output signals that directly trigger monostable circuit; Directly but non-four the ternary output registers of three chip selects that output to Y/ Δ change-over circuit in signals collecting and the treatment circuit of monostable Q that trigger are done chip select output control in order to produce the EPROM address code (referring to 28,29,30 3 control lines in accompanying drawing 13 left sides) that needs, and (for example wire size 28 is L but four ternary output registers of described three chip selects are deposited signal corresponding to three load line electric current A/D respectively A1, L B1And L C1Totally ten two output codes are according to being put on the EPROM address wire to low level from high-order); Another road of line voltage square wave generator then outputs to variable connector control XOR gate (such as wire size 10), another input signal of this variable connector control XOR gate is the reversed phase signal (corresponding wire size is 24) of square-wave generator of another line voltage of leading these line voltage 120 degree, and the output signal of this variable connector control XOR gate is a signals collecting and one of the control signal of the variable connector of treatment circuit (corresponding wire size is 35); The Third Road output signal of line voltage square wave generator (is example with wire size 10) is input to another variable connector control XOR gate through (corresponding wire size is 22) after the phase inverter paraphase, another input signal of this variable connector control XOR gate be lag behind these line voltage 120 degree another line voltage square-wave generator square-wave signal (corresponding to above-mentioned be wire size 11 for example, so produce totally three of variable connector control signals, except that the top wire size of mentioning for example 35, also have 36,34); The second tunnel output signal of phase voltage square-wave generator is by the paraphase of two-stage phase inverter, and the output signal of two phase inverters all is input to the load character identification circuit and the switching power amplifier (corresponding wire size is 16,17,18,19,20 and 21 6) of signals collecting and treatment circuit.
In the present embodiment, priority encoder 4532 prime variable connectors 4066 operating frequencies are 2K times of mains frequency, and wherein K is the number of phases of electrical network; To three-phase system K=3; The variable connector frequency is 6 times of mains frequencies;
Signals collecting and treatment circuit are made up of according to circuit signals collecting and filter circuit, multi-channel electronic switch, A/D change-over circuit, Y/ Δ change-over circuit, load current property identification circuit, switching.Signals collecting and filter circuit are handled the back respectively to the three-phase load current signal of gathering and are divided two-way output, one the tunnel outputs to multi-channel electronic switch, carry out sending into Y/ Δ change-over circuit after the A/D conversion through the A/D change-over circuit, another road is shaped to the paraphase square wave and outputs to the load character identification circuit, output code by this circuit control Y/ Δ change-over circuit, the output code of Y/ Δ change-over circuit divides three the tunnel to output to three corresponding switchings respectively according to circuit, and three switchings are according to corresponding respectively to three line voltages.
As shown in Figure 6, signals collecting and filter circuit are by five operational amplifiers, a comparator and an electronic switch and a buffer are mixed the active filter that corresponding resistance capacitance is formed, and the current signal that collects is changed into the first-harmonic absolute value signal for the A/D conversion.
The multi-channel electronic switch way is consistent with the electrical network number of phases, by the way of described clock generator control variable connector with 2K times of mains frequency switching A/D, makes every mutually per half grid cyclic wave carry out an A/D conversion, a Y/ Δ conversion.
The A/D change-over circuit is by selector switch, be subjected to the resistance cascade circuit that can produce threshold voltage of selector switch control, 15 comparators, two three priority encoders, three dual inputs or door and four dual inputs and door formation, it is at most 15 threshold voltages that selector switch can produce three or seven by the controlling resistance cascade circuit, send into corresponding comparator heteropolarity input, the same polarity input of 15 comparators connects together and is used to receive output signal from multi-channel electronic switch, comparator compares back generation code signal to two kinds of signals and outputs in three priority encoders of two tandems, be connected on the Ein termination+5V power supply of first priority encoder of high eight-bit threshold comparator output terminal, thereby its Eout terminates to the Ein end of second priority encoder of low seven threshold comparator output terminals constitutes the priority encoder tandem, the corresponding output of two three priority encoders produces low triad sign indicating number output by two inputs or door, the GS end of first priority encoder outputs to the highest order of four output codes of A/D, four output codes of A/D are received four dual inputs and door respectively, another input of four dual inputs and door is used to receive the locking signal from the output of load character identification circuit, dual input and door to two kinds of signals of input carry out with computing after output to Y/ Δ change-over circuit.
But Y/ Δ change-over circuit is by three groups of chip select input registers, an EPROM, four XOR gate, three address switches and three switchings constitute according to register, every group of input register formed by three four ternary output registers arranged side by side, deposit control signal and the equal input register of chip select output control signal by the chip select that clock generator produces, be respectively applied for four output signals of A/D from the A/D change-over circuit are selected to deposit, every group of three input registers are imported simultaneously and are deposited and select output, respectively select an input register to output to the address bus of EPROM simultaneously in three groups, EPROM receives the addressing operation signal that produces from clock generator, four output codes of EPROM are outputed to an input of four XOR gate according to this signal by corresponding address switch, another input of four XOR gate is connected together and is used to receive signal from the load character identification circuit, XOR gate outputs to switching according to register according to this signal with true form or radix-minus-one complement, and switching links to each other with the switching display circuit with the switching power amplifier according to the output of register.
Load current property identification circuit is by 6 d type flip flops, one six input nand gate, one six input NOR gate, two XOR gate and two address switches constitute, per two d type flip flops are one group, be respectively applied for and receive three out of phase relevant signals, the D input of two d type flip flops of wherein same group all is used to receive the line current paraphase square-wave signal of same phase, the C input of a d type flip flop is used to receive the square-wave signal of phase voltage, the C input of another d type flip flop is used to receive phase voltage square wave reversed phase signal, in the same group of trigger, the C input is input as the Q output of phase voltage square-wave signal and the non-output of Q that the C input is input as phase voltage square wave reversed phase signal and all imports six input nand gates and six and import NOR gate, the output of six input nand gates links to each other with one of them XOR gate, another input of this XOR gate is connected to+the 5V power supply, its output divides two-way, the address switch of leading up to outputs to Y/ Δ change-over circuit and switching display circuit, another road outputs to another XOR gate, another input of this XOR gate is used to receive the output signal from six input NOR gate, and its output outputs to four dual inputs and door and switching display circuit in the A/D change-over circuit by another address switch.
Switching is made up of the XOR gate coding circuit that is subjected to the control of load current property identification circuit according to forming circuit, thereby its effect is to notify Y/ Δ transformation result the circuits for triggering of noncontacting switch to make the switching effect meet expectation with true form or with radio-minus-one complement form or with the hybrid code form.
The switching display circuit is imported NOR gate and corresponding 22 LED light-emitting diodes and three phase inverters by 12 XNORs and 21 three-states two and is constituted, the input of XNOR is used to receive from the signal of switching according to circuit, except that the XNOR of every phase highest order only links with a three-state two input NOR gate, the output of all the other each XNORs joins with the input that two three-states two are imported NOR gate respectively, another input of each ternary two input NOR gate is used to receive control signal and the control signal of this signal after the phase inverter paraphase from the load character identification circuit, and its output then links by current-limiting resistance and LED light-emitting diode; 21 three-state two input NOR gate are divided into two groups, one group is 12, drive 12 green LED, another group is 9, drive 9 red LED, be respectively applied for and receive two kinds of logical signals that come from the load character identification circuit, one altogether yellow led by a logical signal of load character identification circuit through twice paraphase rear drive, this logical signal is when the driving yellow led is bright, blocked A/D output, also blocked 12 green LED and 9 red LED, shown that whole device is in the wait state of no switching compensation.
The switching power amplifier has three groups, every group respectively corresponding to different phases, constitute by 8 unit, each unit is by a d type flip flop, one two input nand gate and an optoelectronic isolating element and a pulse transformer are formed, the D input of d type flip flop is used to receive the signal of switching according to circuit, an input of its Q output and two input nand gates links, another input of two input nand gates and the input end of clock C of d type flip flop join, the input that its output is isolated by current-limiting resistance and photoelectricity links, photoelectricity is isolated input positive termination+5V power supply, the output that photoelectricity is isolated is connected to pulse transformer, by the secondary thyristor contactless switch element that triggers of pulse transformer; Shared one of per four d type flip flops come from the clock signal that clock generator produces, and each group switching power amplifier all receives two clock signals, and these two clock signals are paraphase mutually; The clock that each group switching power amplifier is received is the clock signal that this group switching produces according to the third phase phase voltage beyond the relevant two-phase of homologous lines voltage, in order to be connected across the positive half cycle of noncontacting switch and the negative half period trigger impulse of break-make compensating element, on this line voltage synchronously.
Below to dividing four aspects that the operation principle of controller of the present invention is described further:
1. signals collecting and processing.For the purpose of comparing, will mention 89103959.7 frequently in this specification with Chinese patent 89103959.7.89103959.7 the compensation arrangement of being supported supposition load all is hysteresis property without exception, so sampling system is only gathered the positive peak of reactive load electric current.Sampling system of the present invention must judge that also this reactive current is that lag behind or leading except that the positive and negative peak values of gathering each phase reactive current.Because, if load lags behind, palpus input compensation electric capacity, and if load is leading, then must the input compensation inductance.In addition, 89103959.7 every grid cyclic waves are to every phase acquisition and handle a signal, and the present invention be per half grid cyclic wave promptly to every phase acquisition with handle a signal, speed is doubled, so switching behavior speed also is doubled.Accompanying drawing 5 is control circuit light current power supply and clock part.Appropriate section promptly is doubled in signal 34,35 that is produced by XOR gate and 36 frequency ratios 89103959.7, makes Fig. 8 variable connector operating frequency bring up to 300Hz (50Hz electrical network) by 150Hz, or perhaps six times of mains frequency.Accompanying drawing 6 promptly is load current signals collecting and Filtering Processing, has three the tunnel.Self-evident, this is for three-phase system.If power supply is the K phase, current acquisition has the K road certainly.Five 324 operational amplifiers of each route and one 339 comparator and a noncontacting switch 4066 and a buffer are mixed suitable resistance capacitance and are formed.With the first via is example, and the load current signal is from 46 inputs, and 48 output signals are 46 first-harmonics " full-wave rectification " signals.This passage is an active filter in fact, and 100Hz signal attenuation is 16%, and 150Hz signal attenuation is 4%, and 250Hz signal attenuation is 0.6%, and more the high-frequency signal decay is bigger.Can think that 48 signal promptly is the load current fundamental signal.49 is the square-wave signal of load current fundametal compoment antiphase.Clock pulse is and the square-wave signal of relevant voltage in-phase signal, sees accompanying drawing 7.Sampled signal is seen accompanying drawing 8.Accompanying drawing 9 is load signal property identification circuit.It is realized with d type flip flop 4013.With first via sampled signal 49 is example, receives D 1And D 2The D input, D 1Clock is that a1 is the synchronous square wave clock pulse 17 of phase voltage U.D 2Clock is that a1 is the square wave clock pulse 16 (all seeing accompanying drawing 7) of phase voltage U paraphase position.If load current lags behind, then its output signal 401 and 412 is H, and in like manner signal 501,512, and 601 and 612 are H.Like this, signal 468 is H, and 478 is L.In other words, the while 478 is L if signal 468 is H, promptly represents three-phase load to lag behind.Three-phase load hysteresis identification oscillogram is seen Figure 10.Figure 11 is that three-phase load is leading identification, and this moment, 468 signals were that L while 478 signals are H.If three-phase load is existing also in advance a hysteresis, 468 and 478 signals are L simultaneously so.See Table 2:
Load character Logical relation
468 points 478 points
Three-phase all lags behind H L
Three-phase is all leading L H
Having has hysteresis in advance L L
Table 2: load character is discerned in addition, and 48 signals are absolute value signal of 46 signal first-harmonic content.Absolute value signal is by comparator 339, noncontacting switch 4066 and operational amplifier 324 realizations.Because be absolute value signal, just make the every grid cyclic wave of control circuit that this phase current is carried out twice A/D conversion and have same precision becoming possibility.
The second portion of signal processing is the A/D conversion.From hardware aspect, the present invention compares much at one with 89103959.7, and as shown in figure 12, but the variable connector operating frequency is doubled.Each grid cyclic wave divides six continuous time zones, successively to the positive half cycle of U specific electric load electric current (49 signals), W specific electric load electric current negative half period (56 signals), the positive half cycle of V specific electric load electric current (52 signals), U line current signal negative half period (49 signals), the positive half cycle of W specific electric load electric current (56 signals) then V line current signal negative half period (52 signals) carries out the A/D conversion, then begins the circulation in six time zones of second cycle.The mid point in a sixth cycle time zone of each A/D conversion promptly is that phase voltage of the same name becomes positive zero crossing from just becoming negative or thinking highly of oneself.59 points of Figure 12,60 points, 61 and tetrad sign indicating number of 62 output signals formations, 59 is the highest order sign indicating number, 62 is minimum bit code.The signal digitalized back of U line current tetrad sign indicating number deposits into three 4508 register L simultaneously A1, L A2And L A3See accompanying drawing 13.In like manner, the V line current deposits into L after signal digitalized B1, L B2And L B3Deposit into L after the W line current is signal digitalized C1, L C2And L C3Because store the moment by 4508 (2) pin or (14) pin, i.e. set control end control, the set moment is in phase voltage zero passage of the same name constantly just as can be known from accompanying drawing 8.This moment load current instantaneous value is the peak value of its idle component just.In other words, memory L A1-L A3Middle canned data is the size of U line current idle component, L B1-L B3In the information that stores be the size of V line current idle component and L C1-L C3The middle information that stores is the size of W line current idle component.This principle was set forth in 89103959.7, but 891G3959.7 only stores the reactive current positive peak, and each grid cyclic wave upgrades once.The present invention alternately stores reactive current positive peak and negative peak, and per half grid cyclic wave upgrades once.In other words, 89103959.7 three memory stores is, for example: first memory is current sampled value, the reactive current positive peak of u line current iu for example, second memory stores be the reactive current positive peak of W line current iw before 1/3rd grid cyclic waves, the 3rd memory stores be V line current iv reactive current positive peaks before 2/3rds grid cyclic waves.89104223.7 set forth with these three storage values foundation that to be converted into the equivalent reactive current component of Δ connection be fling-cut switch electric capacity.
Three groups of memory stores of the present invention be, for example: first group of memory stores be current sampled value, the reactive current positive peak of U line current iu for example, second group of memory stores be the reactive current negative peak of V line current iv before the sixth grid cyclic wave, the 3rd group of memory stores be the reactive current positive peak of 1/3rd grid cyclic wave W line current iw.The foundation that it is switching compensation rate (electric capacity or inductance) that so the present invention is converted into the equivalent reactive current component of Δ connection than 89104223.7 foundation want " newly " many, this is the speed reason more fast again than SVS device that the present invention responds.
The third part of signal processing is the conversion of Y/ Δ.This part principle is same as patent of invention 89104223.7, but the technology realization wants much succinct.Figure 13 is seen in Y/ Δ conversion of the present invention.89104223.7 in used two nineteen integrated circuit chips to realize Y/ Δ conversion, particularly used 4503 numerous tri-state gate circuits.The present invention selects the memory 4508 with chip select function for use, and itself just has the high-impedance state performance its output, so only used eight integrated circuit chips altogether: six 4508, a slice 4070 and a slice 27c256 have promptly realized the conversion of Y/ Δ.The solder joint number of this part has only 40 percent of 89104223.7 solder joint number, has improved reliability greatly.Other 89104223.7 Y/ Δ transformation results are stored in L Ab, L BcAnd L CaIn information without exception be the transformation result true form, and the present invention may be a true form, also may be radix-minus-one complement, also may be hybrid code by the control of load character testing circuit, depend on that also bucking-out system is operated in TSC mode or FCTSR mode.
2. switching foundation.Switching foundation of the present invention is memory L Ab, L BcAnd L CaCanned data.As mentioned above, the stored information content depends on that the working method of bucking-out system is TSC or FCTSR.When the FCTSR working method, memory contents is the true form or the radix-minus-one complement of Y/ Δ transformation result by the decision of load character testing circuit, or hybrid code.Details are as follows:
1). bucking-out system TSC working method.In this working method, the direct switching building-out capacitor of noncontacting switch is as patent of invention 89103959.7 and the 89104223.7 SVS compensation arrangements of supporting.Why the TSC working method also has market to be because a large amount of users still is that harmonic content is low but need the situation of reactive power compensation.The compensation arrangement cost of TSC working method is compared with the compensation capacity apparatus cost with the FCTSR working method will hang down 30% or more, so occupation rate of market is still very high.The SVS product of the compatible TSC working method of FCTSR control circuit perhaps so to say that of the present invention.When the TSC working method, the switch SW 2 of accompanying drawing 13 disconnects.If every phase four road building-out capacitors, then SW3 and SW4 are all closed.If every phase three road building-out capacitors, SW3 disconnects but the SW4 closure.Because SW2 disconnects, so four XOR gate 4070 all are operated in noninverting buffer device state, so L Ab, L BcAnd L CaMemory contents is the true form of Y/ Δ transformation result.This course of work is promptly the same with SVS, repeats no more herein.
2). bucking-out system is operated in the concentrated hysteresis load compensation way of FCTSR.For example, first kind of situation is that supply power voltage contains tangible harmonic content, the occasion that voltage waveform distortion is serious; Second kind of situation is that load current has very big harmonic content, as the welding machine of thyristor control, automobile factory's automobile body welding workshop spot welding group of planes; Perhaps commercial building, office building, its lighting all are the electricity-saving lamps that contains serious harmonic wave.To the compensation of this type load, SVS is powerless, can only use the FCTSR working method.But this type load still belongs to hysteresis property.At this moment, the switch SW 2 of accompanying drawing 13 is closed.64 signals among Figure 13 are brought by accompanying drawing 9.Switch SW 5 and SW6 all disconnect in the accompanying drawing 9.So 64 current potentials are that 4.5V is H to 4070 inputs, so four 4070 of accompanying drawing 13 are operated in the phase inverter state.Like this, L Ab, L BcAnd L CaCanned data is the radix-minus-one complement of Y/ Δ transformation result.When this kind working method, switching holds according to the reason that why is the radix-minus-one complement of Y/ Δ transformation result and illustrates with a numerical example.If 48 points in the accompanying drawing 6,52 and 56 three-phase load current detection values are followed successively by iu, iv and iw.Deposit L after the digitlization in A1,2,3For [iu] is the idle component peak value of iu, be a tetrad sign indicating number, be made as 1101B.Be the decimal system 13, L B1,2,3Storing value [iv] is the tetrad sign indicating number of iv idle component peak value, is made as 1001B, and promptly the decimal system 9; L C1,2,3Storing value [iw] is the tetrad sign indicating number of the idle component peak value of iw, is made as 0101B, and promptly the decimal system 5.The same with 89104223.7, Y/ Δ conversion Calculation is that transformation result is by going out that the EPROM27C256 addressing of accompanying drawing 13 is tabled look-up: [iuv]=3 * [iu] * [iv]/([iu]+[iv]+[iw])=1101B[ivw]=3 * [iv] * [iw]/([iu]+[iv]+[iw])=0101B[iwu]=3 * [iw] * [iu]/([iu]+[iv]+[iw])=0111B result of calculation shows and should drop into the i.e. 13 grades of building-out capacitors of 1101B on the uv line voltage; Should drop into 0101B on the vw line voltage is the Pyatyi building-out capacitor; Should drop into the i.e. seven grades of building-out capacitors of 0111B on the wu line voltage.Because be that FCTSR concentrates the load compensation work mode that lags behind, building-out capacitor is fixed, and to every phase four road compensating inductances, the situation of reactive capability is set with the binary system flexible strategy, the fixed capacity of Δ connection, every is that 1111B is 15 grades of the decimal systems mutually, every phase switched inductors four tunnel, and first via flexible strategy are 1, the second right of way number is 2, the Third Road flexible strategy are that 4, the four right of way numbers are 8, and flexible strategy are i.e. ten Pyatyis of 1111B altogether.Switching be switched inductors.L AbStorage be that the radix-minus-one complement of [iuv] is 0010B, promptly the decimal system 2, L BcStorage be that the radix-minus-one complement of [ivw] is that 1010B is the decimal system 5, L CaStorage be that the radix-minus-one complement of [iwu] is 1000B.Like this, dropping into 0010B on the uv line voltage is the secondary switch inductance; Drop into the i.e. ten grades of switched inductors of 1010B on the vw line voltage; Drop into the i.e. eight grades of switched inductors of 1000B on the wu line voltage.And fixed capacity all is i.e. ten Pyatyis of 1111B on each line voltage.So dropping into clean leading reactive power on the uv line voltage is 15-2=13, the clean leading reactive power that drops on the vw line voltage is 15-10=5, and the clean leading reactive power that drops on the wu line voltage is 15-8=7, this needed just offset.
3). bucking-out system is operated in FCTSR area compensator working method.This kind working method is used in 3.3kv electric pressure or higher electric pressure, 6kv for example, 10kv, 35kv etc.When being used in this working method, the SW2 closure of accompanying drawing 13, SW3 disconnects, SW4 closure (every phase four-way switch inductance) or disconnect (every phase three-way switch inductance).The SW5 of accompanying drawing 9 and SW6 are all closed.With numerical example L is described Ab, bcWith CaMemory contents and switching process.During this kind working method, the fixed capacity flexible strategy are relevant with the switched inductors way.If the every phase four tunnel of switched inductors, flexible strategy are respectively 1,2,4 and 7 (not being 8) fixed capacity flexible strategy is 7 (not being 8).If switched inductors is every phase three tunnel, then flexible strategy are respectively 1,2 and 3 (not being 4), and the fixed capacity flexible strategy are 3 (not being 4), and the SW4 of accompanying drawing 13 should disconnect during certain every phase three-way switch inductance.The switching foundation of every phase four-way switch inductance is described with numerical example.Divide three kinds of situations:
First kind of situation, three-phase load are hysteresis.If Y/ Δ transformation result: [iuv]=101B, [ivw]=001B, [iwu]=011B are according to table 2, and 468 is L for 478 of H.Know that from accompanying drawing 9 be H at 64,63 also is H.63 signals are received the public input of 12 4 two inputs of accompanying drawing and door, be used for blocking these four with door because be H, thus four with a door deblocking, the A/D output code is not blocked.64 signals are received four the 4070 public inputs of XOR gate of accompanying drawing 13, because be H, so four XOR gate are operated in the phase inverter state, because SW3 disconnects, so the tetrad sign indicating number highest order that XOR gate is formed is 0, back three is the radix-minus-one complement of Y/ Δ transformation result.L like this AbStored information is 0010B, L BcBe 0110B, L CaBe 0100B, the switched inductors of input is respectively a secondary, six grades and level Four.Because fixed capacity is seven grades, so the clean leading reactive power of compensation that drops into is Pyatyi successively, one-level and three grades, this needs just.Second kind of situation, three-phase load is in advance.Still establish Y/ Δ transformation result as first kind of situation.What illustrate a bit is, though numerical value is identical, and incompatibility, the expression load current is leading, bucking-out system should drop into corresponding hysteresis reactive power and compensate load.Know that according to table 2 when three-phase was leading load, be L at 468,478 is H.Like this, 64 is L, and 63 still is H.A/D output is not blocked.Four XOR gate of accompanying drawing 13 are operated in noninverting buffer device state.Because SW3 disconnects, so the tetrad sign indicating number highest order that four XOR gate output is formed H always, back three is Y/ Δ transformation result true form.When above-mentioned data are routine, L AbStored information is 1101B, L BcBe 1001B L CaBe 1011B.Highest order is to drop into flexible strategy 7 switched inductors, because of its flexible strategy equate with fixed capacity, is that 101B, 001B and 011B just in time suit the requirements successively so each drops into clean hysteresis reactive power mutually.
The third situation, load current have hysteresis are in advance also arranged.As regional compensator, this situation occurs in night to transition in the late into the night and the daybreak time zone to the transition in morning.Night, customer charge reduced gradually when late into the night transition, but certain user's hand throws compensation arrangement and may not operate a switch, and showed as capacitive on the single site network gradually so cause, and promptly single site network is gradually from lagging behind to leading transition.Daybreak, user's load that lags behind increased gradually when the morning transition, and single site network is from advance to the hysteresis transition.Online reactive power absolute value is very little in this special time zone, need not the bucking-out system intervention.From this paper table 2 as can be known 468 and 478 of accompanying drawing 9 be L.A/D is output as 0000B in the accompanying drawing 12.The 27C256 output of accompanying drawing 13 also is 0000B.Because 64 is L, so four XOR gate of accompanying drawing 13 are operated in noninverting buffer device state.Because SW3 disconnects, so the tetrad sign indicating number highest order of XOR gate output is 1, other three are 0.So, L Ab, L BcAnd L CaStored information is 1000B.In other words, each has only flexible strategy mutually is 7 switched inductors input, with flexible strategy be that 7 fixed capacity reactive power is offset.Bucking-out system does not have compensating action to load.There is not harmonic wave to produce when by the way, FCTSR is operated in this state.And if FCTCR is operated in this state,, could provide the harmonic current of fixed capacity rated current 30% to pollute electrical network to power supply network according to table 1!
Illustrate a bit have five toggle switch SW2-6 and a selector switch SW1 must be pre-set in control circuit at user's compensation work mode.The compensation work mode at user place is because of its load character, supply power voltage quality relative fixed in case the compensation work mode is definite, can not change, more than each switch can in control circuit, establish hardware and realize, the Programming of programmable controller that also can nationality helps compensation arrangement realizes.
3. switching shows.According to the 2nd) the joint switching according to described in three kinds of working methods of this scheme:
1) TSC working method
2) FCTSR concentrates the load working method that lags behind
3) FCTSR area compensator working method
Preferably provide display message intuitively to the operations staff.To the 1st) and 2) two kinds of working methods preferably provide " building-out capacitor " progression of input, i.e. the information of the difference of the hysteresis reactive power of the switched inductors of the leading reactive power that provides of fixed capacity and input.And to the 3rd) plant working method, preferably provide " building-out capacitor " progression information of input when lagging behind at load, provide the information of input " compensating inductance " when being leading at load.When bucking-out system does not externally afford redress, also corresponding demonstration should be arranged, cause illusion to think that bucking-out system has the operation of fault refusal with the exempt from customs examination operations staff.Display part of the present invention is designed according to above-mentioned requirements.
Accompanying drawing 14 is display parts of the present invention.Display message comes from the L of accompanying drawing 13 Ab, bcWith CaOutput 65-68,69-72,73-76 totally three tetrad sign indicating numbers.Control signal 78 comes from the end of the SW2 of accompanying drawing 13, and this signal is used for controlling biconditional gate 5-1～4, the operating state of 6-1～4 and 7-1～4.12 green LED of left bank are driven by the NOR gate 4502 of corresponding controlled output, show the progression of " building-out capacitor ".Nine red LED of right row are shown the progression of " compensating inductance " by corresponding 4502 controls.Narrate the display message of three kinds of working methods of compensation arrangement below respectively.
1) TSC working method: because the SW5 of accompanying drawing 9,6 all disconnect, thus 63 and 64 be H, so 21 4502 gate control ends are L, output determines by importing.Because 3-2～4,3-6,4-1～2, the public input end signal 64 that 4-4～6 nine are 4502 is H, so these nine doors outputs are L, nine red LED all do not work.And 12 4502 the public inputs in the left side are L, so another input signal is depended in its output.Because SW2 disconnects, 78 is L, so 12 biconditional gates all are operated in the phase inverter state.L Ab, bcWith CaWhat store is the true form of Y/ Δ transformation result, and 12 biconditional gates in the accompanying drawing 14 are all exported radix-minus-one complement, corresponding 4502 true forms that are output as Y/ Δ transformation result.Green LED shows is the binary code of the progression of " building-out capacitor " that drop into.The SVS control that this point and 89104223.7 is supported shows the same, is compatible.
2) .FCTSR concentrates the load working method that lags behind: because the SW2 closure, so 78 signals are H, 12 biconditional gates are operated in noninverting buffer device state in the accompanying drawing 14.So biconditional gate is output as L Ab, bcWith CaThe true form of stored information is the radix-minus-one complement of Y/ Δ transformation result, and what green LED showed is the true form of Y/ Δ transformation result, promptly drops into the progression of " building-out capacitor ".
3) .FCTSR area compensator working method.This moment SW2,5,6 is all closed.If every phase four-way switch inductance then SW3 disconnects, the SW4 closure, if every phase three-way switch inductance SW3 then, 4 all disconnect.Be that example illustrates with every phase four-way switch inductance below.
First kind of situation loaded to what lag behind, and 63 and 64 are H.64 H blocks nine 4502 on accompanying drawing 14 the right, so red LED does not all work.78 signals are H with 63, so 12 4077 of accompanying drawing 14 all are operated in noninverting buffer device state.L Ab, L BcAnd L CaStored information is the radix-minus-one complement of Y/ Δ transformation result, so 12 4077 radix-minus-one complements that are output as Y/ Δ transformation result.Corresponding 4502 are output as the true form of Y/ Δ transformation result, and green LED shows as the same, and what promptly show is that each drops into the progression of it " building-out capacitor " mutually.
Second kind of situation loaded to leading.63 is H, and 64 is L.12 4502 on accompanying drawing 14 left sides are blocked by public input signal, and all green LED all do not work.Nine the 4502 public inputs in the right are L, and its output depends on that another input is the output of biconditional gate 4077.Since 64 for L accompanying drawing 13 in four XOR gate 4070 be operated in noninverting buffer device state.So L Ab, bcWith CaThe highest order of three memory stores information is 1, and other three is the true form of Y/ Δ transformation result.It is 7 switched inductors that stored information highest order 1 enables (enable) flexible strategy, and its hysteresis reactive power and fixed capacity leading reactive power are offset.The hysteresis reactive power that low three switched inductors that enable are input just in time compensates the leading reactive power of load.The low triad sign indicating number information of corresponding registers is only accepted on nine 4502 on accompanying drawing 14 the right.Because 78 is that 64 signals are L, so biconditional gate 4077 is operated in the phase inverter state.Like this, what red LED showed is the low triad sign indicating numbers of three memory stores, i.e. the progression of " compensating inductance " of Tou Ruing (not showing that flexible strategy are 7 switched inductors input, because it is that to be used for offsetting flexible strategy also be 7 fixed capacity).
It is leading that the third situation, three-phase load have, the hysteresis that has.At this moment, 63 and 64 two be L, accompanying drawing 14 all 4502 equal controlled terminals block the output high-impedance state.So all are red, green LED does not all work.But because of 63 being L, so yellow led is bright.This signal prompt operations staff, bucking-out system fault-free, just act without compensation under this operating mode.By the way, act without compensation is to realize when flexible strategy are 7 switched inductors input.Display message such as above-mentioned design come into plain view the operations staff: how many compensation capacities are bucking-out system drop into this moment on earth, are leading or that lag behind or act without compensation.
4. switching power amplifier.Switching basis signal essence be switching power amplifier level enable (enable) signal.Switching power amplifier example such as accompanying drawing 15.Every cover compensation arrangement has the same switching power amplifier level of three covers.15 in the accompanying drawing cover switching power amplifier level of having drawn.For clarity sake, used three kinds of mark systems to indicate three cover power amplifier levels respectively among the figure.Zero mark system is corresponding to the UV phase, and mark system is corresponding to the VW phase, and ◇ mark system is corresponding to the WU phase.Have only output light every external power supply 100 for just, 181 for negative be public, in zero mark system, outpour among the figure, do not use and ◇ repeat mark.As can be seen, every cover switching power amplifier level is made up of eight identical unit.Self-evident, this is corresponding to every phase N=4.If N=3, every cover have only six unit to form, in general, every phase N branch road should have 2N unit to form this cover switching power amplifier level.Each unit is made up of every for example 2G03DIC 4011 light of 4013, one dual input NAND gate of a d type flip flop.4013 D input (5) end or (9) end promptly trigger foundation or claim enable signal to come from the latch L of accompanying drawing 13 Ab, bcWith CaBring in from accompanying drawing 5 4013 clock signal (3) end or (11).With UV phase switched inductors L 0For example illustrates trigger mechanism.Corresponding noncontacting switch from accompanying drawing 3 as can be known by thyristor T 10And T 30Inverse parallel is formed.Corresponding switching power amplifier group is that zero mark system is mixed in two unit in accompanying drawing 15 lower-lefts and bottom right.Accompanying drawing 16 is these noncontacting switch circuits for triggering details.Accompanying drawing 17 is corresponding oscillograms.Suppose the t=0 moment at accompanying drawing 17, phase voltage u thinks highly of oneself and becomes positive zero passage L constantly AbThe minimum bit code that latchs (68 point) is 1, then the d type flip flop D of accompanying drawing 16 101And D 103The D input be H.D 101Clock signal 20 forward positions are t constantly 1Trigger D 101Make (13) pin become H, light is every at t 1Conducting constantly, 101 pulse voltages with 181 are added to the pulse transformer PTF of accompanying drawing 16 10At the beginning of the level, thereby thyristor T 10Triggering and conducting.Because pulse front edge is the positive peak moment of line voltage uv constantly, so inductance L 0Electric current be from the sine wave of zero beginning as shown in Figure 17, do not have transient process.Trigger impulse 101 width are half grid cyclic wave.Suppose at phase voltage u from the zero passage moment of the negative transition of forward t 2, 68 still is H, i.e. d type flip flop D 103D be input as H, t constantly in (11) pin clock signal 21 forward positions 3The time, D 103Q output (13) pin become H, corresponding light is every conducting, trigger impulse 103 is by pulse transformer PTF 30Trigger thyristor T 30Conducting, L 0The electric current continuity is to negative half period.Suppose at the zero crossing t of the phase voltage u next one from the negative sense accelerating transition 4, became 0 from 1 at 68 o'clock, then D 101D input be zero, at t 5When constantly clock 20 forward positions occurred, defeated (13) pin of its Q was L, thus corresponding light every not conducting, T10 does not have trigger impulse, so L 0Electric current is kept null value after negative half period carries out the transition to 0.From top narration, obviously as seen, per half grid cyclic wave of controller is regulated a switched inductors input, and response speed is half grid cyclic wave.The thyristor trigger pulse width is that half grid cyclic wave is a TSC working method of considering the FCTSR compensation arrangement, i.e. the working method of the direct switching building-out capacitor of noncontacting switch.Accompanying drawing 18 is TSC working method noncontacting switch SW 0Circuits for triggering.The compensating circuit major loop as shown in Figure 1.Uv phase SW when accompanying drawing 19 is the TSC working method 0Triggering switching and C 0Current waveform figure.Noncontacting switch is made up of a power electronics diode and a thyristor inverse parallel when the TSC working method.The power electronics diode is used for capacitance voltage is biased in positive peak (also can be the negative peak value).When needs drop into this grade building-out capacitor, example as shown in Figure 19, during t=0 68 by L → H, t=t 1The time, D is triggered in the clock pulse forward position 101Make its Q become H, light is every logical, by the pulse transformer PTF of accompanying drawing 18 0Trigger T 0Connect capacitor C 0, C 0Both end voltage changes and C 0Current waveform as shown in figure 19, be sinusoidal wave.T 0When half grid cyclic wave of conducting finishes, C 0The negative half period zero passage.After this, D 0Half grid cyclic wave of conducting is again C 0Bias to the positive peak of line voltage uv.Because t 4Constantly 68 by H → L, so t 5Moment D 101Q be L, the triggerless pulse.C like this 0Be biased online voltage uv positive peak and wait for the triggering switching that next cycle is possible.From above-mentioned explanation as seen, each grid cyclic wave of noncontacting switch is adjusted a switching, and per half grid cyclic wave is adjusted a switching unlike switched inductors, though the speed of signals collecting and processing is constant, however switching foundation L during the TSC working method Ab, bcWith CaEvery renewal is utilized for twice once, and another time is unemployed, because that is corresponding to power electronics diode current flow time zone, this time zone is not controlled.From above-mentioned explanation as can be seen, when the TSC working method, controller switching power amplifier part, promptly the right half part of accompanying drawing 15 is must outlet.
2 explanations.The first, when installed capacity is bigger, select for use the thyristor rated current of making noncontacting switch bigger, the triggering power ratio that needs is bigger, controller switching power amplifier light every and pulse transformer between must add power-amplifier stage so that reliably trigger thyristor.The second, when compensation arrangement is used in high electric pressure, 10kv for example, during 35kv, noncontacting switch is the two string infrared triggering thyristor of same model specification (cache thyristor) inverse parallels.Because infrared light triggering part and the reliable voltage isolation of thyristor main body, as long as being triggered the input series connection, same shish-kebab brake tube triggers input as one, export by controller switching power amplifier, for example 101 and 181, behind applied power amplifying stage power amplifier, trigger, antiparallel another shish-kebab brake tube triggers the input series connection by 103 and 181, triggers behind applied power amplifying stage power amplifier, and it triggers switching principle indistinction just and during low pressure.
4. computer simulation example: this is that the application FCTSR of a cement tube factory spiral reinforcement skeleton welding shop concentrates hysteresis load compensation example.Supply transformer 800kVA, 10kV/0.4kV is connected to five welding machines altogether.Welding machine is all single-phase, elementary 380V inlet wire, and two thyristor inverse parallels of secondary usefulness phase shift triggers control, and phase shifting angle is near α=90 ° are voltage peak, and phase shift is according to being that welding current is constant.This example is very typical asymmetric load, contains abundant harmonic current.The capacity of five welding machines is two 150kVA, three 50kVA.Before adding compensation, observe with oscilloscope, voltage waveform has spike that depression is also arranged, and is at random, because the working condition of five welding machines is at random, five welding machine work are irrelevant mutually.Because the voltage waveform distortion too SVS device of die TSC working method can't be competent at compensation task, a FCTSR-Δ U-0.4-252 who is about to installing learns with the PSPICE simulation, not only compensation precision is satisfied but also the harmonic current of injection electrical network also is suppressed to the GB/T14549-93 allowed band, and voltage distortion is lower than below 5% of GB/T14549-93 regulation.
The symbol note that uses in the simulation program is as follows:
V (3): V phase phase voltage, nominal value 220V (rms);
I (vou): supply transformer U line current;
I (viu): load U line current;
V (3,13): UV line voltage, nominal value 380V (rms);
V (13): V phase phase voltage, nominal value 220V (rms);
I (vov): supply transformer V line current;
I (viv): load V line current;
V (13,23): VW line voltage, nominal value 380V (rms);
V (23): W phase phase voltage, nominal value 220V (rms);
I (vow): supply transformer W line current;
I (viw): load W line current;
V (23,3): WU line voltage, nominal value 380V (rms).
The Fourier that lists above-mentioned 12 operational factors as a result among the f9904235.out analyzes the 3rd " Fourier Component " listed data of form and is the peak value of corresponding frequencies component, and effective value is 0.707 times of peak value.
For the purpose of eye-catching, if each device of bucking-out system in the file, such as switched inductors, the Fourier of the operational factor voltage and current of each time L-C series filter inductance capacitance analyzes form and all omits.File is the index of compensation effect and filter effect at last, calculates according to above-mentioned 12 operational factors, titled with the title of EVALUATION.From the index of calculating, bucking-out system connects the site: 3,13 and 5% the index all stipulated of 23 phase voltage distortion less than GB/T14549-93, and compensation effect makes three-phase activity coefficient be not less than 99%, and each phase power factor minimum is 0.9842.From destination file line voltage V (3,13), V (13,23) and V (23,3) see that it distorts also less than 5%.For the purpose of contrast, enclose in the lump the situation Simulation result file (filename f9904290.out) of the uncompensated device operation of system with the ruuning situation Simulation result file (filename f9904291.out) of SVS compensation arrangement.From f9904290.out as seen, it is the regulation that surpasses international GB/T14549-93 that voltage distortion reaches 7%, and natural power factor has only 0.7293, is must compensation.After adopting the SVS compensation arrangement, from f9904290.out as can be known, phasor power factor has compensated to more than 0.99 really.Regrettably, to the harmonic wave severe overweight of electrical network discharging: voltage distortion surpasses more than the regulation twice up to 15%.Harmonic current to the electrical network discharging is also bigger than the fundamental current of drawing from electrical network unexpectedly! The I (vou) of contrast this document, the Fourier of I (vov) and I (vow) analyzes and can find, and quintuple harmonics and the seventh harmonic current component are than loading with the subharmonic height.Especially the quintuple harmonics electric current is four times of load quintuple harmonics electric current unexpectedly! This be because the L-C parallel resonance natural mode shape that building-out capacitor and supply transformer winding leakage reactance are formed just about 250Hz due to.For the specific load of this class, be very unbefitting if adopt the SVS compensation arrangement, and the reliability of operation of SVS device own is subjected to serious threat.By the way, the SVS device does not have filter capacity, can not make the L-C series filter to the building-out capacitor of SVS device as FCTSR.If catastrophic result will occur like that, because the every grid cyclic wave adjustment of building-out capacitor input amount is once, series filter will be in the transient process always, its transient current not only can not dwindle the harmonic wave to the electrical network discharging, but opposite.

Claims (3)

1, a kind of reactive power compensator of aontactless switch, reactive power compensation element and controller by thyristor contactless switch element, contactless switch element switching constitute, and it is characterized in that controller is made of clock generator, signals collecting and treatment circuit, switching display circuit and switching power amplifier; Clock generator has two groups of outputs, and one group outputs to signals collecting and treatment circuit, and another group outputs to the switching power amplifier, controls the work tempo of aforementioned two circuit; Signals collecting and treatment circuit are handled the back to the load current signal that receives and are divided two-way output, and one the tunnel outputs to the switching display circuit, and another road outputs to the switching power amplifier, by the break-make of this circuit triggers thyristor contactless switch element,
Described clock generator comprises No. six square-wave generators, and wherein three the tunnel is the phase voltage square-wave generator of the phase voltage homophase of input and three phase mains, and three the tunnel is the line voltage square wave generator of the line voltage homophase of input and three phase mains in addition; Line voltage square wave generator all has three tunnel outputs, and the phase voltage square-wave generator then all has two-way output; Mutually wherein a tunnel the exporting and all be input to buffer of phase voltage square-wave generator before wherein one tunnel output of line voltage square wave generator and this line voltage neck by XOR gate, buffer divides three tunnel outputs, but the first via outputs to four ternary output registers of three chip selects arranged side by side of Y/ Δ change-over circuit in signals collecting and the treatment circuit and does the chip select of load line electric current A/D output and deposit control, the second the tunnel directly triggers monostable circuit, Third Road triggers the shared monostable circuit of three-way voltage square wave generator by one three input or door, the Q output of the monostable circuit that each directly triggers divides two-way, one the tunnel all outputs in signal acquisition circuit and the treatment circuit corresponding four switchings of Y/ Δ change-over circuit by one two input and door with the Q output of the shared monostable circuit of three-way voltage square wave generator deposits control according to register do chip select, three input of another road to one or Men Jingsan the paraphase that directly trigger the Q output of monostable circuit output to Y/ Δ change-over circuit control EPROM addressing operation in signals collecting and the treatment circuit, and two inputs in addition of described three inputs or door are two other Q output signals that directly trigger monostable circuit; Directly but non-four the ternary output registers of three chip selects that output to Y/ Δ change-over circuit in signals collecting and the treatment circuit of monostable Q that trigger are made the EPROM address code that chip select output control needs in order to generation, but four ternary output registers of described three chip selects are deposited signal corresponding to three load line electric current A/D respectively; Another road of line voltage square wave generator then outputs to variable connector control XOR gate, another input signal of this variable connector control XOR gate is the reversed phase signal of square-wave generator of another line voltage of leading these line voltage 120 degree, and the output signal of this variable connector control XOR gate is one of the control signal of the variable connector of signals collecting and treatment circuit; The Third Road output signal of line voltage square wave generator is input to another variable connector control XOR gate after through a phase inverter paraphase, and another input signal of this variable connector control XOR gate is the square-wave signal of square-wave generator of another line voltage of these line voltage 120 degree of lagging behind; The second tunnel output signal of phase voltage square-wave generator is by the paraphase of two-stage phase inverter, and the output signal of two phase inverters all is input to the load character identification circuit and the switching power amplifier of signals collecting and treatment circuit,
Described signals collecting and treatment circuit by signals collecting and filter circuit, multi-channel electronic switch, A/D change-over circuit,
Y/ Δ change-over circuit, load character identification circuit and switching constitute according to circuit, signals collecting and filter circuit are handled the back respectively to the three-phase load current signal of gathering and are divided two-way output, one the tunnel outputs to multi-channel electronic switch, carry out sending into Y/ Δ change-over circuit after the A/D conversion through the A/D change-over circuit, another road is shaped to the paraphase square wave and outputs to the load character identification circuit, output code by this circuit control Y/ Δ change-over circuit, the output code of Y/ Δ change-over circuit divides three the tunnel to output to three corresponding switchings respectively according to circuit, three switchings are according to corresponding respectively to three line voltages
Described A/D change-over circuit is by selector switch, be subjected to the resistance cascade circuit that can produce threshold voltage of selector switch control, 15 comparators, two three priority encoders, three dual inputs or door and four dual inputs and door formation, it is at most 15 threshold voltages that selector switch can produce three or seven by the controlling resistance cascade circuit, send into corresponding comparator heteropolarity input, the same polarity input of 15 comparators connects together and is used to receive output signal from multi-channel electronic switch, comparator compares back generation code signal to two kinds of signals and outputs in three priority encoders of two tandems, be connected on the Ein termination+5V power supply of first priority encoder of high eight-bit threshold comparator output terminal, thereby its Eout terminates to the Ein end of second priority encoder of low seven threshold comparator output terminals constitutes the priority encoder tandem, the corresponding output of two three priority encoders produces low triad sign indicating number output by two inputs or door, the GS end of first priority encoder outputs to the highest order of four output codes of A/D, four output codes of A/D are received four dual inputs and door respectively, another input of four dual inputs and door is used to receive the locking signal from the output of load circuit property identification circuit, dual input with the door to the input two kinds of signals carry out with computing after output to Y/ Δ change-over circuit
But described Y/ Δ change-over circuit is by three groups of chip select input registers, an EPROM, four XOR gate, three address switches and three switchings constitute according to register, every group of input register formed by three four ternary output registers arranged side by side, deposit control signal and the equal input register of chip select output control signal by the chip select that clock generator produces, be respectively applied for four output signals of A/D from the A/D change-over circuit are selected to deposit, every group of three input registers are imported simultaneously and are deposited and select output, respectively select an input register to output to the address bus of EPROM simultaneously in three groups, EPROM receives the addressing operation signal that produces from clock generator, four output codes of EPROM are outputed to an input of four XOR gate according to this signal by corresponding address switch, another input of four XOR gate is connected together and is used to receive signal from the load character identification circuit, XOR gate outputs to switching according to register according to this signal with true form or radix-minus-one complement, switching links to each other with the switching display circuit with the switching power amplifier according to the output of register
Described load current property identification circuit is by 6 d type flip flops, one six input nand gate, one six input NOR gate, two XOR gate and two address switches constitute, per two d type flip flops are one group, be respectively applied for and receive three out of phase relevant signals, the D input of two d type flip flops of wherein same group all is used to receive the line current paraphase square-wave signal of same phase, the C input of a d type flip flop is used to receive the square-wave signal of phase voltage, the C input of another d type flip flop is used to receive phase voltage square wave reversed phase signal, in the same group of trigger, the C input is input as the Q output of phase voltage square-wave signal and the non-output of Q that the C input is input as phase voltage square wave reversed phase signal and all imports six input nand gates and six and import NOR gate, the output of six input nand gates links to each other with one of them XOR gate, another input of this XOR gate is connected to+the 5V power supply, its output divides two-way, the address switch of leading up to outputs to Y/ Δ change-over circuit and switching display circuit, another road outputs to another XOR gate, another input of this XOR gate is used to receive the output signal from six input NOR gate, its output outputs to four dual inputs and door and switching display circuit in the A/D change-over circuit by another address switch
Described switching display circuit is imported NOR gate and corresponding 22 LED light-emitting diodes and 3 phase inverters by 12 XNORs and 21 three-states two and is constituted, the input of XNOR is used to receive from the signal of switching according to circuit, except that the XNOR of every phase highest order only links with a three-state two input NOR gate, the output of all the other each XNORs joins with the input that two three-states two are imported NOR gate respectively, another input of each ternary two input NOR gate is used to receive control signal or the control signal of this signal after the phase inverter paraphase from the load character identification circuit, and its output then links by current-limiting resistance and LED light-emitting diode; 21 three-state two input NOR gate are divided into two groups, one group is 12, drive 12 green LED, another group is 9, drive 9 red LED, be respectively applied for and receive two kinds of logical signals that come from the load character identification circuit, yellow led by a logical signal of load character identification circuit through twice paraphase rear drive, this logical signal is when the driving yellow led is bright, blocked A/D output, also blocked 12 green LED and 9 red LED, shown that whole device is in the wait state of no switching compensation
Described switching power amplifier has three groups, every group respectively corresponding to different phases, constitute by 8 unit, each unit is by a d type flip flop, one two input nand gate and an optoelectronic isolating element and a pulse transformer are formed, the D input of d type flip flop is used to receive the signal of switching according to circuit, an input of its Q output and two input nand gates links, another input of two input nand gates and the input end of clock C of d type flip flop join, the input that its output is isolated by current-limiting resistance and photoelectricity links, photoelectricity is isolated input positive termination+5V power supply, the output that photoelectricity is isolated is connected to pulse transformer, by the secondary thyristor contactless switch element that triggers of pulse transformer; Shared one of per four d type flip flops come from the clock signal that clock generator produces, and each group switching power amplifier all receives two clock signals, and these two clock signals are paraphase mutually; The clock that each group switching power amplifier is received is the clock signal that this group switching produces according to the third phase phase voltage beyond the relevant two-phase of homologous lines voltage, in order to be connected across the positive half cycle of noncontacting switch and the negative half period trigger impulse of break-make compensating element, on this line voltage synchronously.
2, reactive power compensator of aontactless switch as claimed in claim 1, it is characterized in that the thyristor contactless switch element can be the thyristor inverse parallel of two same model specifications, also can be a bidirectional thyristor or the identical thyristor inverse parallel of two strings, every string be made up of the thyristor of several same model specifications.
3, reactive power compensator of aontactless switch as claimed in claim 1, the reactive power compensation element that it is characterized in that the contactless switch element switching comprises switched inductors and L-C series filter, be connected across on the power supply after switched inductors and the series connection of thyristor contactless switch element, the L-C series filter also is connected across on the power supply.
CN 99109784 1999-07-15 1999-07-15 Reactive power compensator of aontactless switch Expired - Fee Related CN1112750C (en)

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