CN111262742A - SCA-based dynamic partially reconfigurable equipment resource virtualization and waveform deployment method - Google Patents

Abstract

The invention relates to a resource virtualization and waveform deployment method for a dynamic partially reconfigurable device based on an SCA (supervisory control and reporting architecture), which solves the problems that the conventional SCA specification and related implementation only provide support for global dynamic reconfiguration of an FPGA (field programmable gate array), a DPR (distributed data recovery) technology is not supported, the reconfiguration granularity is too large, resources cannot be effectively multiplexed in a space-time mode and the like. The method establishes a mapping relation from a waveform component to a dynamic partial reconfigurable area of the FPGA. By designing and configuring the domain description file under the core framework, the overall architecture of a software system is not changed while the system functions are expanded under the SCA specification, the portability of components and the heterogeneity of a platform are ensured, and the development and maintenance complexity is reduced.

Description

SCA-based dynamic partially reconfigurable equipment resource virtualization and waveform deployment method

Technical Field

The invention relates to a mechanism for hardware device virtualization and software deployment in a software radio system. Specifically, the method uses eXtensible Markup Language (XML) to perform scheme design, has greater flexibility, and improves the hardware resource utilization rate and waveform deployment efficiency of a Software radio system.

Background

Various communication modes exist in the civil wireless communication field, wherein short-distance wireless communication mainly comprises WIFI, Bluetooth, Zigbee, REID and the like, and long-distance wireless communication comprises communication modes of satellite communication, 2G, 3G, 4G cellular networks and the like. At present, the development of the 5 th generation mobile wireless communication technology is actively promoted in all countries in the world, and the 5G communication can be widely applied to a plurality of aspects such as artificial intelligence, high-definition multimedia, unmanned driving, remote medical treatment and the like in the future. In the military field, taking the U.S. military as an example, the bandwidth of communication radio stations among various military types covers 2MHz-3GHz, and the communication systems are dozens. In the civil and military fields, hardware equipment platforms different from each other are brought by various communication systems, so that the software development and maintenance difficulty is high, and the upgrading period is long.

Software Defined Radio (SDR) technology is a third communication revolution following wired to wireless communication, analog to digital communication. The core of SDR is to build a standardized, generalized and integrated hardware platform, and realize the switching of communication modes by loading different communication waveform software. SDR systems can be divided into hardware platforms and software architectures, where the hardware platforms typically employ a general purpose processor CPU and reprogrammable, reconfigurable specialized processors such as FPGAs, DSPs, and the like. Hardware modularization design SDR hardware solutions for performing functions such as radio frequency, signal processing, analog-to-digital conversion and the like are also presented in the industry to adapt to different communication waveform requirements, such as hardware development platforms such as USRP, Sora and the like. The software system architecture is most widely applied to SCAs issued by Joint Tactical Network Centers (JTNC), and about 50 ten thousand software radio stations based on the SCAs are equipped in the army by 2017. In 2018, the American military uses SCA 4.1 as a mandatory standard to be popularized in the whole military, and marks that the SCA standard becomes a technical system and a development direction of a global military wireless communication system.

The Field Programmable Gate Array (FPGA) can realize the conversion of internal logic functions by loading different bit stream files, and the function reconfiguration can be divided into Dynamic global reconfiguration and Dynamic Partial Reconfiguration (DPR) according to the number of reconfiguration resources, and the resources of the whole chip can be reconfigured during the global reconfiguration, which will cause the waste of computing resources when the task instance occupies smaller resources. The DPR technology can enable different tasks to run in different areas of the FPGA at the same time without being influenced by each other, and the utilization rate of hardware resources is increased. However, the existing SCA specification and related implementation only provide support for global dynamic reconfiguration of the FPGA, do not support the DPR technology well, and result in that resources cannot be effectively multiplexed in space-time due to too large reconfiguration granularity. The invention designs the hardware resource virtualization and waveform deployment scheme of the DPR FPGA based on the SCA architecture, thereby exerting the advantages of the SCA and the DPR and improving the comprehensive performance and flexibility of the system.

Disclosure of Invention

In order to overcome the defects of large reconstruction granularity and low resource utilization rate of an FPGA in a software radio system based on an SCA system architecture, the invention provides a dynamic partial reconfigurable equipment resource virtualization and waveform deployment mechanism based on an SCA. The method carries out resource virtualization design on the domain description file of the logic device in the SCA by utilizing XML language, and comprises the related realization of FPGADPR and the dynamic partial reconfigurable deployment of waveform components. On the premise of not influencing the system function, the FPGA can realize space-time multiplexing, and the reconstruction granularity of the FPGA is reduced.

Under the architecture of the SCA, hardware equipment is abstractly encapsulated into logical equipment components, and each component has a corresponding domain description file to describe the information of the component such as the implementation, the port connection and the like. The domain manager starts, initializes, runs, configures and reconstructs corresponding application programs by analyzing the XML domain configuration file. The domain description file can be divided into a device package description file (DPD), a device configuration description file (DCD), a software assembly description file (SAD), a software package description file (SPD), a software component description file (SCD), an attribute description file (PRF), a domain manager configuration description file (DMD), etc. according to different description contents. In order to solve the problem of insufficient support of the reconfigurable capability of the FPGA dynamic part in the SCA specification, the SPD file and the PRF file are designed to complete the DPR resource virtualization and waveform deployment of the equipment, and the realization of the reconfigurable function of the dynamic part is completed on the premise of conforming to the SCA specification.

The SCA specification is a guarantee that a software radio system can exert platform heterogeneity and load software to complete function switching, and the invention provides a mapping process which is complete in waveform application creation, dependency check, capacity allocation and reconfigurable deployment in a domain aiming at dynamic partial reconfigurable deployment of software components under the SCA specification.

The technical scheme adopted by the invention is as follows: analyzing the resource virtualization of hardware equipment and the deployment mode of a software component based on an operation mechanism of an SCA, providing a plurality of partition modes through an SPD (Surge-protective device) and a PRF (pseudo random field function) domain description file of a logic equipment component, and reconfiguring a resource virtualization mode by an FPGA (field programmable gate array) dynamic part with a plurality of resource configurations;

providing a dynamic partial reconfigurable resource virtualization of the FPGA and a dynamic partial reconfigurable deployment mechanism of the component through an XML domain description file, and completing a series of operations of dependency check, capacity allocation and dynamic partial reconfigurable deployment by the SCA through analyzing an SPD and a PRF domain description file of a waveform component, thereby establishing a mapping relation between an FPGA reconfigurable region and the waveform component;

the method specifically comprises the following steps:

1. dynamic partially reconfigurable device resource virtualization

1.1 SPD File core elements and composition

In a software radio system based on an SCA architecture, physical computing equipment is modularized and designed into a logic equipment assembly, an FPGA with a reconfigurable dynamic part is subjected to software modularization through a basic equipment interface and a basic equipment assembly in a Core Framework (CF), and the logic equipment assembly supporting the DPR FPGA is abstractly packaged. The SPD file of the logic device assembly carries out resource virtualization on the FPGA, configures the DPR parameter information of the FPGA, and supports various reconstruction modes with different divided regions and resource allocation with smaller granularity.

The SPD file is of a tree structure, softpkg is a root element of the whole SPD document and comprises 7 sub-elements such as title, author, description, propertyfile, descriptor, instantiation, usesdevice and the like.

(1) title element: the name of the software component is represented.

(2) author element: representing developer information for the software component.

(3) description element: additional description information representing the software component.

(4) propertyfile element: the PRF file representing the SPD file reference.

(5) descriptor element: the SCD file representing the SPD file reference.

(6) An implementation element: representing implementation information for the software component.

(7) usesdevice element: representing the usage relationship of the software component with other devices in the system.

The implementation element is a core element of device DPR resource virtualization and provides description information for a specific implementation of a software component, and one softpkg can contain a plurality of different implementations, for example, the component supports different types of processors and operating systems. This element also allows the definition of dependency properties used in the device component or application component creation process. The id attribute of the element is used to uniquely identify a particular implementation of the software component. The instantiation element includes sub-elements such as description, propertyfile, code, compiler, programinglinggugage, humanlangugage, runtime, os, processor, dependency, and usesdevice.

in the instantiation element, a code sub-element represents the name of the component implementation code in the local path, an os sub-element represents the operating environment supported by the component deployment and operation, and a processor represents the name of the computing processing device of the component deployment. Other sub-elements describe the compiler information, programming language, runtime, etc. information required by the component.

1.2 FPGA device DPR resource virtualization

Through analysis of an operation mechanism of an SCA system, when DPR resources of FPGA equipment are virtualized, parameter information of SPD files and PRF files in a domain description file is configured. The logic device assembly has resource allocation modes of different division modes, different reconstruction region constraints and different resource configurations. On the premise of meeting SCA specifications, the integrity and the transportability of the system are ensured, the hardware resource virtualization degree of the SCA is expanded, and the support for the DPR FPGA equipment is provided. The design scheme of the domain description file of the FPGA logic device component is as follows:

step 1: the softpkg root element of the SPD file is configured to contain a plurality of instantiation sub-elements.

Each duplication element is configured with a resource description of a partition mode of the FPGA dynamic part reconfigurable area, the partition modes are different, and the number and the size of the contained dynamic part reconfigurable areas are also different.

Step 2: the PRF file referenced in the implementation element is configured.

The PRF file provides resource configuration of each dynamic partial reconfigurable sub-area in the dividing mode. One of the reconstructed sub-regions contains the following information:

(1) reconstructing the area identification;

(2) reconstructing a region coordinate position;

(3) the number of CLB Logic Cells in the reconstruction region;

(4) the number of CLB Slices of the reconstruction area;

(5) the number of Digital Clock Managers in the reconstruction region;

(6) reconstructing the number of DSP areas;

(7) the number of the reconstructed area RAMs;

and step 3: configuring the PRF file under the softpkg root element of the SPD file.

The PRF file under the softpkg root element can be used by all the component imagination under the softpkg root element. The PRF file comprises the model and the running environment of the FPGA and version information, and is used for dependency check when the waveform component is deployed.

And 4, step 4: other information is configured that ensures the logical device component operation and functional description.

Child elements such as author, descriptor, description and the like under the softpkg root element provide information such as component developers, component port connections, component function descriptions and the like.

The design scheme of the domain description file can complete the DPR resource virtualization of the logic device assembly, has the resource description with smaller granularity, comprises the device model and the operation environment required by the operation of the waveform assembly, is realized by a plurality of reconstruction region dividing modes, and provides the reconstruction support for the DPR under the SCA framework.

2. SCA-based waveform component dynamic partial reconfigurable deployment mechanism

The waveform application in the SCA domain adopts a componentized design idea, the waveform application is composed of a plurality of waveform components, and the components are realized by specific functional modules. Each component has a separate domain description file to provide information required by the operations of configuration, deployment, reconstruction, query and the like for the SCA. And the SCA analyzes the SPD file in the domain description file of each component to complete component deployment by analyzing the domain description file of the waveform application to obtain the relation of connection, configuration and the like of each component. The process of creating the waveform application in the SCA domain and deploying the components is as follows:

step 1: and calling the create operation of the application factory interface in the CF framework control interface by the client.

The create operation creates an application within the SCA domain, which provides a client interface for creating the application on the device requested by the client.

Step 2: the domain description file of the SCA parsing waveform application includes SAD file of the application and SPD file of each component, etc. to obtain configuration information of the composition of the application, port connection between each component, processor/operating environment required for component deployment, etc.

And step 3: the logic device executes allocatecapabilities operation, allocates memory and processors required by the components to run, and updates the memory and processor usage of the devices(s).

And 4, step 4: the logic device completes the loading and execution of the components through the LoadableInterface and the Executable Interface.

When the component performs DPR deployment, the applicationFactory interface obtains a registered device list in the SCA domain, and performs dependency check on the devices in the SPD file of the component and the logical devices registered in the SCA domain. The matching information such as the processor model, the running environment, the version and the like required by the check is configured through the 'initialization' element of the SPD file of the waveform component.

The invention has the beneficial effects that: the invention provides a resource virtualization and waveform deployment mechanism of a dynamic partial reconfigurable device based on an SCA (supervisory control and data acquisition), which enables a software radio system based on the SCA to have a resource virtualization mode with a reconfigurable FPGA (field programmable gate array) dynamic partial and simultaneously provides a dynamic partial reconfigurable deployment support of a waveform component by designing a domain description file under an SCA core framework. The method has stronger engineering use value in the aspects of expanding the deployment mode of the waveform assembly under the traditional SCA, improving the utilization rate of hardware resources, reducing the weight of equipment and the like.

Drawings

Figure 1 is a block diagram of a system supporting a dynamic partial reconfigurable function,

figure 2 is a schematic diagram of the dynamic partial reconfigurable function of the FPGA,

figure 3 is the SPD file core element configuration information,

fig. 4 is partial configuration information of the reconstruction region in the PRF file.

Detailed Description

The invention will be further described with reference to the accompanying drawings in which:

fig. 1 is a block diagram of a dynamic partially reconfigurable software wireless system architecture to which the present invention is directed. As shown in FIG. 1, the system is composed of three parts, namely waveform application, SCA software architecture and DPR FPGA. In the example diagram, the waveform application is composed of four components, the FPGA is divided into three dynamic partial reconfigurable areas, and a core framework in the SCA completes component management and resource allocation of the whole system. The resource virtualization technology and the waveform deployment mechanism provided by the invention are to establish a mapping relation from a waveform application component to a reconfigurable area of a FPGA dynamic part.

Fig. 2 is a schematic diagram of a dynamic partially reconfigurable function. As shown in fig. 2, the FPGA downloads the configuration file in the memory to the reconfigurable sub-regions through the ICAP reconfiguration port, the FPGA may have a plurality of partition modes, that is, the size and number of the reconfigurable sub-regions may be different according to task requirements, and each reconfigurable sub-region may also load different configuration files.

FIG. 3 is a partial core element of the SPD file of the DPR FPGA logical device component. As shown in fig. 3, the duplication element represents a partition manner of the reconstruction area, the PRF file referenced by the child element propertyfile configures information of the reconstruction area in the partition manner, and the other elements configure information of the device and the operating environment necessary for the execution of the logical device component.

Fig. 4 is partial information describing a reconstruction area in the PRF file. The two simple elements are respectively configured with the reconstruction region identification 'PR 1' and the number '2312' of CLB Logic Cells contained in the reconstruction region, and the SCA can inquire the related information.

In conclusion, the dynamic partially reconfigurable resource virtualization mode and the waveform deployment mechanism provided by the invention effectively expand the functions of the SCA, provide the functions of the dynamic partially reconfigurable through the SCA domain description file under the condition of not changing the whole software architecture, and reduce the workload of development and maintenance personnel. The miniaturization, the light weight and the integration development of equipment are promoted. There are a wide range of application scenarios for software defined satellites, software radio based communication base stations, etc.

Claims (4)

1. A method for virtualizing resources and deploying waveforms of dynamic partially reconfigurable equipment based on SCA comprises virtualizing resources of dynamic partially reconfigurable equipment and deploying dynamic partially reconfigurable waveform components based on SCA, and is characterized in that the virtualization of the dynamic partially reconfigurable resources is completed by using a domain description file of logic equipment under the standard based on SCA specification, the deployment of the dynamic partially reconfigurable components is completed by using the domain description file of the waveform components,

the resource virtualization of the dynamic partially reconfigurable equipment comprises the following specific steps:

1.1 SPD File core elements and composition

Modularizing and designing a computing device into a logic device component, carrying out software componentization on the FPGA with a reconfigurable dynamic part, abstractively packaging into a logic device component supporting a DPR FPGA,

the SPD file is of a tree structure, softpkg is a root element of the whole SPD document and comprises 7 sub-elements of title, author, description, propertyfile, descriptor, instantiation and usesdevice;

1.2 FPGA device DPR resource virtualization

The domain description file design of the FPGA logic device component is as follows:

step 1: configuring a softpkg root element of the SPD file to contain a plurality of instantiation sub-elements;

each implementation element is configured with a resource description of an FPGA dynamic partial reconfigurable region partition mode,

step 2: the PRF file referenced in the provisioning element,

the PRF file provides resource configuration of each dynamic part reconfigurable subarea in the dividing mode;

and step 3: configuring the PRF file under the softpkg root element of the SPD file,

the PRF file under the softpkg root element contains the model, the operating environment and the version information of the FPGA, and is used for dependency check when the waveform component is deployed;

and 4, step 4: configuring other information that ensures the logical device component operation and functional description,

the author, descriptor and description sub-elements under the softpkg root element provide component developers, component port connection and component function description information;

the SCA-based waveform component dynamic partial reconfigurable deployment mechanism comprises the following specific steps:

the SCA obtains the connection and configuration relation of each component by analyzing the domain description file of the waveform application,

the process of creating the waveform application in the SCA domain and deploying the components is as follows:

step 2.1: the client calls create operation of application factory interface in the CF framework control interface,

create operation creates application in SCA domain, which provides a client interface to create application on the device requested by client;

step 2.2: analyzing a domain description file of waveform application by the SCA, wherein the domain description file comprises an SAD file of the application and an SPD file of each component, and acquiring the composition of the application, port connection among the components and processor/operating environment configuration information required by component deployment;

step 2.3: the logic Device executes allocateCapability operation, allocates memory and processor required by the operation of the component, and updates the service condition of the memory and the processor of the Device;

step 2.4: the logic device completes the loading and execution of the components through the LoadableInterface and the Executable Interface.

2. An SCA based dynamic partial reconfigurable device resource virtualization and waveform deployment method as claimed in claim 1, wherein the implementation element provides description information for a specific implementation of a software component, and an id attribute of the element is used to uniquely identify a specific implementation of a software component.

3. The method as claimed in claim 1, wherein the implementation element comprises sub-elements of description, propertyfile, code, composer, programinglinggugage, humanlangugage, runtime, os, processor, dependency, and usesdevice.

4. The SCA-based dynamic partially reconfigurable device resource virtualization and waveform deployment method according to claim 1, wherein the information contained in the reconfigurable sub-regions is as follows:

(1) reconstructing the area identification;

(2) reconstructing a region coordinate position;

(3) the number of CLB Logic Cells in the reconstruction region;

(4) the number of CLB Slices of the reconstruction area;

(5) the number of Digital Clock Managers in the reconstruction region;

(6) reconstructing the number of DSP areas;

(7) the number of area RAMs reconstructed.

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