CN111260654A - Video image processing method and video processor - Google Patents
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Abstract
The embodiment of the invention discloses a video image processing method and a video processor, wherein the video image processing method comprises the following steps: intercepting an input image to obtain a plurality of first images, wherein each first image comprises an expanded intercepted area; carrying out zooming processing operation on the plurality of first images to obtain a plurality of second images respectively corresponding to the plurality of first images, wherein each second image comprises an expanded intercepting area after zooming; respectively cutting the plurality of second images to cut off the zoomed extended cutting area of each second image to obtain a plurality of images to be spliced; and splicing the images to be spliced to obtain a target image. The video image processing method provided by the embodiment of the invention solves the problems of poor local definition and fine definition of the image when the high-definition video image is processed in the prior art.
Description
Technical Field
The present invention relates to the field of image processing and display technologies, and in particular, to a video image processing method and a video processor.
Background
The video source usually needs the video processor to carry out image processing to it and then plays by display device and shows, along with the development of technique, more and more high definition video source appears for the video processor needs when carrying out image processing to carry out the video source image intercepting, zoom, the concatenation is handled the back, and output display again, however current video processor when carrying out the intercepting processing to the video image, can produce the pixel loss at the division edge of image, has influenced output picture's local definition and fineness.
Disclosure of Invention
The embodiment of the invention provides a video image processing method and a video processor, which are used for solving the problems of poor local definition and fine degree of an output picture when a high-definition video image is processed.
In one aspect, a video image processing method provided in an embodiment of the present invention includes: intercepting an input image to obtain a plurality of first images, wherein each first image comprises an expanded intercepted area; carrying out zooming processing operation on the plurality of first images to obtain a plurality of second images respectively corresponding to the plurality of first images, wherein each second image comprises an expanded intercepting area after zooming; respectively cutting the plurality of second images to cut off the zoomed extended cutting area of each second image to obtain a plurality of images to be spliced; and splicing the images to be spliced to obtain a target image.
In an embodiment of the present invention, before the step of performing the intercepting operation on the input image to obtain the plurality of first images, the method further includes: receiving the input image; acquiring attribute parameters of the input image and attribute parameters of the target image; and judging whether the interception operation is needed or not based on the attribute parameters of the input image and the attribute parameters of the target image.
In one embodiment of the present invention, in the step of determining whether or not the clipping operation is required based on the attribute parameter of the input image and the attribute parameter of the target image, the attribute parameter of the input image and the attribute parameter of the target image correspond to a pixel clock, a video memory size, and a line size of a processable image of an image processing unit within a video processing chip that performs the scaling processing operation, and the clipping operation is determined to be required when the pixel clock, the video memory size, and the line size do not satisfy specified conditions.
In an embodiment of the present invention, in the step of performing a scaling operation on the plurality of first images to obtain a plurality of second images respectively corresponding to the plurality of first images, a scaling rate of the scaled extended cropped area with respect to the extended cropped area is equal to a scaling rate of the second image with respect to the first image.
In an embodiment of the present invention, in the step of performing the clipping operation on the input image to obtain a plurality of first images, the plurality of first images have the same resolution.
In an embodiment of the present invention, in the step of performing the clipping operation on the input image to obtain a plurality of first images, the extended clipping area of each of the first images is at least one and is located at a side of the first image, and the width of each of the extended clipping areas is at least four pixels
In another aspect, an embodiment of the present invention provides a video processor, including: the video processing device comprises a first programmable logic device, a second programmable logic device and a video processing chip, wherein the video processing chip is respectively connected between the first programmable logic device and the second programmable logic device, and a microcontroller is respectively connected with the video processing chip, the first programmable logic device and the second programmable logic device; wherein the content of the first and second substances,
the first programmable logic device is used for intercepting an input image to obtain a plurality of first images, wherein each first image comprises an expanded intercepting area;
the video processing chip is used for carrying out zooming processing operation on the plurality of first images to obtain a plurality of second images respectively corresponding to the plurality of first images, wherein each second image comprises an expanded intercepting area after zooming;
the second programmable logic device is used for respectively carrying out cutting operation on the plurality of second images so as to cut out the zoomed extended cutting area of each second image and obtain a plurality of images to be spliced; and splicing the images to be spliced to obtain a target image.
In one embodiment of the invention, the first programmable logic device is further configured to: receiving the input image, acquiring the attribute parameters of the input image and the attribute parameters of the target image, and judging whether the interception operation is needed or not based on the attribute parameters of the input image and the attribute parameters of the target image.
In an embodiment of the present invention, in the step of determining whether or not the clipping operation is required to be performed based on the attribute parameter of the input image and the attribute parameter of the target image, the attribute parameter of the input image and the attribute parameter of the target image correspond to a pixel clock, a video memory size, and a line size of a processable image of an image processing unit in the video processing chip, and the clipping operation is required to be performed when the pixel clock, the video memory size, and the line size do not satisfy specified conditions.
In one embodiment of the invention, the scaling rate of the scaled extended cropped area relative to the extended cropped area is equal to the scaling rate of the second image relative to the first image.
In one embodiment of the invention, the plurality of first images have the same resolution; the extended intercepting area of each first image is at least one and is positioned at the side of the first image, and the width of each extended intercepting area is at least four pixels.
In an embodiment of the present invention, the video processing chip includes four image processing units, the input ends of four image processing channels respectively corresponding to the four image processing units are connected to the first programmable logic device, and the output ends of the four image processing channels respectively corresponding to the four image processing units are connected to the second programmable logic device.
The technical scheme has the following advantages or beneficial effects: the method comprises the steps of intercepting and dividing an input image into a plurality of images, arranging at least one extended intercepting area on the side edge for dividing each image, zooming the plurality of images, cutting off the zoomed extended intercepting areas from the plurality of images to obtain images to be spliced, and finally splicing all the images to be spliced to obtain a complete and clear target image. The video image processing method and the video processor provided by the embodiment of the invention can solve the problem that the local definition and the fineness of the picture are poor when the high-definition video image is processed in the prior art.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a flowchart illustrating a video image processing method according to a first embodiment of the present invention;
FIG. 2 is a diagram illustrating an image processing procedure in a horizontal direction according to a first embodiment of the present invention;
FIG. 3 is a diagram illustrating an image processing procedure in a vertical direction according to a first embodiment of the present invention;
FIG. 4 is a flowchart illustrating a video image processing method according to a second embodiment of the present invention;
FIG. 5 is a block diagram of a video processor according to a third embodiment of the present invention;
FIG. 6 is a diagram illustrating an image processing procedure according to another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
First embodiment
As shown in fig. 1, a video image processing method provided in a first embodiment of the present invention includes:
step S10: intercepting an input image to obtain a plurality of first images, wherein each first image comprises an expanded intercepted area;
step S20: carrying out zooming processing operation on the plurality of first images to obtain a plurality of second images respectively corresponding to the plurality of first images, wherein each second image comprises an expanded intercepting area after zooming;
step S30: respectively cutting the plurality of second images to cut off the zoomed extended cutting area of each second image to obtain a plurality of images to be spliced; and
step S40: and splicing the images to be spliced to obtain a target image.
In order to understand the present embodiment more clearly, the foregoing steps S10-S40 are described in detail below with specific examples.
In step S10, a clipping operation is performed on the input video source image to divide it into a plurality of first images. As shown in fig. 2 and 3, in the row direction (horizontal direction) or the column direction (vertical direction) of the cutout image B, a plurality of first images each including one sub-image C and a plurality of extended cutout areas a may be divided. Here, fig. 2 and 3 only illustrate the case where the cutout image B is divided into two first images, and thus each of the first images includes one sub-image C and one extended cutout area a; if the cutout image B is divided into two or more first images, the first images located at both ends in the row direction or the column direction include one sub-image C and one extended cutout area a, and the first image located in the middle includes one sub-image C and two extended cutout areas a.
In view of the above, in order to solve the problem of pixel loss at the segmentation edge of the image during the scaling process, the video image processing method provided in this embodiment collects a certain size/number of pixels at the segmentation edge as an extended capture area based on the requirement of an image scaling algorithm (for example, 6 symbol's interpolation algorithm, and generation of a new pixel needs related data of 6 surrounding pixels during the scaling process). Specifically, for example, as shown in fig. 2, after the capture screen B is divided into two first images, each first image includes one sub-image C and an extended capture area a, there are two adjacent extended capture areas a between the two sub-images C, and taking the extended capture area a on the left as an example, the extended capture area a is generated by capturing a certain number of pixels from the first image on the left toward the first image on the right during the division; similarly, the right extended clipping area a is also generated by clipping a certain number of pixels from the right first image to the left first image during the division.
In step S20, after the division into the plurality of first images, the scaling process is performed on the first images, and the plurality of second images and the post-scaling extended cropped area D included in the second images are obtained. As shown in fig. 2 and 3, each second image includes a sub-image E and a scaled extended clipping region D. And each sub-image C is zoomed to obtain a sub-image E, and each expanded intercepting area A is converted into a zoomed expanded intercepting area D. Here, the scaling rate from the sub-image C to the sub-image E is the same as the scaling rate from the extended clipping region a to the scaled extended clipping region D to ensure that the image is not distorted.
In step S30, after the scaling process is performed, the scaled extended cropped area D needs to be cropped from the second image to obtain a plurality of images to be stitched (sub-images E).
In step S40, all the images to be stitched (sub-images E) are finally stitched to obtain the target image F.
As can be seen from the above, the video image processing method provided in this embodiment, based on the requirement of the image scaling algorithm, divides an input image into a plurality of images, and has at least one extended intercepting region on a side where each image is divided, then performs scaling processing on the plurality of images, cuts out the extended intercepting regions after scaling from the plurality of images after scaling processing to obtain a plurality of images to be stitched, and finally stitches all the images to be stitched to obtain a complete and clear target image. The video image processing method provided by the embodiment can solve the problem that the local definition and the fineness of the picture are poor when the high-definition video image is processed in the prior art.
Second embodiment
As shown in fig. 4, on the basis of the foregoing embodiment, the video image processing method according to the second embodiment of the present invention further includes, before the foregoing step S10:
step S01: receiving an input image;
step S02: acquiring attribute parameters of the input image and attribute parameters of a target image;
step S03: and judging whether the interception operation is needed or not based on the attribute parameters of the input image and the attribute parameters of the target image.
Specifically, according to the processing capability of the video processing chip, the video image processing method provided in this embodiment needs to first obtain the attribute parameters of the input image and the target image to determine what processing manner is needed, where the attribute parameters correspond to the hardware specification of the video processing chip, such as the pixel clock of the image processing unit, the video memory size, and the line size of the image that can be processed. For example, an image processing unit in a video processing chip of a video processor can perform direct image processing on a 1080P (resolution is 1920 × 1080@60HZ) video, and when an input image and/or a target image exceeds 1080P resolution (i.e. exceeds the line size of an image which can be processed by the image processing unit), for example, the input image and/or the target image is 4k × 2k (resolution is 3840 × 2160@60HZ or 4096 × 2160@60HZ) specification, the input image needs to be divided into a plurality of first images to be respectively subjected to image (scaling) processing, and then the first images are spliced to output a complete image; and when the input image and/or the target image are smaller than or equal to the specification of 1080P, the input image is not required to be divided, and the video processing chip directly outputs the input image after the scaling processing. In other words, when the pixel clock, the video memory size and the line size of the image processing unit in the video processing chip do not meet the specified conditions, it is determined that the clipping operation is required, otherwise, the clipping operation is not required.
Further, in step S10, in order to prevent the target image obtained by subjecting the input image to the processes of clipping, scaling, and stitching from being distorted, it is necessary that the scaling rate R1 of the post-scaling extended clipped region D with respect to the extended clipped region a be equal to the scaling rate R2 of the second image (D + E) with respect to the first image (a + C). As shown in fig. 2 and fig. 3, the above content can be expressed by the following formula:
r1 ═ Dsize/size, R2 ═ Dsize + Esize)/(size + Csize), and R1 ═ R2, where Asize is the size of the extended cropped area a, Csize is the size of the sub-image C, Dsize is the size of the scaled extended cropped area D, and Esize is the size of the sub-image E.
As described above, the first images obtained in step S10 all have the same resolution. Specifically, in order to make the divided pixel size of the image complete, for example, as shown in fig. 2 and 3, after the input image B is cut and divided into two first images, the sum of the sizes of the two corresponding sub-images C is equal to the size of one cut image B, if Bsize cannot be evenly divided by 2, Csize has a problem that decimal affects that one pixel in the actual image division is difficult to allocate, so that Bsize can be subtracted by one pixel to be evenly divided by 2, thereby enabling the input image B to divide two sub-images C of the same size. Of course, if the input image B is to be truncated into three first images, if Bsize cannot be divided exactly by 3, then Bsize can be divided exactly by 3 after subtracting a certain number of pixels so that the truncated image B can be divided equally into three equally sized sub-images C, and so on. Similarly, the size of the two sub-images C after the scaling process is changed from Csize to Esize, and if the stitched image size Fsize cannot be divided by 2, the size Fsize can be divided by 2 by adding one pixel when calculating Esize, so that the pixel size of Esize does not have a decimal condition. Through the operation, the zoomed expanded intercepting area D can be accurately cut off in the splicing process of the plurality of second images, and the complete display target image F can be accurately spliced.
Furthermore, in order to enable the plurality of first images after being captured to obtain more pixel point references at the captured edge, 3 pixel points need to be referred to at one side of the edge pixel point according to a scaling processing algorithm, such as a 6symbol interpolation algorithm, however, at least 4 pixel points need to be referred to in order to give consideration to interlaced and progressive division and splicing of the display picture. In other words, when dividing the extended clipping area a, it is necessary to clip the sub-image C connected to the edge thereof to another sub-image C adjacent thereto by a width of at least 4 pixels. Note that the width is a length in the left-right direction when divided in the horizontal direction shown in fig. 2, and a length in the up-down direction when divided in the vertical direction shown in fig. 3.
Finally, as shown in fig. 6, in other embodiments of the present invention, the input image B may be cut into a plurality of first images in the horizontal and vertical directions simultaneously, and the first images include the sub-image C and 2, 3, or 4 extended cut areas a located at the side of the first pixel, and after the above processing, the first images are spliced into the complete target image F.
Third embodiment
As shown in fig. 5, a video processor 300 provided in a third embodiment of the present invention includes: the video processing system comprises a first programmable logic device 310, a second programmable logic device 330, a video processing chip 320 and a microcontroller 340, wherein the video processing chip 320 is respectively connected with the first programmable logic device 310 and the second programmable logic device 330, and the microcontroller 340 is respectively connected with the video processing chip 320, the first programmable logic device 310 and the second programmable logic device 330. The microcontroller 340 is, for example, an ARM-based embedded processor, and the programmable logic device is, for example, an FPGA (field programmable Gate Array).
Specifically, the first programmable logic device 310 is configured to intercept a plurality of first images from an input video source signal. As shown in fig. 2 and 3, in the row direction (horizontal direction) or the column direction (vertical direction) of the cutout image B, a plurality of first images each including the sub-image C and the extended cutout area a may be divided. Here, fig. 2 and 3 only illustrate the case where the cutout image B is divided into two first images, and thus each of the first images includes one sub-image C and one extended cutout area a; if the cutout image B is divided into two or more first images, the first images located at both ends in the row direction or the column direction include one sub-image C and one extended cutout area a, and the first image located in the middle includes one sub-image C and two extended cutout areas a. In addition, in order to enable the plurality of first images after being captured to obtain more pixel point references at the captured edge, 3 pixel points need to be referred to at one side of the edge pixel point according to a scaling processing algorithm, such as a 6symbol interpolation algorithm, however, at least 4 pixel points need to be referred to in order to give consideration to interlaced and progressive division and splicing of the display picture. In other words, when dividing the extended clipping area a, it is necessary to clip the sub-image C connected to the edge of the extended clipping area a to another sub-image C adjacent to the edge of the extended clipping area a by at least 4 pixel points. Note that the width is a length in the left-right direction when divided in the horizontal direction shown in fig. 2, and a length in the up-down direction when divided in the vertical direction shown in fig. 3.
The video processing chip 320 is configured to, after being divided into a plurality of first images, perform scaling processing on the first images to obtain a plurality of second images and a scaled extended capture area D in the second images. As shown in fig. 2 and 3, each second image includes a sub-image E and a scaled extended clipping region D. And each sub-image C is zoomed to obtain a sub-image E, and each expanded intercepting area A is converted into a zoomed expanded intercepting area D. Here, the scaling rate from the sub-image C to the sub-image E is the same as the scaling rate from the extended clipping region a to the scaled extended clipping region D to ensure that the image is not distorted.
Furthermore, in order to prevent the target image obtained by the input image after being subjected to the processes of clipping, scaling and stitching, the video processing chip 320 needs the scaling rate R1 of the scaled extended clipping region D relative to the extended clipping region a to be equal to the scaling rate R2 of the second image (D + E) relative to the first image (a + C). As shown in fig. 2 and fig. 3, the above content can be expressed by the following formula:
r1 ═ Dsize/size, R2 ═ Dsize + Esize)/(size + Csize), and R1 ═ R2, where Asize is the size of the extended cropped area a, Csize is the size of the sub-image C, Dsize is the size of the scaled extended cropped area D, and Esize is the size of the sub-image E.
In view of the above, in order to make the divided pixel size of the image complete, it is necessary that the first image intercepted by the first programmable logic device 310 has the same resolution, and the specific processing manner may refer to the foregoing embodiments, which is not described herein.
The second programmable logic device 330 is configured to respectively perform a cropping operation on the plurality of second images to crop out the zoomed extended cropping area of each of the second images, so as to obtain a plurality of images to be stitched; and splicing the images to be spliced to obtain a target image.
In addition, the video processor 300 provided in this embodiment, depending on the processing capability of the video processing chip 320, for example, includes four image processing units 321, and each image processing unit 321 has, for example, the capability of individually processing a 1080P (resolution is 1920 × 1080@60HZ) video source image. Each image processing unit corresponds to one image processing channel, as shown in fig. 5, the image processing channels are CH0, CH1, CH2 and CH3, respectively, an input end of each image processing channel is connected to the first programmable logic device 310, and an output end thereof is connected to the second programmable logic device 320. After analyzing the attribute parameters of the input image, the processing method is determined according to the processing capability of the image processing unit 321, and the attribute parameters correspond to the hardware specifications of the video processing chip 320, such as the pixel clock, the video memory size, and the line size of the image that can be processed by the image processing unit 321321. For example, the image processing unit 321 of the video processing chip 320 of the video processor 300 can satisfy the direct image processing of 1080P (resolution is 1920 × 1080@60HZ) video, when the input image and/or the target image exceeds 1080P resolution, for example, the input image and/or the target image is 4k2k (resolution is 3840 × 2160@60HZ or 4096 × 2160@60HZ) specification, the input image needs to be divided into a plurality of first images, and the first images are transmitted to the corresponding image processing units 321 through a plurality of image processing channels for scaling processing, and then the whole target image is spliced and output; on the contrary, when the input image and/or the target image is smaller than or equal to the 1080P standard, the video processing chip 320 directly scales and outputs the input image and/or the target image without intercepting and splicing.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and/or method may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (12)
1. A video image processing method, comprising:
intercepting an input image to obtain a plurality of first images, wherein each first image comprises an expanded intercepted area;
carrying out zooming processing operation on the plurality of first images to obtain a plurality of second images respectively corresponding to the plurality of first images, wherein each second image comprises an expanded intercepting area after zooming;
respectively cutting the plurality of second images to cut off the zoomed extended cutting area of each second image to obtain a plurality of images to be spliced;
and splicing the images to be spliced to obtain a target image.
2. The video image processing method of claim 1, wherein the step of performing the clipping operation on the input image to obtain the plurality of first images further comprises:
receiving the input image;
acquiring attribute parameters of the input image and attribute parameters of the target image;
and judging whether the interception operation is needed or not based on the attribute parameters of the input image and the attribute parameters of the target image.
3. The method according to claim 2, wherein in the step of determining whether or not the clipping operation is necessary based on the attribute parameter of the input image and the attribute parameter of the target image, the attribute parameter of the input image and the attribute parameter of the target image correspond to a pixel clock, a video memory size, and a line size of a processable image of an image processing unit within a video processing chip that performs the scaling processing operation, and the clipping operation is necessary when the pixel clock, the video memory size, and the line size do not satisfy specified conditions.
4. The method according to claim 1, wherein in the step of performing the scaling operation on the plurality of first images to obtain a plurality of second images respectively corresponding to the plurality of first images, a scaling rate of the scaled extended cropped area with respect to the extended cropped area is equal to a scaling rate of the second image with respect to the first image.
5. The method according to claim 4, wherein in the step of performing the clipping operation on the input image to obtain the plurality of first images, the plurality of first images have the same resolution.
6. The method according to claim 1, wherein in the step of performing the clipping operation on the input image to obtain a plurality of first images, the extended clipping area of each of the first images is at least one and is located at a side of the first image, and each of the extended clipping areas has a width of at least four pixels.
7. A video processor, comprising:
a first programmable logic device;
a second programmable logic device;
the video processing chip is respectively connected between the first programmable logic device and the second programmable logic device;
the microcontroller is respectively connected with the video processing chip, the first programmable logic device and the second programmable logic device; wherein the content of the first and second substances,
the first programmable logic device is used for intercepting an input image to obtain a plurality of first images, wherein each first image comprises an expanded intercepting area;
the video processing chip is used for carrying out zooming processing operation on the plurality of first images to obtain a plurality of second images respectively corresponding to the plurality of first images, wherein each second image comprises an expanded intercepting area after zooming;
the second programmable logic device is used for respectively carrying out cutting operation on the plurality of second images so as to cut out the zoomed extended cutting area of each second image and obtain a plurality of images to be spliced; and splicing the images to be spliced to obtain a target image.
8. The video processor of claim 7, wherein the first programmable logic device is further configured to: receiving the input image, acquiring the attribute parameters of the input image and the attribute parameters of the target image, and judging whether the interception operation is needed or not based on the attribute parameters of the input image and the attribute parameters of the target image.
9. The video processor according to claim 8, wherein in the step of determining whether or not a clipping operation is required based on the attribute parameter of the input image and the attribute parameter of the target image, the attribute parameter of the input image and the attribute parameter of the target image correspond to a pixel clock, a video memory size, and a line size of a processable image of an image processing unit within the video processing chip, and the clipping operation is determined to be required when the pixel clock, the video memory size, and the line size do not satisfy specified conditions. .
10. The video processor of claim 8, wherein a scaling rate of the scaled extended cropped area relative to the extended cropped area is equal to a scaling rate of the second image relative to the first image.
11. The video processor of claim 7, wherein the plurality of first images have the same resolution; the extended intercepting area of each first image is at least one and is positioned at the side of the first image, and the width of each extended intercepting area is at least four pixels.
12. The video processor according to claim 7, wherein the video processing chip comprises four image processing units, the input terminals of four image processing channels corresponding to the four image processing units are respectively connected to the first programmable logic device, and the output terminals of the four image processing channels corresponding to the four image processing units are respectively connected to the second programmable logic device.
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