CN111258833A - High-speed bus stability detection method, system and related components - Google Patents
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Abstract
The application discloses a method for detecting stability of a high-speed bus, which comprises the following steps: controlling the high-speed link to be switched between a linkdown state and a linkup state in a circulating and alternating mode; when the high-speed link is in a link up state, acquiring a system log; judging whether the high-speed link has a fault according to the system log; if yes, stopping switching the state of the high-speed link, and executing fault indication operation. According to the method and the device, in the product development stage, the problem can be found and corrected in advance by testing the stability of the high-speed link in the switching process, the problem that data are lost due to abnormity in the using process of a client is avoided, the stability and the reliability of the server are improved, and the competitiveness of the product is improved. The application also discloses a high-speed bus stability detection system, electronic equipment and a computer readable storage medium, which have the beneficial effects.
Description
Technical Field
The present application relates to the field of servers, and in particular, to a method, a system, and a related component for detecting stability of a high-speed bus.
Background
With the advent of big data, cloud computing and artificial intelligence era, the internet business volume is dramatically increased, and the computing volume and the computing frequency are increased. The data volume is increased in an avalanche mode, massive data needs to be stored, the storage subsystem is particularly important as a main link for data storage, a cloud disk with huge capacity is needed, and high requirements are provided for the stability of the link of the storage subsystem.
The storage link usually includes several parts, such as an operating system, a driver, a CPU (Central Processing Unit), a storage device, and the like, where a PCIE (Peripheral component interconnect Express) high-speed link is often selected as the current storage link, and the PCIE high-speed link brings higher speed and higher performance, and also brings high risk, and in the operation process of the server, if the PCIE high-speed link is unstable, a data transceiving error may be caused, the storage and computation performance may be slightly affected, and a link failure may be seriously caused, which leads to a disk crash, which causes a client service interruption and a data loss, so the stability detection of the PCIE high-speed bus is very important, but at present, there is no scheme for performing stability detection on the PCIE high-speed bus in advance.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The application aims to provide a method, a system, electronic equipment and a computer readable storage medium for detecting the stability of a high-speed bus, and the method, the system, the electronic equipment and the computer readable storage medium can find and correct problems in advance by testing the stability of a high-speed link in a switching process in a product development stage, avoid data loss caused by abnormity in the using process of a client, improve the stability and the reliability of a server and improve the competitiveness of a product.
In order to solve the above technical problem, the present application provides a method for detecting stability of a high-speed bus, including:
controlling the high-speed link to be switched between a linkdown state and a linkup state in a circulating and alternating mode;
when the high-speed link is in the link up state, acquiring a system log;
judging whether the high-speed link has a fault according to the system log;
and if so, stopping switching the state of the high-speed link and executing fault indication operation.
Preferably, the process of controlling the high-speed link to switch cyclically and alternately between the linkdown state and the linkup state specifically comprises:
the method comprises the steps that a state register of a high-speed link is modified to control the high-speed link to be switched between a linkdown state and a linkup state in a circulating and alternating mode;
correspondingly, the process of stopping switching the state of the high-speed link specifically includes:
ceasing to modify the status register of the high speed link.
Preferably, the process of controlling the high-speed link to switch cyclically and alternately between the linkdown state and the linkup state specifically comprises:
and controlling the high-speed link to be circularly and alternately switched between a linkdown state and a linkup state in a first preset time period.
Preferably, the process of controlling the high-speed link to be cyclically and alternately switched between the link down state and the link up state by modifying the state register of the high-speed link specifically comprises:
adjusting a state register of the high-speed link to be in a linkdown state at the starting time of the first preset time period;
waiting for a second preset time period, and adjusting the state register of the high-speed link to be in a link up state; and waiting for the second preset time period, adjusting the state register of the high-speed link to be in the linkdown state, and repeating the step until the end time of the first preset time period is reached.
Preferably, the process of determining whether the high-speed link has a fault according to the system log specifically includes:
traversing the system log according to a preset fault keyword, if the system log has information matched with the preset fault keyword, judging that the high-speed link has a fault, and if not, judging that the high-speed link has no fault.
Preferably, the process of controlling the high-speed link to be cyclically and alternately switched between the link down state and the link up state by modifying the state register of the high-speed link specifically comprises:
adjusting a state register of a high-speed link through a script to control the high-speed link to be switched between a linkdown state and a linkup state in a circulating and alternating mode;
correspondingly, the process of acquiring the system log specifically comprises the following steps:
acquiring a system log through the script;
correspondingly, the process of judging whether the high-speed link has a fault according to the system log specifically comprises the following steps:
and judging whether the high-speed link has a fault or not according to the system log through the script.
Preferably, the process of executing the fault indication operation specifically includes:
when the high-speed link has a fault, generating a low-level signal through the BMC;
and receiving the low-level signal through the CPLD and outputting a pulse signal with a preset frequency to drive the LED lamp to execute fault indication operation.
In order to solve the above technical problem, the present application further provides a high speed bus stability detection system, including:
the adjusting module is used for controlling the high-speed link to be switched between a linkdown state and a linkup state in a circulating and alternating mode;
the acquisition module is used for acquiring a system log when the high-speed link is in the link up state;
the judging module is used for judging whether the high-speed link has a fault according to the system log;
and the error reporting module is used for controlling the adjusting module to stop switching the state of the high-speed link and executing fault indicating operation.
In order to solve the above technical problem, the present application further provides an electronic device, including:
a memory for storing a computer program;
a processor for implementing the steps of the high speed bus stability detection method as described in any one of the above when executing the computer program.
To solve the above technical problem, the present application further provides a computer-readable storage medium, having a computer program stored thereon, where the computer program is executed by a processor to implement the steps of the high-speed bus stability detection method according to any one of the above items.
The application provides a high-speed bus stability detection method, which is characterized in that in a product development stage, a high-speed link is controlled to be switched between a linkdown state and a linkup state in a circulating and alternating mode, and the state machine of the high-speed link can be repeatedly executed again in the switching process, so that the highest pressure is applied to the high-speed bus, and the stability of the high-speed link in the switching process can be tested. Considering that when a PCIE high-speed signal is unstable, a PCIE error report or even a downtime occurs in a switching process, and related error information may be acquired through a system log, and when a fault is detected in a high-speed link, the operation of adjusting the state of the high-speed link is stopped to improve test safety, and a fault indication operation is performed, so that a tester can find and correct the problem in advance, thereby avoiding that an abnormality occurs in a customer using process to cause data loss, improving stability and reliability of a server, and improving competitiveness of a product. The application also provides a high-speed bus stability detection system, electronic equipment and a computer readable storage medium, which have the same beneficial effects as the high-speed bus stability detection method.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
FIG. 1 is a flowchart illustrating steps of a method for detecting stability of a high-speed bus according to the present invention;
fig. 2 is a schematic structural diagram of a fault indication device provided in the present application;
fig. 3 is a schematic structural diagram of a high-speed bus stability detection system provided in the present application.
Detailed Description
The core of the application is to provide a method, a system, an electronic device and a computer readable storage medium for detecting the stability of a high-speed bus, and the method, the system, the electronic device and the computer readable storage medium can find and correct problems in advance by testing the stability of a high-speed link in a switching process in a product development stage, avoid data loss caused by abnormity in the using process of a client, improve the stability and the reliability of a server and improve the competitiveness of a product.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart illustrating steps of a method for detecting stability of a high-speed bus according to the present disclosure, the method comprising:
s101: controlling the high-speed link to be switched between a linkdown state and a linkup state in a circulating and alternating mode;
specifically, the present storage link selects a high-speed PCIE link for multiple purposes, and this embodiment takes the PCIE link as an example to describe the method for detecting the stability of the high-speed bus, and certainly, the high-speed link may also select another high-speed bus link, which is not specifically limited herein.
The method for detecting the stability of the high-speed bus is particularly suitable for the product development stage, so that problems can be found and corrected in time, and the data loss caused by abnormity in the using process of a user is avoided. Considering that when a PCIE link is switched between a linkdown state (i.e., a link interrupted state) and a linkup state (i.e., a link connected state), the switching process may bring the maximum pressure to the PCIE link, and if a PCIE high-speed signal is unstable, a PCIE error report may occur in the switching process between the linkdown state and the linkup state, so that the purpose of this step is to provide a high-pressure environment for the PCIE high-speed signal, so as to test the stability of the high-speed bus.
As a preferred embodiment, the state register of the high-speed link may be modified to control the high-speed link to be cyclically and alternately switched between the link down state and the link up state, and the state switching process may cause the state machine of the PCIE link to be repeatedly executed again, so as to bring high pressure to the PCIE link. Further, to ensure the system stability, a preset test time is required, that is, the high-speed link is controlled to be cyclically and alternately switched between the link down state and the link up state within a first preset time period, and if the first preset time period is exceeded, the state switching operation on the PCIE link is not performed any more, wherein the first preset time period may be set to 48 hours. When the test is started, firstly, the state register of the high-speed link is adjusted to be in a linkdown state, a second preset time period is waited, the state register is adjusted to be in a linkup state, if the server system is normal, the second preset time period is continuously waited, the state register is adjusted to be in the linkdown state, and by analogy, the two states are circularly and alternately switched until the end time of the first preset time period is reached, the state switching of the PCIE link is not performed, wherein the second preset time period can be set to be 20S, certainly, the second preset time period needs to be set according to actual engineering requirements, and as long as the condition that the execution of S102-S103 is not influenced is met.
S102: when the high-speed link is in a link up state, acquiring a system log;
specifically, as described above, in the switching process from the link down state to the link up state, the high-speed link may bring a huge pressure to the PCIE link, and if the PCIE high-speed signal is unstable, information such as PCIE error reporting, even downtime, and PCIE error reporting may be embodied in the system log in the switching process, so that each time the high-speed link enters the link up state, a system log is obtained, so as to determine whether a failure exists in the previous switching process according to the system log in the subsequent process, thereby determining whether the PCIE high-speed signal can be stably transmitted in the high-pressure environment.
S103: judging whether the high-speed link has a fault according to the system log, if so, executing a step S104, and if not, executing a step S101;
s104: the state of the switching high-speed link is stopped, and a failure indication operation is performed.
In this embodiment, the step S103 is executed to determine whether a high-speed link has a fault according to a system log, before the step S103 is executed, the embodiment may further include an operation of presetting a fault keyword, where the preset fault keyword corresponds to PCIE error information and downtime information, and the efficiency of subsequently searching for fault information in the system log may be improved by matching the preset fault keyword. Specifically, after the system log is acquired, the system log is traversed, whether the system log has information corresponding to a preset fault keyword is judged, if yes, it is indicated that a PCIE error occurs, at this time, the operation of performing the state switching of the high-speed link is stopped, that is, the state register of the PCIE link is not modified, so that the PCIE link is kept in the current state; and if not, executing the operation of adjusting the state register to be in the linkdown state after the waiting time reaches a second preset time period. Further, fault indication operation can be executed to remind the staff to take relevant treatment measures.
As a preferred embodiment, in order to improve the response speed, the fault indication may be performed by means of hardware indication, and specifically, the fault indication operation may be performed by a fault indication device. Referring to fig. 2, fig. 2 is a schematic structural diagram of a fault indication device provided in the present application, where the fault indication device may include a BMC 01, a CPLD 02, a switch tube Q, LED, a lamp D and a resistor R, where the BMC 01 may identify whether information corresponding to a fault keyword exists in a system log, if so, the BMC 01 outputs a low level signal to the CPLD 02, and when the CPLD 02 receives the low level signal, outputs a pulse signal with a preset frequency, and controls the LED lamp D to flash through turning on or off of a transistor, so as to prompt a worker.
As a preferred embodiment, in order to further improve the automation level of the test and improve the test efficiency, the operation of controlling the high-speed link to be cyclically and alternately switched between the link down state and the link up state, the operation of acquiring the system log when the high-speed link is in the link up state, and the operation of judging whether the high-speed link has a fault according to the system log may be implemented by using a script, if so, the operation of switching the state of the high-speed link may be stopped, and when the test is performed, the corresponding script may be directly run.
It can be seen that, in the product development phase, the present embodiment controls the high-speed link to be cyclically and alternately switched between the linkdown state and the linkup state, and the switching process causes the state machine of the high-speed link to be repeatedly executed again, so that the highest pressure is applied to the high-speed bus, so as to test the stability of the high-speed link in the switching process. Considering that when a PCIE high-speed signal is unstable, a PCIE error report or even a downtime occurs in a switching process, and related error information may be acquired through a system log, and when a fault is detected in a high-speed link, the operation of adjusting the state of the high-speed link is stopped to improve test safety, and a fault indication operation is performed, so that a tester can find and correct the problem in advance, thereby avoiding that an abnormality occurs in a customer using process to cause data loss, improving stability and reliability of a server, and improving competitiveness of a product.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a high-speed bus stability detection system provided in the present application, including:
the adjusting module 11 is used for controlling the high-speed link to be switched between a linkdown state and a linkup state in a circulating and alternating mode;
the acquisition module 12 is configured to acquire a system log when the high-speed link is in a link up state;
the judging module 13 is used for judging whether the high-speed link has a fault according to the system log;
and an error reporting module 14, configured to control the adjusting module 11 to stop switching the state of the high-speed link, and perform a fault indication operation.
As a preferred embodiment, the adjusting module 11 is specifically configured to:
the state register of the high-speed link is modified to control the high-speed link to be circularly and alternately switched between a linkdown state and a linkup state;
correspondingly, the process of stopping switching the state of the high-speed link specifically includes:
the modification of the status register of the high speed link is stopped.
As a preferred embodiment, the adjusting module 11 is specifically configured to:
and controlling the high-speed link to be circularly and alternately switched between a linkdown state and a linkup state in a first preset time period.
As a preferred embodiment, the process of controlling the high-speed link to cyclically and alternately switch between the link down state and the link up state by modifying the state register of the high-speed link specifically includes:
adjusting a state register of the high-speed link to be in a linkdown state at the starting time of a first preset time period;
waiting for a second preset time period, and adjusting the state register of the high-speed link to be in a link up state; and waiting for a second preset time period, adjusting the state register of the high-speed link to be in a linkdown state, and repeating the step until the end time of the first preset time period is reached.
As a preferred embodiment, the determining module 13 specifically includes:
the traversal unit is used for traversing the system log according to the preset fault keyword;
and the judging unit is used for judging that the high-speed link has a fault if the system log has information matched with the preset fault keyword, and otherwise, judging that the high-speed link does not have the fault.
As a preferred embodiment, the process of controlling the high-speed link to cyclically and alternately switch between the link down state and the link up state by modifying the state register of the high-speed link specifically includes:
adjusting a state register of the high-speed link through a script to control the high-speed link to be switched between a linkdown state and a linkup state in a circulating and alternating mode;
correspondingly, the process of acquiring the system log specifically comprises the following steps:
obtaining a system log through a script;
correspondingly, the process of judging whether the high-speed link has a fault according to the system log specifically comprises the following steps:
and judging whether the high-speed link has a fault or not according to the system log through the script.
As a preferred embodiment, the process of executing the fault indication operation specifically includes:
when the high-speed link has a fault, generating a low-level signal through the BMC;
and receiving the low-level signal through the CPLD and outputting a pulse signal with a preset frequency to drive the LED lamp to execute fault indication operation.
In another aspect, the present application further provides an electronic device, including:
a memory for storing a computer program;
a processor for implementing the high speed bus stability detection method as described in any one of the above embodiments when executing a computer program.
The electronic equipment provided by the application has the same beneficial effects as the high-speed bus stability detection method.
For an introduction of an electronic device provided in the present application, please refer to the above embodiments, which are not described herein again.
In another aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the high-speed bus stability detection method as described in any one of the above embodiments.
The computer-readable storage medium provided by the application has the same beneficial effects as the high-speed bus stability detection method.
For the introduction of a computer-readable storage medium provided in the present application, please refer to the above embodiments, which are not described herein again.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for detecting stability of a high-speed bus is characterized by comprising the following steps:
controlling the high-speed link to be switched between a linkdown state and a linkup state in a circulating and alternating mode;
when the high-speed link is in the link up state, acquiring a system log;
judging whether the high-speed link has a fault according to the system log;
and if so, stopping switching the state of the high-speed link and executing fault indication operation.
2. The method for detecting the stability of the high-speed bus according to claim 1, wherein the step of controlling the high-speed link to cyclically and alternately switch between the linkdown state and the linkup state specifically comprises:
the method comprises the steps that a state register of a high-speed link is modified to control the high-speed link to be switched between a linkdown state and a linkup state in a circulating and alternating mode;
correspondingly, the process of stopping switching the state of the high-speed link specifically includes:
ceasing to modify the status register of the high speed link.
3. The method for detecting the stability of the high-speed bus according to claim 2, wherein the step of controlling the high-speed link to cyclically and alternately switch between the linkdown state and the linkup state specifically comprises:
and controlling the high-speed link to be circularly and alternately switched between a linkdown state and a linkup state in a first preset time period.
4. The method for detecting the stability of the high-speed bus according to claim 3, wherein the step of controlling the high-speed link to cyclically and alternately switch between the link down state and the link up state by modifying the state register of the high-speed link specifically comprises:
adjusting a state register of the high-speed link to be in a linkdown state at the starting time of the first preset time period;
waiting for a second preset time period, and adjusting the state register of the high-speed link to be in a link up state; and waiting for the second preset time period, adjusting the state register of the high-speed link to be in the linkdown state, and repeating the step until the end time of the first preset time period is reached.
5. The method for detecting the stability of the high-speed bus according to claim 1, wherein the step of determining whether the high-speed link has a fault according to the system log specifically comprises:
traversing the system log according to a preset fault keyword, if the system log has information matched with the preset fault keyword, judging that the high-speed link has a fault, and if not, judging that the high-speed link has no fault.
6. The method for detecting the stability of the high-speed bus according to claim 2, wherein the step of controlling the high-speed link to cyclically and alternately switch between the link down state and the link up state by modifying the state register of the high-speed link specifically comprises:
adjusting a state register of a high-speed link through a script to control the high-speed link to be switched between a linkdown state and a linkup state in a circulating and alternating mode;
correspondingly, the process of acquiring the system log specifically comprises the following steps:
acquiring a system log through the script;
correspondingly, the process of judging whether the high-speed link has a fault according to the system log specifically comprises the following steps:
and judging whether the high-speed link has a fault or not according to the system log through the script.
7. The method for detecting stability of a high-speed bus according to any one of claims 1 to 6, wherein the process of performing the fault indication operation is specifically:
when the high-speed link has a fault, generating a low-level signal through the BMC;
and receiving the low-level signal through the CPLD and outputting a pulse signal with a preset frequency to drive the LED lamp to execute fault indication operation.
8. A high speed bus stability detection system, comprising:
the adjusting module is used for controlling the high-speed link to be switched between a linkdown state and a linkup state in a circulating and alternating mode;
the acquisition module is used for acquiring a system log when the high-speed link is in the link up state;
the judging module is used for judging whether the high-speed link has a fault according to the system log;
and the error reporting module is used for controlling the adjusting module to stop switching the state of the high-speed link and executing fault indicating operation.
9. An electronic device, comprising:
a memory for storing a computer program;
processor for implementing the steps of the high speed bus stability detection method according to any of claims 1 to 7 when executing said computer program.
10. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the high speed bus stability detection method according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010093649.8A CN111258833A (en) | 2020-02-14 | 2020-02-14 | High-speed bus stability detection method, system and related components |
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| CN202010093649.8A CN111258833A (en) | 2020-02-14 | 2020-02-14 | High-speed bus stability detection method, system and related components |
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| CN111258833A true CN111258833A (en) | 2020-06-09 |
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| CN202010093649.8A Withdrawn CN111258833A (en) | 2020-02-14 | 2020-02-14 | High-speed bus stability detection method, system and related components |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112416672A (en) * | 2020-11-12 | 2021-02-26 | 宁畅信息产业(北京)有限公司 | PCIE link stability test method, device, computer equipment and medium |
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2020
- 2020-02-14 CN CN202010093649.8A patent/CN111258833A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112416672A (en) * | 2020-11-12 | 2021-02-26 | 宁畅信息产业(北京)有限公司 | PCIE link stability test method, device, computer equipment and medium |
| CN112416672B (en) * | 2020-11-12 | 2024-02-23 | 宁畅信息产业(北京)有限公司 | PCIE link stability testing method, PCIE link stability testing device, computer equipment and medium |
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