CN111257796A - Integrated circuit leakage current test circuit and device - Google Patents
Integrated circuit leakage current test circuit and device Download PDFInfo
- Publication number
- CN111257796A CN111257796A CN202010249281.XA CN202010249281A CN111257796A CN 111257796 A CN111257796 A CN 111257796A CN 202010249281 A CN202010249281 A CN 202010249281A CN 111257796 A CN111257796 A CN 111257796A
- Authority
- CN
- China
- Prior art keywords
- circuit
- signal
- test
- leakage current
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
Landscapes
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present disclosure relates to the field of microelectronic control technologies, and in particular, to a leakage current testing circuit and device for an integrated circuit. The problems that signals at two ends of a sampling resistor cannot be isolated from a test circuit in the integrated circuit pin leakage current test, so that the error of a leakage current test result is large and the reliability is reduced can be solved to a certain extent. The integrated circuit leakage current test circuit comprises: a processor configured to send control signals to the DAC circuit, the pin configuration circuit, and receive a leakage current test voltage signal from the test circuit; a pin configuration circuit for selecting an input signal circuit for a pin to be tested of the integrated circuit according to a control signal from the processor; the DAC circuit provides a level signal and a test signal for the input signal circuit according to a control signal from a processor; and the test circuit is coupled to the processor and the pin configuration circuit and outputs a leakage current test voltage signal to the processor according to the received level signal and the test signal.
Description
Technical Field
The present disclosure relates to the field of microelectronic control technologies, and in particular, to a leakage current testing circuit and device for an integrated circuit.
Background
Leakage current is one of the important safety indicators of medical electrical equipment. According to the relevant data, on average, 1200 people in the United states die due to electric shock in the conventional diagnosis and treatment process every year, and the number of people suffering electric shock injury due to overhigh leakage current is even more countless. The generation of leakage current mainly exists in two forms, one is capacitive current, namely current passing by the current across a capacitor; one is resistive current, i.e., the current resulting from the voltage difference across the resistor, present at the application component. With the miniaturization of electronic devices, the scale of integrated circuits is increasing, and the requirements for integrated circuits are also increasing. The leakage current is one of the most important general test parameters of the integrated circuit, and the leakage current generated by the integrated circuit affects the accuracy of the product and even causes potential safety hazards.
In the implementation of some leakage circuit tests, the leakage test system comprises a plurality of independent leakage current test units and a logic controller, wherein each leakage current test unit comprises an independent test point and a point to be tested; and the leakage current test system performs logic analysis on the output signals of the leakage current test units through the logic controller to obtain a leakage current test result and transmits the leakage current test result to an external circuit. Whether the leakage current on the test point is in an allowable range is judged through an output signal generated by comparing the voltage on the test point with the reference voltage through the voltage comparator. The leakage current test system can be built in an integrated circuit and can test the leakage current of important positions of the circuit in real time.
However, the leakage current testing circuit in the above scheme has a complex structure and higher cost, and the miniaturization of the product leads to the reduction of the physical isolation of the integrated circuit chip and increases the possibility of leakage current.
Disclosure of Invention
The application provides an integrated circuit leakage current test circuit and device, through constructing pin configuration circuit, treater, DAC circuit, test circuit and its voltage follower circuit, can solve to a certain extent in the integrated circuit pin leakage current test sampling resistance both ends signal and test circuit can not keep apart, lead to the problem that the error of leakage current test result is big, the reliability reduces.
The embodiment of the application is realized as follows:
a first aspect of an embodiment of the present application provides an integrated circuit leakage current test circuit, including:
a processor configured to send control signals to the DAC circuit, the pin configuration circuit, and receive a leakage current test voltage signal from the test circuit;
a pin configuration circuit configured to select an input signal circuit for a pin to be tested of the integrated circuit according to a control signal from the processor;
a DAC circuit configured to provide a level signal, a test signal, to the input signal circuit according to a control signal from a processor;
a test circuit coupled to the processor and the pin configuration circuit, configured to output a leakage current test voltage signal to the processor according to the received level signal and the test signal.
Optionally, the test circuit includes: the current collection circuit is configured to obtain a leakage current test voltage signal passing through the sampling resistor.
Optionally, the test circuit further comprises: the first branch circuit comprises a first voltage follower circuit, and the level signal is input to the current acquisition circuit through the first voltage follower circuit; and the second branch circuit comprises a second voltage following circuit, and the test signal is input to the current acquisition circuit through the second voltage following circuit.
Optionally, the second voltage follower circuit is configured as an operational amplifier, a non-inverting input terminal of the second voltage follower circuit receives the test signal, and an output signal of the second voltage follower circuit is input to an inverting input terminal of the current collection circuit; the first voltage follower circuit is set as an operational amplifier, the positive phase input end of the first voltage follower circuit receives the level signal, and the output signal of the first voltage follower circuit is input to the positive phase input end of the current acquisition circuit.
Optionally, the current collecting circuit is configured as an operational amplifier, a positive phase input end of the operational amplifier is provided with a resistor R3 through which the level signal passes, and the operational amplifier further includes a resistor R4 arranged between the positive phase input end and a ground point; the inverting input end of the operational amplifier is provided with a resistor R1 through which the test signal passes, and the operational amplifier further comprises a resistor R2 arranged between the inverting input end and the output end.
Optionally, the current is collected, wherein the resistor R1 is equal to the resistor R3, and the resistor R2 is equal to the resistor R4.
Optionally, the test circuit further includes: an absolute value circuit configured to receive a leakage current test voltage signal from the current collection circuit and output an absolute value voltage signal; an ADC circuit configured to receive the absolute value voltage signal and convert it to a digital signal for output to the processor.
Optionally, the input signal circuit includes: high level signal circuit, low level signal circuit, test signal circuit.
Optionally, the test signal is input to the current collecting circuit through the sampling resistor.
A second aspect of the embodiments of the present application provides an integrated circuit leakage current testing apparatus, which includes any of the integrated circuit leakage current testing circuits as provided in the first aspect of the disclosure of the present application.
The beneficial effect of this application lies in: by constructing the pin configuration circuit, the processor, the DAC circuit, the test circuit and the voltage follower circuit thereof, the problems of large error and low reliability of a leakage current test result caused by the fact that signals at two ends of the sampling resistor cannot be isolated from the test circuit can be solved to a certain extent.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
FIG. 1 is a schematic block diagram illustrating an integrated circuit leakage current test circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a pin configuration circuit in an integrated circuit leakage current test circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a test circuit in an integrated circuit leakage current test circuit according to an embodiment of the present application;
FIG. 4 shows a schematic diagram of a voltage follower circuit according to an embodiment of the present application;
FIG. 5 shows a schematic diagram of a current acquisition circuit according to an embodiment of the present application;
fig. 6 shows a schematic diagram of an absolute value circuit according to an embodiment of the present application.
Detailed Description
To make the objects, technical solutions and advantages of the exemplary embodiments of the present application clearer, the technical solutions in the exemplary embodiments of the present application will be clearly and completely described below with reference to the drawings in the exemplary embodiments of the present application, and it is obvious that the described exemplary embodiments are only a part of the embodiments of the present application, but not all the embodiments.
All other embodiments, which can be derived by a person skilled in the art from the exemplary embodiments shown in the present application without inventive step, are within the scope of protection of the present application. Moreover, while the disclosure herein has been presented in terms of exemplary one or more examples, it is to be understood that each aspect of the disclosure can be utilized independently and separately from other aspects of the disclosure to provide a complete disclosure.
It should be understood that the terms "first," "second," "third," and the like in the description and in the claims of the present application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used are interchangeable under appropriate circumstances and can be implemented in sequences other than those illustrated or otherwise described herein with respect to the embodiments of the application, for example.
Furthermore, the terms "comprises" and "comprising," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such that a product or device that comprises a list of elements is not necessarily limited to those elements explicitly listed, but may include other elements not expressly listed or inherent to such product or device.
The term "component" as used herein refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and/or software code that is capable of performing the functionality associated with that element. .
Reference throughout this specification to "embodiments," "some embodiments," "one embodiment," or "an embodiment," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in various embodiments," "in some embodiments," "in at least one other embodiment," or "in an embodiment" or the like throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Thus, the particular features, structures, or characteristics shown or described in connection with one embodiment may be combined, in whole or in part, with the features, structures, or characteristics of one or more other embodiments, without limitation. Such modifications and variations are intended to be included within the scope of the present application.
Fig. 1 shows a schematic block diagram of a leakage current test circuit of an integrated circuit according to an embodiment of the present application.
An integrated circuit leakage current test circuit comprises a processor, a pin configuration circuit, a DAC circuit and a test circuit.
The processor is configured to send control signals to the DAC circuit, the pin configuration circuit, and receive a leakage current test voltage signal from the test circuit.
In some embodiments, the control signal sent by the processor to the DAC circuit is used by the DAC circuit to produce respective high and low level signals.
In some embodiments, the control signal sent by the processor to the pin configuration circuit is used for controlling the input signal circuit connected with the pin to be tested of different integrated chips in the pin configuration circuit.
A pin configuration circuit configured to select an input signal circuit for a pin under test of the integrated circuit based on a control signal from the processor.
In some embodiments, the pin configuration circuit has one end connected to the outer pin of the integrated circuit pin to be tested and another end with a plurality of different input signal circuits, and the pin to be tested of the integrated circuit can be configured to access the different input signal circuits by receiving the control signal from the processor.
And a DAC (Digital to Analog converter) circuit configured to provide a level signal and a test signal to the input signal circuit according to a control signal from a processor. The DAC circuit converts the digital signal output by the processor into an analog signal and sends the analog signal to the test circuit.
In some embodiments, the level signal is a voltage signal output by the DAC circuit, and the DAC circuit outputs a specified high level VDDmax and/or a specified low level VDDmin according to different and specific requirements of the test item. And the PIN to be tested of the integrated chip is connected with and receives the low level and/or the high level output by the DAC circuit through a selection switch PIN _ x of the PIN configuration circuit, so that the PIN to be tested of the integrated chip is connected to the test circuit.
A test circuit coupled to the processor and the pin configuration circuit, configured to output a leakage current test voltage signal to the processor according to the received level signal and the test signal.
Fig. 2 is a schematic diagram illustrating a pin configuration circuit in an integrated circuit leakage current test circuit according to an embodiment of the present application.
The PIN configuration circuit at least comprises a selection switch PIN _ x, a low level signal circuit, a high level signal circuit and a test signal circuit. The low level signal circuit receives a low level signal sent by the DAC circuit; the high-level signal circuit receives a high-level signal sent by the DAC circuit; the test signal circuit receives a test signal from the DAC circuit.
In some embodiments, the PINs to be tested of the integrated circuit are respectively connected to the PIN configuration circuit, specifically, the outer PINs of the PINs to be tested of the integrated circuit are connected to the fixed end of the selection switch PIN _ X, and the active end of the selection switch PIN _ X is connected to different input signal circuits according to the control signal sent by the processor.
For example, an integrated circuit includes 64 pins to be tested, and when a leakage current test needs to be performed on the pin a to be tested, the pin configuration circuit connects the pin a to be tested to a test signal circuit of the pin configuration circuit thereof according to a control signal from a processor; and respectively connecting the other 63 pins to be tested to the high-level signal circuit and/or the low-level signal circuit of the respective pin configuration circuit according to the requirements of the leakage current test items.
FIG. 3 is a schematic diagram of a test circuit in an integrated circuit leakage current test circuit according to an embodiment of the present application.
The test circuit is coupled to the processor and the pin configuration circuit and configured to output a leakage current test voltage signal to the processor according to the received level signal and the test signal.
The test circuit at least comprises a sampling resistor and a current acquisition circuit. The test signal is input to the current acquisition circuit through the sampling resistor, the current acquisition circuit is used for acquiring a leakage current test voltage signal passing through the sampling resistor, and the leakage current test voltage signal is then sent to the processor to complete a leakage current test.
In some embodiments, the test circuit includes 2 input signals, which are the level signal from the DAC circuit and the test signal. In some embodiments, the test circuit further comprises a first branch, the first branch further comprises a first voltage follower circuit, and the level signal is input to the current collection circuit through the first voltage follower circuit. The first voltage follower circuit is used for isolating signals at two ends of the sampling resistor from the current acquisition circuit so as to ensure the accuracy and reliability of a leakage current test result.
The level signal sent by the DAC circuit is input to the test circuit, and the level signal is firstly input to the first voltage follower circuit. The level signal is input to the non-inverting input terminal of the first voltage follower circuit, as shown in fig. 4.
In some embodiments, a first voltage follower circuit is arranged between the sampling resistor and the DAC circuit, so that the accuracy of the leakage current test is ensured.
The output signal of the first voltage follower circuit is input as an input signal to one end of the sampling resistor and the non-inverting input terminal of the current collection circuit, as shown in fig. 5.
In some embodiments, the test circuit further comprises a second branch, the second branch further comprising a second voltage follower circuit, the test signal being input to the current collection circuit through the second voltage follower circuit. And the second voltage follower circuit is used for isolating signals at two ends of the sampling resistor from the current acquisition circuit so as to ensure the accuracy and reliability of a leakage current test result.
The test signal is routed on the one hand to the sampling resistor and on the other hand to the second voltage follower circuit and then input to the current acquisition circuit.
The output signal of the second voltage follower circuit will be input as an input signal to the current acquisition circuit, as shown in fig. 5.
FIG. 4 shows a schematic diagram of a voltage follower circuit according to an embodiment of the present application.
In some embodiments, the first voltage follower circuit is configured as an operational amplifier, a non-inverting input terminal of the first voltage follower circuit receives the level signal as an input signal, and an output signal of the first voltage follower circuit is input to a non-inverting input terminal of the current collection circuit; the second voltage follower circuit is set as an operational amplifier, the positive phase input end of the second voltage follower circuit receives the test signal, and the output signal of the second voltage follower circuit is input to the negative phase input end of the current acquisition circuit.
As shown, the inverting input of the operational amplifier is connected to the output thereof, and the non-inverting input receives the input signal.
The second voltage follower circuit is coupled to the current acquisition circuit to form an isolation effect, so that the problems of large error and low reliability of a leakage current test result caused by the fact that signals at two ends of the sampling resistor cannot be isolated from the test circuit can be solved to a certain extent.
Fig. 5 shows a schematic diagram of a current collection circuit according to an embodiment of the present application.
In some embodiments, the current acquisition circuit includes 2 input signals, which are a level signal and a test signal. The current acquisition circuit comprises 1 operational amplifier and 4 resistors.
The positive phase input end of the operational amplifier is provided with a resistor R3 through which the level signal passes, and the operational amplifier further comprises a resistor R4 arranged between the positive phase input end and a grounding point.
The inverting input end of the operational amplifier is provided with a resistor R1 through which the test signal passes, and the operational amplifier further comprises a resistor R2 arranged between the inverting input end and the output end.
In some embodiments, the resistor R1 is equal to the resistor R3, and the resistor R2 is equal to the resistor R4. The output signal of the current collection circuit will be used as the input signal of the absolute value circuit, which is input to the input port ABS _ IN of the absolute value circuit, as shown IN fig. 6.
Fig. 6 shows a schematic diagram of an absolute value circuit according to an embodiment of the present application.
And the absolute value circuit is configured to receive the leakage current test voltage signal from the current acquisition circuit and output an absolute value voltage signal, so that the current passing through the sampling resistor can be tested in all directions. And the leakage current test voltage signal is input to an ABS _ IN port of the absolute value circuit and enters an inverting input end of the first operational amplifier.
When the input signal is positive voltage, the circuit can be equivalent to two unit gain reverse amplifiers in cascade connection, the effect of 'negative to positive' is achieved, and absolute value voltage is output.
In some embodiments, the 4 resistors R of the absolute value circuit are resistors of equal resistance.
In some embodiments, the test circuit further comprises an ADC circuit configured to receive the absolute value voltage signal and convert it to a digital signal for output to the processor. An output signal ABS _ OUT of the absolute value circuit is used as an input signal to be connected to an input port of the ADC circuit, and the analog signal is converted into a digital signal, and then the digital signal is processed by the processor and output to a display interface, as shown in fig. 3.
The present application further provides an integrated circuit leakage current testing apparatus, which includes any one of the integrated circuit leakage current testing circuits described in the embodiments of the present application, which has been described in detail above and is not repeated herein.
The beneficial effect of this application lies in: by constructing the pin configuration circuit, the leakage current test circuit and the processor, the problems of large error and low reliability of a leakage current test result caused by the fact that signals at two ends of the sampling resistor cannot be isolated from the test circuit can be solved to a certain extent.
Moreover, those skilled in the art will appreciate that aspects of the present application may be illustrated and described in terms of several patentable species or situations, including any new and useful combination of processes, machines, manufacture, or materials, or any new and useful improvement thereon. Accordingly, various aspects of the present application may be embodied entirely in hardware, entirely in software (including firmware, resident software, micro-code, etc.) or in a combination of hardware and software. The above hardware or software may be referred to as "data blocks," modules, "" engines, "" units, "" components, "or" systems. Furthermore, aspects of the present application may be represented as a computer product, including computer readable program code, embodied in one or more computer readable media.
The computer storage medium may comprise a propagated data signal with the computer program code embodied therewith, for example, on baseband or as part of a carrier wave. The propagated signal may take any of a variety of forms, including electromagnetic, optical, etc., or any suitable combination. A computer storage medium may be any computer-readable medium that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code located on a computer storage medium may be propagated over any suitable medium, including radio, cable, fiber optic cable, RF, or the like, or any combination of the preceding.
Computer program code required for the operation of various portions of the present application may be written in any one or more programming languages, including an object oriented programming language such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C + +, C #, VB.NET, Python, and the like, a conventional programming language such as C, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, a dynamic programming language such as Python, Ruby, and Groovy, or other programming languages, and the like. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any network format, such as a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet), or in a cloud computing environment, or as a service, such as a software as a service (SaaS).
The functions of the various elements described herein, including any functional blocks labeled as "processors" or "logic" or "circuitry," may be provided through the use of dedicated hardware as well as hardware associated with appropriate software (e.g., a processor capable of executing software). When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term "processor" or "controller" or "logic" should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, Digital Signal Processor (DSP) hardware, network processor, Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), Read Only Memory (ROM) for storing software, Random Access Memory (RAM), and non volatile storage. Other hardware, conventional and/or custom, may also be included. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the implementer as more specifically understood from the context.
Additionally, the order in which elements and sequences of the processes described herein are processed, the use of alphanumeric characters, or the use of other designations, is not intended to limit the order of the processes and methods described herein, unless explicitly claimed. While various presently contemplated embodiments have been discussed in the foregoing disclosure by way of example, it should be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described system on an existing server or mobile device.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
The entire contents of each patent, patent application publication, and other material cited in this application, such as articles, books, specifications, publications, documents, and the like, are hereby incorporated by reference into this application. Except where the application is filed in a manner inconsistent or contrary to the present disclosure, and except where the claim is filed in its broadest scope (whether present or later appended to the application) as well. It is noted that the descriptions, definitions and/or use of terms in this application shall control if they are inconsistent or contrary to the statements and/or uses of the present application in the material attached to this application.
Claims (10)
1. An integrated circuit leakage current test circuit, comprising:
a processor configured to send control signals to the DAC circuit, the pin configuration circuit, and receive a leakage current test voltage signal from the test circuit;
a pin configuration circuit configured to select an input signal circuit for a pin to be tested of the integrated circuit according to a control signal from the processor;
a DAC circuit configured to provide a level signal, a test signal, to the input signal circuit according to a control signal from a processor;
a test circuit coupled to the processor and the pin configuration circuit, configured to output a leakage current test voltage signal to the processor according to the received level signal and the test signal.
2. The integrated circuit leakage current test circuit of claim 1, wherein the test circuit comprises:
sampling resistor, current acquisition circuit, and
the current acquisition circuit is configured to acquire a leakage current test voltage signal through the sampling resistor.
3. The integrated circuit leakage current test circuit of claim 2, wherein the test circuit further comprises:
the first branch circuit comprises a first voltage follower circuit, and the level signal is input to the current acquisition circuit through the first voltage follower circuit;
and the second branch circuit comprises a second voltage following circuit, and the test signal is input to the current acquisition circuit through the second voltage following circuit.
4. The integrated circuit leakage current test circuit of claim 3,
the second voltage follower circuit is set as an operational amplifier, a positive phase input end of the second voltage follower circuit receives the test signal, and an output signal of the second voltage follower circuit is input to a negative phase input end of the current acquisition circuit;
the first voltage follower circuit is set as an operational amplifier, the positive phase input end of the first voltage follower circuit receives the level signal, and the output signal of the first voltage follower circuit is input to the positive phase input end of the current acquisition circuit.
5. The integrated circuit leakage current test circuit of claim 1, wherein the current acquisition circuit is configured as an operational amplifier, and
the positive phase input end of the operational amplifier is provided with a resistor R3 through which the level signal passes, and the operational amplifier further comprises a resistor R4 arranged between the positive phase input end and a grounding point;
the inverting input end of the operational amplifier is provided with a resistor R1 through which the test signal passes, and the operational amplifier further comprises a resistor R2 arranged between the inverting input end and the output end.
6. The integrated circuit leakage current test circuit of claim 5, wherein the current collection is performed by equalizing the resistor R1 with the resistor R3, and equalizing the resistor R2 with the resistor R4.
7. The integrated circuit leakage current test circuit of claim 1, wherein said test circuit further comprises:
an absolute value circuit configured to receive a leakage current test voltage signal from the current collection circuit and output an absolute value voltage signal;
an ADC circuit configured to receive the absolute value voltage signal and convert it to a digital signal for output to the processor.
8. The integrated circuit leakage current test circuit of claim 1, wherein said input signal circuit comprises: high level signal circuit, low level signal circuit, test signal circuit.
9. The integrated circuit leakage current test circuit of claim 2, wherein the test signal is input to the current collection circuit through the sampling resistor.
10. An integrated circuit leakage current testing apparatus comprising an integrated circuit leakage current testing circuit as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010249281.XA CN111257796A (en) | 2020-04-01 | 2020-04-01 | Integrated circuit leakage current test circuit and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010249281.XA CN111257796A (en) | 2020-04-01 | 2020-04-01 | Integrated circuit leakage current test circuit and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111257796A true CN111257796A (en) | 2020-06-09 |
Family
ID=70953255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010249281.XA Pending CN111257796A (en) | 2020-04-01 | 2020-04-01 | Integrated circuit leakage current test circuit and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111257796A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113884863A (en) * | 2021-12-03 | 2022-01-04 | 北京壁仞科技开发有限公司 | Chip and chip testing method |
-
2020
- 2020-04-01 CN CN202010249281.XA patent/CN111257796A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113884863A (en) * | 2021-12-03 | 2022-01-04 | 北京壁仞科技开发有限公司 | Chip and chip testing method |
| CN113884863B (en) * | 2021-12-03 | 2022-02-22 | 北京壁仞科技开发有限公司 | Chip and chip testing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10436874B2 (en) | Self-calibration of source-measure unit via capacitor | |
| US9921252B2 (en) | High voltage isolation measurement system | |
| EP2527854B1 (en) | Systems and methods for determining electrical faults | |
| Kumar et al. | Fuzzy classifier for fault diagnosis in analog electronic circuits | |
| EP0342784A2 (en) | Program controlled in-circuit test of analog to digital converters | |
| US10838000B2 (en) | Method and apparatus for simultaneously testing a component at multiple frequencies | |
| US20100070273A1 (en) | Speech synthesis and voice recognition in metrologic equipment | |
| CN111257796A (en) | Integrated circuit leakage current test circuit and device | |
| CN111713020B (en) | Reference noise suppression improvement based on sample and hold circuit | |
| US7969171B1 (en) | Test circuit and system | |
| Rajamani et al. | Interturn short diagnosis in small transformers through impulse injection: on‐line on‐load self‐impedance transfer function approach | |
| CN103532549A (en) | Semiconductor device and fault diagnosis system | |
| CN213069126U (en) | Integrated circuit leakage current test circuit and device | |
| CN103091561B (en) | Device obtaining direct current signals from alternative current and direct current superposition signals and method thereof | |
| US9910074B2 (en) | Digital approach to the removal of AC parasitics for impedance measurements | |
| Varaprasad et al. | A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits | |
| Kapisch et al. | An implementation of a power system smart waveform recorder using FPGA and ARM cores | |
| CN109143111A (en) | A kind of power supply changes test method, device and equipment | |
| CN110927583A (en) | Battery power detection device and battery power test method | |
| CN109799379A (en) | Method for measuring charged, charging detection device and socket | |
| Czaja | A method of fault diagnosis of analog parts of electronic embedded systems with tolerances | |
| US20210330212A1 (en) | Error correction techniques on bio-impedance measurements | |
| US20190004108A1 (en) | Apparatus and method for frequency characterization of an electronic system | |
| CN109495110A (en) | Low noise and low distortion test method and system for analog-digital converter | |
| US20230266390A1 (en) | Test Abstraction Data Model |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |