CN111244191A - Low-forward Schottky tube manufactured by bonded silicon wafers and preparation method thereof - Google Patents
Low-forward Schottky tube manufactured by bonded silicon wafers and preparation method thereof Download PDFInfo
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- CN111244191A CN111244191A CN202010219414.9A CN202010219414A CN111244191A CN 111244191 A CN111244191 A CN 111244191A CN 202010219414 A CN202010219414 A CN 202010219414A CN 111244191 A CN111244191 A CN 111244191A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 7
- 235000012431 wafers Nutrition 0.000 title claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 10
- 229910052710 silicon Inorganic materials 0.000 title claims description 10
- 239000010703 silicon Substances 0.000 title claims description 10
- 239000013078 crystal Substances 0.000 claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 5
- 238000005260 corrosion Methods 0.000 claims description 2
- 230000007797 corrosion Effects 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000000206 photolithography Methods 0.000 claims 1
- 238000005036 potential barrier Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 6
- 238000001704 evaporation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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Abstract
The invention mainly aims to provide a novel ultra-low voltage drop Schottky diode using a single crystal bonding mode and a preparation method thereof. The structure as shown in the figure: 10 is a back electrode; 20 is a high-concentration substrate; 30 is a shallow high-concentration layer diffused on the back of the low-concentration sheet; 40 is a deep high concentration layer; 50 is a low concentration single crystal layer; 60 is barrier layer and upper electrode metal layer; and 70 is an edge insulating layer. The surface area of a potential barrier region is increased by the multi-groove structure, the current of a unit chip is greatly increased, the forward conducting current is greatly increased under the condition of the same chip area, the forward voltage drop is greatly reduced under the same current, and the ultra-low forward effect is achieved. The direct bonding mode of the single crystal wafer avoids the high cost of epitaxial growth, and improves the voltage resistance and reverse leakage resistance.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices and preparation thereof, and particularly relates to a novel ultra-low voltage drop Schottky diode using a bonded single wafer and a preparation method thereof
Background
Schottky Barrier Diode (SBD) is widely used in DC-DC converter (DC-DC converter), Voltage Regulator (Voltage Regulator Module VRM), Telecom/Server (Telecom/Server), ac power adapter (adapter), and Charger (Charger). In all these applications, the schottky barrier diode needs to guarantee a certain breakdown voltage and a low forward voltage drop to guarantee low power consumption.
According to the schottky theory, the forward voltage drop of the power schottky when conducting forward is:
VF＝ФB+KT/q*Ln(JF/AT2)+JF(ρe×de+ρs×dS) - - -equation 1
Wherein: phi (BIs the barrier height, JFFor forward conduction of current, ρe，deResistivity and thickness, respectively, of the epitaxial layer, ps，dSSubstrate resistivity and thickness, respectively, are generally negligible.
JF＝I/S
Wherein I is the forward current and S is the surface area of the barrier region.
From the above formula, the forward voltage drop, the surface area S of the barrier region and the thickness d of the epitaxial layereIn close relation, the forward voltage drop is obviously reduced by increasing the surface area of the potential barrier region, and the forward voltage drop of the Schottky junction is improved by increasing the thickness of the epitaxial layer.
Generally, the schottky diode is formed by epitaxially growing an N-type low-concentration epitaxial layer on an N + type substrate, and then forming a barrier layer and a front electrode on the epitaxial layer, and using the back as a cathode. As shown in figure 1
In order to increase the surface area of the barrier region, one method is to first grow a low-concentration epitaxial layer (e.g., N-layer) of the same type on a high-concentration substrate layer (e.g., N + layer), and then lithographically etch a plurality of trenches, as shown in fig. 2, where the surface is increased to S ═ W +2nh × L, where W is the width of the chip active region, N is the number of etched trenches, h is the trench depth, and L is the length of the chip active region. The increase area is 2 nhL. But has a problem in that breakdown is generated due to reverse breakdown at a fixed positionUnder the premise of voltage, the thickness of the epitaxial layer has a lower limit value, namely breakdown is performed from the thinnest position, as shown in fig. 1, the epitaxial region below W1 is the thinnest region, and the lower limit value of the breakdown voltage must be met, so that the thickness of the epitaxial region below W2 is increased by h, and VF is increased according to formula 1: j. the design is a squareF×ρeX (h.times.W 2/W + 1/2X 2nh), expected VFThe reduced value is not reached.
Meanwhile, the above methods are all performed on an epitaxial wafer, and the ratio of the epitaxial part in the cost composition of the whole silicon wafer is very large, so that improvement is needed in terms of cost reduction.
The method for reducing the epitaxial cost is realized by using a method for bonding a single crystal wafer, but the surface area of an active region is not increased, and the aim of reducing the conduction voltage drop cannot be fulfilled.
Disclosure of Invention
The invention provides a novel ultra-low voltage drop Schottky diode using a bonded single wafer, which comprises the following structures: the high-concentration substrate slice, the back diffusion local deep high-concentration layer or the low-concentration single chip with the shallow high-concentration layer, the grooves arranged at the interval of the front surface and the deep high-concentration layer at the bottom of the low-concentration single chip, the metal barrier layer and the front surface metal electrode formed by the upper surface and the grooves, and the back electrode formed on the back surface.
The structure as shown in FIG. 3: 10 is a back electrode; 20 is a high-concentration substrate; 30 is a shallow high-concentration layer diffused on the back of the low-concentration sheet; 40 is a deep high concentration layer; 50 is a low concentration single crystal layer; 60 is barrier layer and upper electrode metal layer; and 70 is an edge insulating layer.
The back of the low-concentration single wafer is diffused with a plurality of strip-shaped or other deep high-concentration layers 40, grooves which are alternated with the deep high-concentration layers at the bottom of the low-concentration single wafer are formed on the surface of the silicon wafer, and the silicon wafer is formed by directly bonding the single wafer instead of epitaxially growing.
Because the thickness of the low-concentration single crystal layer is the same as that of the high-concentration deep diffusion junction in each area, and the resistance of the low-concentration single crystal layer through which current flows is the same, the resistance increase caused by the low-concentration layers with different thicknesses is effectively avoided, and the forward conduction voltage drop V is reduced to the maximum extentF。
The used silicon wafer is a directly bonded thin single crystal wafer, so that the cost of using an epitaxial wafer is greatly reduced. To increase the strength of the two-piece bond, a shallow high-concentration layer can be diffused over a large area on the back side of the low-concentration piece, as shown in fig. 3 as region 30.
The preparation method comprises the following steps: n-type single crystal wafer-back oxidation-back gumming-back photoetching-etching SiO 2-removing photoresist-diffusing POCL 3-etching SiO 2-diffusing POCL 3-bonding N + type single crystal wafer-high temperature annealing-thinning polishing N-layer-front oxidation-photoetching groove region-etching silicon-removing photoresist-photoetching barrier region-sputtering barrier-silicide formation-evaporating front metal-photoetching corrosion metal-back thinning-evaporating back metal.
A pattern is etched on a low-concentration single crystal wafer by photoetching, and the pattern can be a strip, a square or other polygonal circles and the like, so that high-concentration deep junction diffusion is carried out.
The front groove and the back deep-junction high-concentration layer are alternated, and the thicknesses of the low-concentration single crystal layer left on the top, the side surface of the groove and the lower part of the groove are in the same grade, and the deviation is within +/-30%.
The high-concentration single crystal wafer and the low-concentration single crystal wafer are non-epitaxial single crystal wafers and are directly bonded together.
Drawings
General planar schottky diode structure of figure 1
Fig. 2 shows a low dropout schottky diode structure with a trench structure
Fig. 3 is a new bonded single crystal ultra low drop schottky diode structure of the present invention.
Detailed Description
The present invention is further illustrated by the following specific examples, which are not intended to limit the scope of the invention.
Example (b): area of active area of chip: 2X 2mm2The back of the low-concentration single crystal layer is diffused with 20 strip-shaped deep high-concentration diffusion regions, the width of each diffusion region is 20um, the distance between each diffusion region is 80um, the depth is 30um, the depth of each shallow high-concentration region is 10um, the width of a groove table top opposite to the upper surface is 10um, the groove depth is 10um, the resistivity of the low-electric-concentration layer is 2.2 omega-cm, the thickness is 10um, and barrier metal NiPt.
The reverse breakdown voltage was 135V, the reverse leakage current was 0.5uA, and the forward conduction voltage drop was 10A, which was 0.64V.
Compared with a general product, the forward voltage drop is reduced by 22%, the voltage is increased by 20V, and the electric leakage is equivalent.
Meanwhile, the cost is reduced by more than 30%.
Of course, those skilled in the art should realize that the above embodiments are illustrative only and not limiting of the present invention, and that changes and modifications to the above described embodiments are intended to fall within the scope of the appended claims, as long as they fall within the true spirit and scope of the present invention.
Claims (8)
1. A novel ultra-low voltage drop Schottky diode of a monocrystalline bonded silicon wafer structurally comprises: the high-concentration substrate slice, the back diffusion local deep high-concentration layer or the low-concentration single chip with the shallow high-concentration layer, the grooves arranged at the interval of the front surface and the deep high-concentration layer at the bottom of the low-concentration single chip, the metal barrier layer and the front surface metal electrode formed by the upper surface and the grooves, and the back electrode formed on the back surface.
2. The novel device of claim 1 wherein the low-concentration single wafer is back-diffused with a plurality of stripes or other shaped deep high-concentration layers.
3. The novel device according to claim 1, characterized in that the silicon wafers used are single wafers bonded directly, instead of being grown epitaxially.
4. The novel device of claim 1 wherein the surface of the wafer is formed with trenches alternating with deep high concentration layers at the bottom of the low concentration single wafer.
5. A preparation method of a single crystal bonded silicon ultra-low voltage drop Schottky diode comprises the following steps: oxidizing, photoetching and etching the back of the low-concentration single chip to form a bare pattern of a strip shape, a square shape or other polygonal circles and the like, then diffusing the deep high-concentration layer, etching to remove the oxidized layer, and directly bonding the oxidized layer with the high-concentration substrate single chip; or in the diffusion deep high-concentration layer, after removing the oxide layer by corrosion, the shallow high-concentration layer is diffused in large area, and then the shallow high-concentration layer is directly bonded with the high-concentration substrate single chip; and thinning and polishing the front side of the low-concentration single crystal wafer, etching the silicon wafer to form a groove after oxidizing, photoetching and etching the pattern, and photoetching and etching the lead hole to form a metal barrier layer and front and back metal.
6. A method for manufacturing a device according to claim 5, wherein the low concentration single crystal wafer is etched by photolithography to form a trench, which may be a stripe, a square or other polygonal circle, for high concentration deep junction diffusion.
7. The front side trench of claim 5 is interleaved with the back side deep junction high concentration layer, leaving a low concentration monocrystalline layer on the top and sides of the trench and below the trench of the same thickness, within ± 30%.
8. The high and low concentration single crystal wafer as claimed in claim 5 is a non-epitaxial single crystal wafer bonded directly together.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010219414.9A CN111244191A (en) | 2020-03-25 | 2020-03-25 | Low-forward Schottky tube manufactured by bonded silicon wafers and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010219414.9A CN111244191A (en) | 2020-03-25 | 2020-03-25 | Low-forward Schottky tube manufactured by bonded silicon wafers and preparation method thereof |
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| CN111244191A true CN111244191A (en) | 2020-06-05 |
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| CN202010219414.9A Pending CN111244191A (en) | 2020-03-25 | 2020-03-25 | Low-forward Schottky tube manufactured by bonded silicon wafers and preparation method thereof |
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| CN (1) | CN111244191A (en) |
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- 2020-03-25 CN CN202010219414.9A patent/CN111244191A/en active Pending
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