CN111244187A - Nonvolatile memory - Google Patents
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Abstract
The present invention relates to a nonvolatile memory. The memory is a top gate type transistor structure or a bottom gate type transistor structure; the memory comprises a grid electrode, an insulating layer, a charge storage layer, a source/drain electrode and a semiconductor layer; the charge storage layer is provided with a semiconductor core-shell nanocrystalline structure which is in direct contact with the semiconductor layer, and the charge storage layer is arranged to realize the storage of electrons and/or holes according to different polarities of voltage applied to the grid. According to the charge storage layer, the semiconductor core-shell nanocrystalline structure is discretely distributed in the charge storage layer, and meanwhile, the semiconductor core-shell nanocrystalline structure is in direct contact with the semiconductor layer, so that when the charge storage layer captures charges, the charges can quickly reach the charge storage layer without passing through an insulating layer. The memory device has higher erasing speed by verification, and the time for erasing information is less than or equal to 50 ns; has better erasing resistance, and the erasing resistance times is more than or equal to 105Next, the process is carried out.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a nonvolatile memory.
Background
With the rapid development of the information society, the human society is experiencing an era of data explosion, and on one hand, a nonvolatile memory with larger capacity and higher reliability is required to store the data, and on the other hand, a computer with stronger computing power is required to process the data. As computer processors continue to increase in integration and performance, the speed at which computer memory is accessed has become a bottleneck limiting computing performance, referred to as "memory walls" or "von neumann bottlenecks". Therefore, high performance memory becomes an inevitable hardware requirement for information technology.
At present, a computer system adopts a three-level storage arrangement of 'cache-memory-external memory', and uses a volatile memory with extremely high access speed, including a Dynamic Random Access Memory (DRAM) and a Static Random Access Memory (SRAM), as a cache and a memory to improve the computing capacity. However, these volatile memories cannot store data when power is off, have small capacity and high price, can only alleviate the problem of memory walls, and are not the final answer to computer memories. Flash memory, as a currently used non-volatile memory device, has problems of slow erasing speed, high erasing voltage, insufficient erasing frequency, and the like.
Therefore, a new nonvolatile memory capable of solving the above technical problems is needed.
Disclosure of Invention
In view of the above, it is necessary to provide a nonvolatile memory in order to solve the above problems.
A nonvolatile memory, the memory is a top gate type transistor structure or a bottom gate type transistor structure;
the memory comprises a grid electrode, an insulating layer, a charge storage layer, a source/drain electrode and a semiconductor layer;
the charge storage layer is provided with semiconductor core-shell nanocrystalline structures which are in direct contact with the semiconductor layer, and the charge storage layer is arranged to realize the storage of electrons and/or holes according to different polarities of voltages applied to the grid.
In one embodiment, when the memory is a bottom gate transistor structure, the gate electrode, the insulating layer, the charge storage layer, the source/drain electrode and the semiconductor layer are sequentially stacked;
the semiconductor core-shell nanocrystalline structures distributed discretely in the charge storage layer are located in the range of the channel of the source/drain electrode.
In one embodiment, when the memory is a top gate transistor structure, the memory comprises, from top to bottom, a gate electrode, an insulating layer, a charge storage layer, source/drain electrodes, and a semiconductor layer;
the semiconductor core-shell nanocrystalline structures distributed discretely in the charge storage layer are located in the range of the channel of the source/drain electrode.
In one embodiment, information can be written when a positive voltage and a negative voltage are applied to the grid, and the core/shell material of the semiconductor core-shell nanocrystal structure comprises one or more of ZnSe/ZnS, CdSe/CdS, CdSe/ZnS, CdS/ZnS and InP/ZnS.
In one embodiment, the core/shell material of the semiconductor core-shell nanocrystal structure includes one or more of CdTe/CdSe, ZnTe/CdS, ZnTe/CdSe, ZnTe/ZnSe, and ZnTe/ZnS by applying a negative voltage to the gate to write information.
In one embodiment, the core/shell material of the semiconductor core-shell nanocrystal structure includes one or more of CdS/ZnTe, CdSe/ZnTe, ZnSe/ZnTe by applying a positive voltage to the gate to write information.
In one embodiment, when the core/shell material of the semiconductor core-shell nanocrystal structure is an InP/ZnS structure, the diameter of the InP core layer is between 3nm and 20nm, and the thickness of the ZnS shell layer is between 3nm and 10 nm.
In one embodiment, the thickness of the shell layer in the semiconductor core-shell nanocrystal structure is less than or equal to the diameter of the core layer.
In one embodiment, the semiconductor layer includes any one of silicon, graphene, pentacene, and indium gallium zinc oxide.
In one embodiment, the thickness of the source/drain is between 10nm and 100 nm.
According to the nonvolatile memory, the semiconductor core-shell nanocrystalline structure is discretely distributed in the charge storage layer, and is directly contacted with the semiconductor layer; so that the charge storage layer of the present application is trappedWhen acquiring the charges, the charges can quickly and nondestructively reach the charge storage layer without passing through an insulating layer. In addition, due to the unique structural advantage of the semiconductor core-shell nanocrystal structure, an energy band potential barrier existing between the core and the shell can effectively block charge recombination, so that the memory is more stable, and meanwhile, the semiconductor core-shell nanocrystal has excellent light absorption capacity and can use an optical signal as a means for writing or erasing information. By verification and referring to fig. 8, the memory device of the application has a faster erasing speed, and the information erasing time is less than or equal to 50 ns; has better erasing resistance, and the erasing resistance times is more than or equal to 105Next, the process is carried out.
Drawings
FIG. 1 is a diagram of a non-volatile memory according to an embodiment;
FIG. 2 is a diagram illustrating a structure of a non-volatile memory according to the prior art;
FIG. 3 is a graph of the transfer curves for different gate voltage scan ranges in the present application;
FIG. 4 is a schematic diagram of the performance of the memory of the present application when writing information with a positive voltage and erasing information with a negative voltage;
FIG. 5 is a schematic diagram of the performance of the memory of the present application when writing information with a negative voltage and erasing information with a positive voltage;
FIG. 6 is a diagram illustrating the performance of the memory device when writing information with negative voltage and erasing information with light according to the present application;
FIG. 7 is a schematic diagram of the performance of the memory of the present application for writing under the effect of 50ns ultrashort gate voltage pulse and erasing under the effect of 100ns ultrashort gate voltage pulse;
FIG. 8 shows a memory pass 10 of the present application5Performance diagram after sub-cycle erasing.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
The structure of a conventional metal floating gate transistor memory is shown in fig. 2, wherein the floating gate transistor memory may include a gate electrode 1, a first insulating layer 2, a floating gate layer 3, a second insulating layer 4, a source electrode 51, a drain electrode 52 and a semiconductor layer 6. In the conventional metal floating gate transistor memory, charges need to tunnel directly through the second insulating layer 4 and enter the metal floating gate layer 3 during the process of trapping the charges (i.e. during the process of erasing and writing information), but the tunneling process is a slow and destructive process, so that the erasing and writing speed of the floating gate transistor is slow (in the order of microseconds) and the erasing and writing resistance is not strong.
Based on the problem, after research, the inventor redesigns a novel nonvolatile memory, which has nanosecond erasing and writing speed, good retention performance, excellent erasing and writing resistance, bipolar storage and photoelectric erasing and writing performance. The details thereof will be described below with reference to the following embodiments and accompanying drawings.
Referring to fig. 1, the nonvolatile memory device includes, but is not limited to, a gate electrode, an insulating layer, a charge storage layer, source/drain electrodes, and a semiconductor layer; the nonvolatile memory of the present application may be divided into a top gate type memory and a bottom gate type memory according to the position of the gate. When the nonvolatile memory is a top gate type memory, the structures (the grid electrode, the insulating layer, the charge storage layer, the source/drain electrode and the semiconductor layer) are arranged from top to bottom; when the nonvolatile memory is a bottom gate memory, the above-described structures (the gate electrode, the insulating layer, the charge storage layer, the source/drain electrode, and the semiconductor layer) are sequentially stacked. The following embodiments each describe, as an example, a detailed principle of the nonvolatile memory of the present application in a bottom gate type transistor structure.
Please refer to fig. 1, which is a schematic structural diagram of a bottom gate type nonvolatile memory. The bottom gate type memory may include a gate electrode 10, an insulating layer 20, a charge storage layer (not shown), source/ drain electrodes 410 and 420, and a semiconductor layer 50, which are sequentially stacked. The gate 10 may use heavily doped conductive silicon. The source/ drain electrodes 410 and 420 may be made of any one of gold, silver, platinum, and aluminum. It should be understood that different electrodes are selected depending on the semiconductor layer 50, subject to the formation of ohmic contact between the metal and the semiconductor layer 50. In addition, the thickness of the source/ drain electrodes 410 and 420 is between 10nm and 100 nm. The insulating layer 20 may have a thickness of 300nm and may be any dielectric material, such as silicon dioxide, hafnium dioxide, polyvinylidene fluoride copolymers; wherein the polyvinylidene fluoride copolymer can be vinylidene fluoride-trifluoroethylene-chlorofluoroethylene ("P" (VDF-TrFE-CFE)). The semiconductor layer 50 may include any one of silicon, graphene, pentacene, and indium gallium zinc oxide.
The semiconductor core-shell nanocrystalline structures 310 are discretely distributed in the charge storage layer, namely, the distribution is discontinuous and irregular; in addition, the semiconductor core-shell nanocrystal structure 310 is in direct contact with the semiconductor layer 50, that is, there is no remaining dielectric layer (e.g., insulating layer) between the semiconductor core-shell nanocrystal structure 310 and the semiconductor layer 50, so that the process of trapping charges by the charge storage layer is faster and more lossless. Further, in order to make the process of charge trapping faster, the charge storage layer may be constituted only by the semiconductor core-shell nanocrystal structure 310.
Semiconductor nanocrystals refer to minute semiconductor crystal grains exhibiting size dependence between 1-100nm in particle size. The semiconductor core-shell nanocrystal structure is a composite semiconductor nanostructure formed by further effectively combining two (or more) types of semiconductor nanoparticles, and also maintains the photoelectric characteristics of the semiconductor nanocrystal.
Core-shell type composite nanoparticles can be divided into inorganic/inorganic core-shell systems and inorganic/organic core-shell systems according to the composition of the core and the shell. The inorganic/inorganic core-shell systems can be roughly classified into four types: metal/semiconductor type, metal/metal type, semiconductor/semiconductor type, and semiconductor/metal type. The core-shell semiconductor nanocrystal is mainly of a semiconductor/semiconductor type, namely nanoparticles obtained by coating two or more inorganic semiconductor materials layer by layer. Since in such core-shell structures the shell provides a physical barrier between the optically active core and its surrounding medium, making the nanocrystal less sensitive to changes in the external environment, surface chemistry and photo-oxidation.
Core-shell semiconductor nanoparticles can be mainly classified into three types according to the relative position of the electronic energy state of the semiconductor: form I, form II and inverse form I. In the type I system, a wide band gap semiconductor is used as a shell material, a narrow band gap semiconductor is used as a core material, and electrons and holes are limited in the core. The conduction and valence band edges of the core are both located within the energy band of the shell. In this system, a wide band gap shell can enhance the electron and hole confinement effect in the core, thereby enabling confinement of both electrons and holes. Whereas in a type II system, the valence band edge or conduction band edge of the shell material is located in the bandgap of the core. In this system, the band gap transition energy is small and electrons and holes are separated, so that the structure of the system can only bind one charge.
Core-shell systems are generally prepared by a two-step process: firstly, synthesizing nano core crystal, purifying and then growing the shell. This allows the amount of shell precursor to be calculated from the core concentration, thereby obtaining the shell thickness.
Further, as shown in fig. 1, the region of the charge storage layer in which the semiconductor nanocrystal structures 310 are discretely distributed in the present embodiment is mainly located between the channels of the source 410 and the drain 420, and it can be understood that the semiconductor nanocrystal structures 310 are also distributed below the source 410 and the drain 420, but the semiconductor nanocrystal structures 310 located below the source 410 and the drain 420 cannot actually store charges due to the shielding of the source 410 and the drain 420, so for simplicity and convenience of description, the semiconductor nanocrystal structures 310 below the source 410 and the drain 420 are omitted; in addition, in the present embodiment, in order to achieve charge confinement, the thickness of the shell layer of the semiconductor nanocrystal structure 310 may be set to be less than or equal to the diameter of the core layer. The charge storage layer of the present application is configured to achieve storage of electrons and/or holes depending on the polarity of a voltage applied to the gate electrode 10.
Specifically, in some embodiments, the writing of information can be realized by applying a positive voltage and a negative voltage to the gate 10, and as a realization, the core/shell material of the selected semiconductor core-shell nanocrystal structure 310 may include one or more of ZnSe/ZnS, CdSe/CdS, CdSe/ZnS, CdS/ZnS, and InP/ZnS. The ZnSe/ZnS, CdSe/CdS, CdSe/ZnS, CdS/ZnS and InP/ZnS core-shell nanocrystal structures are I-type systems, and can simultaneously realize the constraint of electrons and holes, that is, when positive voltage is applied to the grid 10, the electron storage can be realized in the semiconductor core-shell nanocrystal structure 310; when a negative voltage is applied to the gate electrode 10, hole storage can be achieved in the semiconductor core-shell nanocrystal structure 310, thereby achieving writing of information. Due to the unique structural advantage of the semiconductor core-shell nanocrystal structure, an energy band potential barrier existing between the core and the shell can effectively block charge recombination, so that the memory is more stable (refer to fig. 3, in fig. 3, the memory has a great hysteresis effect along with the expansion of an applied gate voltage range).
Further, when the core/shell material of the semiconductor core-shell nanocrystal structure 310 is an InP/ZnS structure, the diameter of the InP core layer is between 3nm and 20nm, and the thickness of the ZnS shell layer is between 3nm and 10 nm.
In some embodiments, the core/shell material of the semiconductor core-shell nanocrystal structure 310 can include one or more of CdTe/CdSe, ZnTe/CdS, ZnTe/CdSe, ZnTe/ZnSe, ZnTe/ZnS, when information is written by applying a negative voltage to the gate 10. The CdTe/CdSe, ZnTe/CdS, ZnTe/CdSe, ZnTe/ZnSe and ZnTe/ZnS core-shell nanocrystalline structures are II-type systems and can bind a charge, but the core layer material selected in the specific embodiment has a high valence band, so that the core layer material can be used for binding holes, and the holes can be stored when negative voltage is applied to the grid 10.
In some embodiments, the semiconductor core-shell nanocrystal structure 310 can include one or more of CdS/ZnTe, CdSe/ZnTe, ZnSe/ZnTe when information is written by applying a positive voltage to the gate 10. The core-shell nano-crystalline structure of CdS/ZnTe, CdSe/ZnTe, ZnSe/ZnTe is also a type II system, which can confine a charge, but since the core layer material selected in this embodiment has a low conduction band, it can be used to confine electrons, so that when a positive voltage is applied to the gate 10, the storage of electrons can be achieved.
In addition, in order to make the description of the features of the present application more detailed, the following illustrates the erasing and writing principle of the memory of the present application.
The information writing method comprises the following steps: referring to fig. 4-6, when a positive voltage is applied to the gate 10, electrons can be injected from the semiconductor layer 50 through the channel and through the nanocrystalline shell layer into the core layer, so as to implement electron storage; when a negative voltage is applied to the gate electrode 10, holes can be injected from the semiconductor layer 50 into the core layer through the channel and through the nanocrystalline shell layer, and hole storage is achieved.
The information erasing method comprises the following steps: with reference to fig. 4-7, for the case of storing electrons, by applying a negative voltage to the gate 10, the electrons can be rapidly discharged from the nanocrystal core layer, thereby implementing erasure of information; in the case where holes are stored, by applying a positive voltage to the gate electrode 10, the holes can be promptly removed from the nanocrystal core layer, thereby realizing information erasure.
The information reading method comprises the following steps: under the action of a charge electric field of the semiconductor core-shell nanocrystalline structure, the conductivity in the channel can be changed. By applying a voltage between the source 410 and the drain 420, a change in conductivity can be detected, and a read of the state of the memory device can be achieved.
In addition, taking a bottom gate type transistor memory and InP/ZnS semiconductor core-shell nano-crystal as an example, the preparation method is briefly described as follows:
1. firstly, preparing a dispersion solution of InP/ZnS semiconductor core-shell nanocrystals by a solution method, wherein the diameter of an InP core layer is controlled to be 3nm-20nm, and the thickness of a ZnS shell layer is controlled to be 3nm-10 nm;
2. then heavily doping a silicon wafer to form a grid;
3. forming a layer of silicon dioxide with the thickness of 300nm on the grid electrode by using a thermal growth technology;
4. then preparing a layer of InP/ZnS semiconductor core-shell nanocrystalline in discrete distribution on the silicon chip with the silicon dioxide layer prepared in the step 3 by using the solution prepared in the step 1 through a spin coating method;
5. and then preparing a source/drain electrode on the InP/ZnS semiconductor core-shell nanocrystalline layer by using a mask method.
6. And finally, transferring a layer of single-layer graphene grown by a CVD method on the source/drain electrode.
It can be understood that the processes of nanocrystal synthesis, thermal growth of silicon dioxide, deposition of source and drain electrodes, CVD growth of graphene, transfer of graphene and the like mentioned in the present application can refer to the prior art, and are not described herein in detail.
In conclusion, the semiconductor core-shell nanocrystalline structure is discretely distributed in the charge storage layer and is directly contacted with the semiconductor layer; when the charge storage layer captures charges, the charges can quickly and nondestructively reach the charge storage layer without passing through an insulating layer. In addition, due to the unique structural advantage of the semiconductor core-shell nanocrystal structure, an energy band potential barrier existing between the core and the shell can effectively block charge recombination, so that the memory is more stable, and meanwhile, the semiconductor core-shell nanocrystal has excellent light absorption capacity and can use an optical signal as a means for writing or erasing information.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A nonvolatile memory is characterized in that the memory is of a top gate type transistor structure or a bottom gate type transistor structure;
the memory comprises a grid electrode, an insulating layer, a charge storage layer, a source/drain electrode and a semiconductor layer;
the charge storage layer is provided with semiconductor core-shell nanocrystalline structures which are in direct contact with the semiconductor layer, and the charge storage layer is arranged to realize the storage of electrons and/or holes according to different polarities of voltages applied to the grid.
2. The nonvolatile memory according to claim 1, wherein when the memory has a bottom-gate transistor structure, the gate electrode, the insulating layer, the charge storage layer, the source/drain electrode, and the semiconductor layer are sequentially stacked;
the semiconductor core-shell nanocrystalline structures distributed discretely in the charge storage layer are located in the range of the channel of the source/drain electrode.
3. The non-volatile memory according to claim 1, wherein the memory comprises a gate electrode, an insulating layer, a charge storage layer, a source/drain electrode and a semiconductor layer from top to bottom when the memory is a top-gate transistor structure;
the semiconductor core-shell nanocrystalline structures distributed discretely in the charge storage layer are located in the range of the channel of the source/drain electrode.
4. The nonvolatile memory according to claim 1, wherein information can be written when both positive and negative voltages are applied to the gate, and the core/shell material of the semiconductor core-shell nanocrystal structure includes one or more of ZnSe/ZnS, CdSe/CdS, CdSe/ZnS, CdS/ZnS, and InP/ZnS.
5. The nonvolatile memory according to claim 1, wherein the core/shell material of the semiconductor core-shell nanocrystal structure includes one or more of CdTe/CdSe, ZnTe/CdS, ZnTe/CdSe, ZnTe/ZnSe, ZnTe/ZnS by writing information by applying a negative voltage to the gate.
6. The nonvolatile memory according to claim 1, wherein information is written by applying a positive voltage to the gate, and wherein the core/shell material of the semiconductor core-shell nanocrystal structure comprises one or more of CdS/ZnTe, CdSe/ZnTe, ZnSe/ZnTe.
7. The nonvolatile memory according to claim 4, wherein when the core/shell material of the semiconductor core-shell nanocrystal structure is an InP/ZnS structure, the diameter of the InP core layer is between 3nm and 20nm, and the thickness of the ZnS shell layer is between 3nm and 10 nm.
8. The nonvolatile memory according to claim 1, wherein the thickness of the shell layer in the semiconductor core-shell nanocrystal structure is less than or equal to the diameter of the core layer.
9. The nonvolatile memory according to any one of claims 1 to 8, wherein the semiconductor layer comprises any one of silicon, graphene, pentacene, and indium gallium zinc oxide.
10. The nonvolatile memory as in any of claims 1-8, wherein the source/drain has a thickness of between about 10nm and about 100 nm.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1864253A (en) * | 2003-10-06 | 2006-11-15 | 马萨诸塞州技术研究院 | Non-volatile memory device |
| US20090184346A1 (en) * | 2008-01-09 | 2009-07-23 | Jain Faquir C | Nonvolatile memory and three-state FETs using cladded quantum dot gate structure |
| CN102099913A (en) * | 2008-07-09 | 2011-06-15 | 昆南诺股份有限公司 | Nanostructured memory device |
| US20150097193A1 (en) * | 2011-11-28 | 2015-04-09 | Michigan Technological University | Room temperature tunneling switches and methods of making and using the same |
| US20150236029A1 (en) * | 2014-02-14 | 2015-08-20 | International Business Machines Corporation | Junction field-effect floating gate quantum dot memory switch |
| US20160204202A1 (en) * | 2012-05-07 | 2016-07-14 | Faquir Chand Jain | Quantum dot channel (qdc) quantum dot gate transistors, memories and other devices |
-
2020
- 2020-02-03 CN CN202010078655.6A patent/CN111244187B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1864253A (en) * | 2003-10-06 | 2006-11-15 | 马萨诸塞州技术研究院 | Non-volatile memory device |
| US20090184346A1 (en) * | 2008-01-09 | 2009-07-23 | Jain Faquir C | Nonvolatile memory and three-state FETs using cladded quantum dot gate structure |
| CN102099913A (en) * | 2008-07-09 | 2011-06-15 | 昆南诺股份有限公司 | Nanostructured memory device |
| US20150097193A1 (en) * | 2011-11-28 | 2015-04-09 | Michigan Technological University | Room temperature tunneling switches and methods of making and using the same |
| US20160204202A1 (en) * | 2012-05-07 | 2016-07-14 | Faquir Chand Jain | Quantum dot channel (qdc) quantum dot gate transistors, memories and other devices |
| US20150236029A1 (en) * | 2014-02-14 | 2015-08-20 | International Business Machines Corporation | Junction field-effect floating gate quantum dot memory switch |
Non-Patent Citations (2)
| Title |
|---|
| YAN, CY; WEN, JM; LIN, P; SUN, ZH: "A Tunneling Dielectric Layer Free Floating Gate Nonvolatile Memory Employing Type-I Core–Shell Quantum Dots as Discrete Charge-Trapping/Tunneling Centers", 《SMALL》 * |
| 孙海珠，祖龙飞，张恺: "《纳米粒子与聚合物功能复合材料导论》", 31 March 2015 * |
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