CN111244059A - Semiconductor package and manufacturing method thereof - Google Patents
Semiconductor package and manufacturing method thereof Download PDFInfo
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- CN111244059A CN111244059A CN201811445744.9A CN201811445744A CN111244059A CN 111244059 A CN111244059 A CN 111244059A CN 201811445744 A CN201811445744 A CN 201811445744A CN 111244059 A CN111244059 A CN 111244059A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a semiconductor package and a manufacturing method thereof. The semiconductor package includes: a rewiring layer including a first surface and a second surface opposite to the first surface; a plurality of first connectors connected to the first surface of the redistribution layer; the chips are all arranged on one side, away from the rewiring layer, of the first connecting piece and are all connected to the first connecting piece; the multiple intermediate members are connected to the second surface of the redistribution layer, a groove is formed between every two adjacent intermediate members, and one side surface, close to the redistribution layer, of the groove is in direct contact with the second surface of the redistribution layer; and the second connecting pieces are connected to one side, away from the rewiring layer, of the intermediate piece, and the chip is electrically connected to the second connecting pieces through the first connecting pieces, the rewiring layer and the intermediate piece. The arrangement of the groove can effectively avoid the cracking of the semiconductor packaging body caused by the warping of the intermediate substrate in the manufacturing process, and the yield of the semiconductor packaging body is improved.
Description
Technical Field
The present invention relates generally to semiconductor device packaging technology, and more particularly, to a semiconductor package and a method of fabricating the same.
Background
With the rapid development of wireless communication, automotive electronics, and other consumer electronics products, microelectronic packaging technology is developing towards multifunction, miniaturization, portability, high speed, low power consumption, and high reliability. In order to realize miniaturization, high speed and modularization of electronic devices, one of the packaging techniques is to package a plurality of chips together to form a packaged device, and then mount the packaged device on a printed circuit board.
The existing multi-chip packaging technology generally adopts a method of packaging a plurality of chips on an intermediate substrate, the size of the intermediate substrate is larger and larger as the number of the chips is increased or the size of the chips is larger, and the size of the intermediate substrate is generally larger than 40mm x 40 mm. However, when the larger-sized interposer substrate is used as a supporting component of a semiconductor package, the warpage is often significant, and is particularly significant during the reflow process. During the fabrication of semiconductor packages, warpage of the interposer substrate can reduce process yield and affect package reliability.
The above information disclosed in this background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not constitute prior art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
It is a primary object of the present invention to overcome at least one of the above-mentioned disadvantages of the prior art, and to provide a semiconductor package comprising:
a rewiring layer including a first surface and a second surface opposite to the first surface;
a plurality of first connectors connected to the first surface of the redistribution layer;
the chips are all arranged on one side, away from the rewiring layer, of the first connecting piece and are all connected to the first connecting piece;
the multiple intermediate members are connected to the second surface of the redistribution layer, a groove is formed between every two adjacent intermediate members, and one side surface, close to the redistribution layer, of the groove is in direct contact with the second surface of the redistribution layer; and
a plurality of second connecting pieces connected to a side of the interposer facing away from the redistribution layer,
wherein the chip is electrically connected to the second connection member through the first connection member, the redistribution layer, and the interposer.
According to one embodiment of the present invention, the redistribution layer includes an etch stop layer covering the groove.
According to one embodiment of the invention, the chip and the interposer are square plates,
the chip comprises a first edge and a second edge adjacent to the first edge, the interposer comprises a third edge parallel to the first edge and a fourth edge adjacent to the third edge and parallel to the second edge,
the sum of the side lengths of the third sides of the plurality of the intermediate members is greater than 2 times the side length of the first side, and the sum of the side lengths of the fourth sides of the plurality of the intermediate members is greater than 2 times the side length of the second side.
According to an embodiment of the present invention, the side length of the third side is less than or equal to 1.2 times the side length of the first side, and the side length of the fourth side is less than or equal to 1.2 times the side length of the second side.
According to an embodiment of the present invention, a length of the third side ranges from 0.2 to 0.8 times of a length of the first side, and a length of the fourth side ranges from 0.2 to 0.8 times of a length of the second side.
According to an embodiment of the present invention, the interposers are arranged in a matrix on the second surface of the redistribution layer.
According to one embodiment of the present invention, two adjacent chips are separated from each other to form a gap between the two adjacent chips, and the gap is aligned with one of the grooves on the other side of the redistribution layer.
According to an embodiment of the present invention, the semiconductor package further includes a first mold for packaging the redistribution layer, the first connection, and the chip together;
the first molding part comprises a first molding layer filled between the chip and the rewiring layer, and a plurality of first through holes used for accommodating the first connecting parts are formed in the first molding layer;
the first molding member further includes a second molding layer extending from the first molding layer toward the chips and filling gaps between adjacent chips.
According to one embodiment of the invention, a side of the chip facing away from the first connection element is exposed from the first molding.
According to an embodiment of the present invention, the semiconductor package further includes a second mold;
the second molding part comprises a third molding layer which covers one side of the intermediate parts, which faces away from the rewiring layer, and covers the grooves, and a plurality of second through holes for passing through the second connecting parts are formed in the third molding layer;
the second molding further includes a filling part connecting the third molding layer and filling the groove.
According to one embodiment of the present invention, at least two of the chips are electrically connected to each other through the first connection member and the redistribution layer.
According to an embodiment of the invention, a through silicon channel having one end connected to the redistribution layer and the other end connected to the second connection member is disposed in the interposer.
An embodiment of the present invention further provides a method for manufacturing a semiconductor package, including:
providing a rewiring layer on an interposer and electrically connecting the interposer to the rewiring layer;
connecting the rewiring layer with a plurality of chips by adopting a plurality of first connecting pieces;
forming a first mold that encapsulates the plurality of first connectors, the plurality of chips, and the redistribution layer together;
cutting the intermediate plate to form a plurality of mutually separated intermediate pieces, and forming a groove between every two adjacent intermediate pieces;
forming a second mold that encapsulates a plurality of the interposers together;
and connecting a second connecting piece on the intermediate piece, and enabling the chip to be electrically connected to the second connecting piece through the first connecting piece, the rewiring layer and the intermediate piece.
According to an embodiment of the present invention, in the process of disposing the redistribution layer on the interposer, an etching stop layer is formed on a surface of the interposer;
and cutting the intermediate board by adopting an etching method, wherein the slots on the intermediate board are aligned with the etching stop layer, so that the etching stop layer blocks the etching of the redistribution layer.
According to an embodiment of the invention, the method further comprises: after forming the first mold, the first mold is ground to expose a portion of the surface of the chip.
According to one embodiment of the present invention, the interposer has a through silicon via;
the method further comprises the following steps: grinding the interposer to expose the through-silicon vias in the interposer before cutting the interposer.
According to one embodiment of the invention, after the second molding is formed, the second molding is further drilled to form a second through hole exposing the through-silicon via;
connecting the second connector to the through-silicon via through the second through-hole.
According to the technical scheme, the semiconductor package and the manufacturing method have the advantages and positive effects that:
the chip may be electrically connected to a second connector through the first connector, the redistribution layer, and the interposer in sequence, the second connector being capable of connecting to other electronic devices as an external interface to the semiconductor package. Meanwhile, the groove is formed between two adjacent intermediate members and is an expansion joint of the intermediate substrate formed by the plurality of intermediate members, so that the groove can be narrowed or widened along with the expansion and contraction of the semiconductor packaging body in the manufacturing process of the semiconductor packaging body, and the semiconductor packaging body is effectively prevented from cracking due to the warping of the intermediate substrate in the manufacturing process.
Drawings
Various objects, features and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments of the invention, when considered in conjunction with the accompanying drawings. The drawings are merely exemplary of the invention and are not necessarily drawn to scale. In the drawings, like reference characters designate the same or similar parts throughout the different views. Wherein:
fig. 1 is a schematic top view of a semiconductor package according to an illustrative embodiment;
FIG. 2 is a schematic cross-sectional view of the semiconductor package shown in FIG. 1 on plane A-A;
FIG. 3 is a flow chart illustrating a method of fabricating a semiconductor package according to one embodiment;
fig. 4 is a schematic cross-sectional view of the semiconductor package after step S110, according to an embodiment;
fig. 5 is a schematic cross-sectional view of the semiconductor package after step S120, shown in accordance with an embodiment;
fig. 6 is a schematic cross-sectional view of the semiconductor package after step S130, according to an embodiment;
fig. 7 is a schematic cross-sectional view of the semiconductor package after step S150, according to an embodiment;
fig. 8 is a schematic cross-sectional view of the semiconductor package after step S160, according to an embodiment;
fig. 9 is a schematic cross-sectional view of the semiconductor package after step S170, according to an embodiment;
fig. 10 is a schematic cross-sectional view of the semiconductor package after step S180, shown in accordance with an embodiment;
fig. 11 is a schematic cross-sectional view of the semiconductor package after step S190, according to an embodiment;
fig. 12 is a schematic top view of a semiconductor package according to the second embodiment;
fig. 13 is a schematic top view of a semiconductor package according to a third embodiment.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Example one
Fig. 1 and 2 show a structure of a semiconductor package 1 in the present embodiment. The semiconductor package 1 includes a plurality of interposers 123, a plurality of chips 11, a plurality of first connections 14, a plurality of second connections 17, and a rewiring layer 13. The plurality of first connectors 14 and the plurality of interposers 123 are respectively fixed to both sides of the redistribution layer 13. The plurality of chips 11 are fixed to the first connecting member 14. The second connection member 17 is disposed on a side of the interposer 123 facing away from the rewiring layer 13. The two chips 11 can be electrically connected to each other through the redistribution layer 13, and the chips 11 are electrically connected to the second connection member 17 through the first connection member 14, the redistribution layer 13, and the interposer 123, which are connected in this order. The second connection members 17 as pins of the semiconductor package 1 can be connected to other electronic devices.
In the present embodiment, the Redistribution Layer 13 (RDL) has a sheet structure. The rewiring layer 13 includes a first surface 133 and a second surface 134 opposite to the first surface 133. The first face 133 and the second face 134 are parallel to each other. The redistribution layer 13 is a plurality of dielectric conductive layers stacked in sequence, and each dielectric conductive layer includes an insulating base material layer and a metal layer 131 embedded in the insulating base material layer. The insulating substrate layer can be made of silicon nitride, silicon oxide or polyimide and the like. The metal layer 131 can be made of a metal material, such as aluminum, gold, copper, tungsten, titanium, and alloys thereof. The metal pattern layers 131 of two adjacent dielectric conductive layers abut against each other to form a conductive path, which can make electrical conduction between the first surface 133 and the second surface 134 of the rewiring layer 13. It is also possible to form a complex three-dimensional wiring layout within the redistribution layer 13 by appropriately arranging the pattern of the metal layer 131 within each dielectric conductive layer. The redistribution layer 13 can simultaneously achieve conduction between a specific point on the first surface 133 and another specific point on the first surface 133, conduction between a specific point on the first surface 133 and a specific point on the second surface 134, and conduction between a specific point on the second surface 134 and another specific point on the second surface 134.
The first connection 14 is a conductor. The first connection 14 may be a metal ball or bump, preferably a solder ball, a solder bump or a solder pillar bump (CPB). A plurality of first connections 14 are distributed on the first surface 133 of the rewiring layer 13, and adjacent two first connections 14 are spaced apart from each other. First connector 14 is fixedly connected to metal pattern layer 131 on first surface 133 of redistribution layer 13 to form an electrical connection with redistribution layer 13.
The chip 11 may be in the shape of a square chip 11. One side of the chip 11 is provided with a bonding pad, and the bonding pad is an external input/output interface of the chip 11. The thickness of each chip 11 may be the same. The number of chips 11 may be two. The chips 11 are all tiled on the plurality of first connection members 14, and the side of the chip 11 provided with the bonding pads faces the first connection members 14. The first connecting members 14 are connected to pads of the chip 11, and the first connecting members 14 are connected to the pads in a one-to-one correspondence. The chip 11 and the first connecting members 14 form a fixed connection therebetween, and a plurality of first connecting members 14 support one chip 11. The chips 11 are preferably parallel to the first face 133 of the redistribution layer 13 with the same spacing between each chip 11 and the first face 133, so that each chip 11 and the redistribution layer 13 can be connected to each other with first connections 14 of uniform size. Two adjacent chips 11 are spaced apart from each other. Two adjacent chips 11 can be electrically connected to each other through the first connection member 14 and the rewiring layer 13.
The interposer 123 includes an interposer substrate 125 and a Through Silicon Via (TSV) 122 disposed in the interposer substrate 125. The interposer substrate 125 may be made of an insulating material such as silicon or silicon oxide. Interposer substrate 125 is configured as a plate-like structure, preferably a square plate. The through-silicon vias 122 extend vertically through the interposer substrate 125. The through silicon vias 122 are conductive vias that extend through the interposer 123. The through-silicon vias 122 may be metal lines extending from one side of the interposer 123 to the opposite side, and the metal lines may be gold, copper, or aluminum lines. The interposers 123 are distributed on the second surface 134 of the redistribution layer 13, and are fixedly connected to the redistribution layer 13. The through-silicon vias 122 of each interposer 123 are connected to the redistribution layer 13 and form an electrical connection with the redistribution layer 13. Two adjacent interposers 123 are spaced apart from each other such that a groove 124 is formed between the two adjacent interposers 123. One side of the groove 124 near the redistribution layer 13 is in direct contact with the second side 134 of the redistribution layer 13
The second connector 17 is a conductor. The second connection member 17 may be a metal ball or a metal bump, preferably a solder ball, a solder bump or a solder stud bump. The second connecting members 17 are disposed on a side of the interposer 123 away from the redistribution layer 13, and are connected to the through-silicon vias 122 in a one-to-one correspondence. In this way, an electrical connection is made between the through-silicon via 122 and the second connector 17.
The chip 11 may be electrically connected to the second connection member 17 through the first connection member 14, the redistribution layer 13, and the interposer 123 in sequence, and the second connection member 17 may be connected to another electronic device (e.g., a printed circuit board) as an external interface of the semiconductor package 1. Meanwhile, since the groove 124 is formed between two adjacent intermediate members 123, and the groove 124 is an expansion joint of the intermediate substrate composed of the plurality of intermediate members 123, the groove can be narrowed or widened along with thermal expansion and cold contraction of the semiconductor package 1 in the semiconductor package manufacturing process, and cracking of the semiconductor package 1 due to warping of the intermediate substrate in the manufacturing process is effectively avoided.
Further, the interposers 123 may be cut from the interposer 12 covering the second surface 134 of the redistribution layer 13. This makes it possible to first form the redistribution layer 13 on the interposer 12 and connect the chip 11 to the redistribution layer 13 using the first connection 14. The interposer 12 may be etched to separate the interposer 123 into a plurality of pieces by dry etching or chemical etching.
Further, the redistribution layer 13 further includes an etching stop layer 132. The etching stop layer 132 is disposed on a side of the redistribution layer 13 close to the interposer 123, covering the groove 124 between two adjacent interposers 123. Prior to etching, the etch stop layer 132 is disposed along the parting line of the interposer 12 to block the etching medium from etching onto the redistribution layer 13 when the interposer 12 is etched. . The etching stop layer 132 may be a metal layer, such as copper, aluminum, gold, etc.
Further, the chip 11, the interposer 12, and the interposer 123 are all configured as square plates. The chip 11 includes a first side and a second side adjacent to the first side.
The interposer 123 includes a third side and a fourth side adjacent to the third side. The third side of interposer 123 is parallel to the first side of chip 11. The fourth side of interposer 123 is parallel to the second side of chip 11.
The sum of the side lengths of the third sides of the plurality of interposers is greater than 2 times the side length of the first sides, and the sum of the side lengths of the fourth sides of the plurality of interposers is greater than 2 times the side length of the second sides, so that the semiconductor package 1 is in an RDL fan-out type.
The side length of the third side is less than or equal to 1.2 times the side length of the first side. The side length of the fourth side is less than or equal to 1.2 times of the side length of the second side. More preferably, the length of the third side is 0.2 to 0.8 times of the length of the first side, and the length of the fourth side is 0.2 to 0.8 times of the length of the second side.
With this arrangement, the area of the single interposer 123 is smaller, and the grooves 124 are more densely distributed, thereby better releasing the stress.
Further, a plurality of interposers 123 are arranged in a matrix on the second surface 134 of the redistribution layer 13. In this way, interposer 123 and its recesses 124 are more evenly distributed, and the force between interposer 123 and redistribution layer 13 is also more evenly distributed. It is possible to cut the intermediate sheet 12 by providing one or more slits in a direction parallel to one side of the intermediate sheet 12 and one or more slits in a direction parallel to the other side of the intermediate sheet 12 so that the grooves 124 of the finally cut intermediate sheet 12 extend in a grid-like manner.
When cutting, the cutting seam is aligned with the seam of two adjacent chips 11, so that a finally formed groove 124 is aligned with the seam, and thus, the two adjacent chips 11 are relatively independent, and the mutual influence between the two adjacent chips 11 is reduced.
Further, the semiconductor package 1 further includes a first mold 15. The first mold 15 is used to package the redistribution layer 13, the first connection 14, and the chip 11 together. The first mold 15 may be formed by a molding process, and the first mold 15 covers all the chips 11 and fills the gap between the chips 11 and the redistribution layer 13. The side of the chip 11 facing away from the first connection 14 may be exposed from the first molding 15, so that the chip 11 dissipates heat better.
The first molding 15 includes a first molding layer 151. The first molding layer 151 is filled between the chip 11 and the rewiring layer 13. The first molding layer 151 is provided with a plurality of first through holes 153 for receiving the first connectors 14, and the first connectors 14 are located in the first through holes 153. The first mold 15 encapsulates and fixes the chip 11, the first connection 14, and the redistribution layer 13 together, and reinforces the connection structure between the chip 11, the first connection 14, and the redistribution layer 13.
The first molding 15 further includes a second molding layer 152. The second molding layer 152 extends from the first molding layer 151 toward the chips 11 and fills gaps between the chips 11. The second molding layer 152 fixedly connects the first molding layer 151 and the chip 11 and fixes two adjacent chips 11 together, further enhancing the structure of the entire semiconductor package 1.
Further, the first molding layer 151 and the second molding layer 152 may be integrally formed, and are formed by one-step injection molding using the same molding compound. The molding compound may be a molding compound (epoxy molding compound).
Alternatively, the first molding layer 151 and the second molding layer 152 may be formed by two-shot injection molding using two different molding compounds, respectively. The first molding layer 151 may be made of underfill, and the second molding layer 152 may be made of molding compound.
Further, the semiconductor package 1 further includes a second mold 16. The second molding 16 includes a third molding layer 161. The third molding layer 161 covers all the interposers 123 on the side away from the redistribution layer 13, and covers the openings of the grooves 124 between two adjacent interposers 123. The third molding layer 161 is provided with a plurality of second through holes 163 for passing the second connecting members 17, and the second connecting members 17 are disposed in the second through holes 163. The third molding layer 161 may be a passivation layer or a molding encapsulant layer.
The third molding layer 161 connects the interposers 123 to each other and further fixes the second connection members 17 and the interposers 123 with respect to each other, the structural strength of the semiconductor package 1 is greater.
Further, the second molding 16 further includes a filling portion 162. The filling part 162 fills the grooves 124 between the interposers 123. The filling part 162 is also connected to the third molding layer 161. The material of the filling portion 162 may be a molding compound, which may be a molding compound. The material of the filling part 162 is preferably the same as that of the first molding layer 151.
The filling part 162 fills the grooves 124 between the interposers 123 so that the interposers 123 are connected to each other, further increasing the structural strength of the interposers 123, and at the same time, the filling part 162 supports the lifting wiring layer 13. Since the material used for the filling part 162 has a thermal expansion coefficient similar to or equal to that of the first molding member 15, even if the grooves 124 between the intermediate members 123 are filled, the function of the grooves 124 as expansion joints is not lowered.
Referring to fig. 3, the present embodiment further provides a method for manufacturing the semiconductor package 1, and the semiconductor package 1 can be manufactured by the method. The manufacturing method comprises the following steps:
step S110: referring to fig. 4, a redistribution layer 13 is provided on the interposer 12 such that one end of the through-silicon via 122 in the interposer 12 is connected to the redistribution layer 13.
The interposer 12 is preferably a silicon interposer. The interposer 12 is provided with a through-silicon via 122 extending perpendicular to the interposer 12. In the process of forming the redistribution layer 13, the metal pattern on the redistribution layer 13 is connected to one end of the through-silicon via 122, and an etching stop pattern layer 132 is formed on the surface of the interposer 12.
Step S120: referring to fig. 5, the redistribution layer 13 is connected to the plurality of chips 11 using a plurality of first connections 14.
In this step, a Flip-chip technique (Flip chip) may be used to connect the chip 11 to the redistribution layer 13 via the fused first connection 14.
Step S130: referring to fig. 6, a molding compound is filled to form a first molding 15 that encapsulates the plurality of first connectors 14, the plurality of chips 11, and the redistribution layer 13 together.
And injecting molten molding compound into a cavity which contains the first connecting piece 14, the plurality of chips 11 and the rewiring layer 13 for plastic molding by adopting an injection molding process, and solidifying the molding compound after cooling to form a first molding piece 15 which connects the first connecting piece 14, the chips 11 and the rewiring layer 13 together.
In this step, a first molding layer 151 filled between the chip 11 and the redistribution layer 13 may be formed, and after the first molding layer 151 is cured, a second molding layer 152 filling a gap between the chips 11 may be formed on the first molding layer 151; the first molding layer 151 and the second molding layer 152 may be formed at the same time to form the first molding member 15 integrally formed.
Step S140: the first mold 15 is ground to expose a portion of the surface of the chip 11.
In this step, the part of the first molding 15 covering the side of the chip 11 facing away from the first connection 14 is ground until the chip 11 is exposed.
Step S150: referring to fig. 7, one end of the interposer 12 facing away from the redistribution layer 13 is removed to expose the other end of the through-silicon via 122 facing away from the redistribution layer 13.
In this step, the end of interposer 12 facing away from redistribution layer 13 may be ground to remove a portion of the interposer substrate until through-silicon vias 122 are exposed.
Step S160: referring to fig. 8, the interposer 12 is cut to form a plurality of interposers 123 separated from each other, and a groove 124 is formed between two adjacent interposers 123.
In this step, the intermediate plate 12 may be cut by an etching method, which may be a dry etching method or a chemical etching method. Etching is performed from the side of the interposer 12 away from the redistribution layer 13 toward the redistribution layer 13, and etching is stopped until the redistribution layer 13 is reached. The surface of the redistribution layer 13 is preferably provided with an etching stop pattern layer 132 to control the depth of etching, so as to avoid damage to the redistribution layer 13 due to etching. During the dicing, the slits on the interposer 12 are aligned with the etching stop layer 132, so that the etching stop layer 132 can block the etching of the redistribution layer 13, after the dicing is completed, a groove 124 is formed between two adjacent interposers 123, and the etching stop layer 132 covers the groove 124.
Step S170: referring to fig. 9, the molding compound is filled to form a second molded part 16 that encapsulates a plurality of the interposers 123 together.
In this step, a molten molding compound may be injected into the chamber containing the redistribution layer 13 and the interposer 123, and after the molding compound completely fills the recesses 124 between the interposers, it is cooled and solidified to form the second molding compound 16 filled between the recesses 124 of the interposers 123.
In another embodiment, this step may be replaced by forming a passivation layer (passivation layer) directly on the side of interposer 123 facing away from redistribution layer 13 to cover interposer 123.
Step S180: referring to fig. 10, a second via 163 is opened in the second molding 16 so that an end portion of the through-silicon via 122 facing away from the rewiring layer 13 is exposed.
In this embodiment, after the second mold 16 is formed, the second mold 16 blocks the end of the through-silicon via 122 away from the redistribution layer 13, and a second through-hole 163 needs to be formed in the second mold 16. The second through-hole 163 may be formed in the second molding 16 by laser drilling.
Step S190: referring to fig. 11, the second connection member 17 is connected to the interposer 123 and connected to the other end of the through-silicon via 122.
The second connecting member 17 is heated to melt and then welded to the intermediate member 123 and connected to the through-silicon via 122.
Example two
The semiconductor package 1a in the second embodiment is different from the semiconductor package 1 in the first embodiment only in the intermediate member and the groove. For the sake of brevity, only the structure and shape of the interposer 123a and the recess 124a in the second embodiment will be described below.
Referring to fig. 12, in the present embodiment, the interposer 123a is a right triangle. The interposition members 123a are provided in pairs. The oblique sides of the two interposers 123a disposed in a pair are parallel to and close to each other, and the groove 124a separates the oblique sides of the interposers 123 a. The interposition members 123a are provided in two pairs, and the two pairs of interposition members 123a are separated from each other by the grooves 124 a. The chips 11a are provided in two pieces, and each chip 11a can be projected onto a pair of interposers 123a provided in pairs.
Since the groove 124a is formed between two adjacent interposers 123a, and the groove 124a is an expansion joint of the interposer substrate composed of the interposers 123a, the semiconductor package 1a can be narrowed or widened along with thermal expansion and contraction of the semiconductor package 1a in the manufacturing process, and cracking of the semiconductor package 1a caused by warpage of the interposer substrate in the manufacturing process is effectively avoided. Meanwhile, the number of the grooves 124a is small, and the machining is easier.
EXAMPLE III
The semiconductor package 1b in the third embodiment is different from the semiconductor package 1 in the first embodiment only in the intermediate member and the groove. For the sake of brevity, only the interposer 123b and the recess 124b in the third embodiment are described below.
Referring to fig. 13, in the present embodiment, the interposer 123b has a rectangular shape. The interposition member 123b is provided with four pieces. Two adjacent interposers 123b are spaced apart from each other, and a groove 124b is formed between the two adjacent interposers 123 b. The grooves 124 are connected to form a cross-shaped structure. Two chips 11b are provided, and one chip 11b can be projected onto two interposers 123b, and the other chip 11b can be projected onto the other two interposers 123 b.
Since the groove 124b is formed between two adjacent interposers 123b, and the groove 124b is an expansion joint of an interposer substrate composed of a plurality of interposers 123b, the semiconductor package 1b can be narrowed or widened along with thermal expansion and contraction of the semiconductor package 1b in the manufacturing process, and cracking of the semiconductor package 1b caused by warpage of the interposer substrate in the manufacturing process is effectively avoided. Meanwhile, the number of the grooves 124b is small, and the machining is easy.
It is to be understood that the various examples described above may be utilized in various orientations (e.g., inclined, inverted, horizontal, vertical, etc.) and in various configurations without departing from the principles of the present invention. The embodiments illustrated in the drawings are shown and described merely as examples of useful applications of the principles of the invention, which is not limited to any specific details of these embodiments.
Of course, once the above description of representative embodiments is considered in great detail, those skilled in the art will readily appreciate that many modifications, additions, substitutions, deletions, and other changes may be made to these specific embodiments, and such changes are within the scope of the principles of the present invention. Therefore, the foregoing detailed description is to be clearly understood as being given by way of illustration and example only, the spirit and scope of the present invention being limited solely by the appended claims and their equivalents.
Claims (17)
1. A semiconductor package, comprising:
a rewiring layer including a first surface and a second surface opposite to the first surface;
a plurality of first connectors connected to the first surface of the redistribution layer;
the chips are all arranged on one side, away from the rewiring layer, of the first connecting piece and are all connected to the first connecting piece;
the multiple intermediate members are connected to the second surface of the redistribution layer, a groove is formed between every two adjacent intermediate members, and one side surface, close to the redistribution layer, of the groove is in direct contact with the second surface of the redistribution layer; and
a plurality of second connecting pieces connected to a side of the interposer facing away from the redistribution layer,
wherein the chip is electrically connected to the second connection member through the first connection member, the redistribution layer, and the interposer.
2. The semiconductor package of claim 1, wherein the redistribution layer comprises an etch stop layer covering the recess.
3. The semiconductor package of claim 1, wherein the chip and the interposer are square boards,
the chip comprises a first edge and a second edge adjacent to the first edge, the interposer comprises a third edge parallel to the first edge and a fourth edge adjacent to the third edge and parallel to the second edge,
the sum of the side lengths of the third sides of the plurality of the intermediate members is greater than 2 times the side length of the first side, and the sum of the side lengths of the fourth sides of the plurality of the intermediate members is greater than 2 times the side length of the second side.
4. The semiconductor package according to claim 3, wherein a side length of the third side is less than or equal to 1.2 times a side length of the first side, and a side length of the fourth side is less than or equal to 1.2 times a side length of the second side.
5. The semiconductor package according to claim 4, wherein a side length of the third side ranges from 0.2 to 0.8 times a side length of the first side, and a side length of the fourth side ranges from 0.2 to 0.8 times a side length of the second side.
6. The semiconductor package according to claim 1, wherein the interposers are arranged in a matrix on the second surface of the redistribution layer.
7. The semiconductor package according to claim 1, wherein adjacent two of the chips are separated from each other to form a gap between the adjacent two of the chips, the gap being aligned with one of the grooves on the other side of the redistribution layer.
8. The semiconductor package of claim 1, wherein the semiconductor package further comprises a first mold for packaging the redistribution layer, the first connection, and the chip together;
the first molding part comprises a first molding layer filled between the chip and the rewiring layer, and a plurality of first through holes used for accommodating the first connecting parts are formed in the first molding layer;
the first molding member further includes a second molding layer extending from the first molding layer toward the chips and filling gaps between adjacent chips.
9. The semiconductor package of claim 8, wherein a side of the chip facing away from the first connection is exposed from the first mold.
10. The semiconductor package of claim 8, wherein the semiconductor package further comprises a second mold;
the second molding part comprises a third molding layer which covers one side of the intermediate parts, which faces away from the rewiring layer, and covers the grooves, and a plurality of second through holes for passing through the second connecting parts are formed in the third molding layer;
the second molding further includes a filling part connecting the third molding layer and filling the groove.
11. The semiconductor package according to claim 1, wherein at least two of the chips are electrically connected to each other through the first connection member and the redistribution layer.
12. The semiconductor package according to any one of claims 1 to 11, wherein the interposer has a through silicon via disposed therein, one end of the through silicon via being connected to the redistribution layer, and the other end of the through silicon via being connected to the second connection member.
13. A method for manufacturing a semiconductor package, comprising:
providing a rewiring layer on an interposer and electrically connecting the interposer to the rewiring layer;
connecting the rewiring layer with a plurality of chips by adopting a plurality of first connecting pieces;
forming a first mold that encapsulates the plurality of first connectors, the plurality of chips, and the redistribution layer together;
cutting the intermediate plate to form a plurality of mutually separated intermediate pieces, and forming a groove between every two adjacent intermediate pieces;
forming a second mold that encapsulates a plurality of the interposers together;
and connecting a second connecting piece on the intermediate piece, and enabling the chip to be electrically connected to the second connecting piece through the first connecting piece, the rewiring layer and the intermediate piece.
14. The method of claim 13, wherein an etch stop layer is formed on the surface of the interposer during the step of disposing the redistribution layer on the interposer;
and cutting the intermediate board by adopting an etching method, wherein the slots on the intermediate board are aligned with the etching stop layer, so that the etching stop layer blocks the etching of the redistribution layer.
15. The method of manufacturing of claim 13, further comprising: after forming the first mold, the first mold is ground to expose a portion of the surface of the chip.
16. The method of claim 13, wherein the interposer has through silicon vias;
the method further comprises the following steps: grinding the interposer to expose the through-silicon vias in the interposer before cutting the interposer.
17. The method of manufacturing according to claim 16, wherein after the second molding is formed, the second molding is further drilled to form a second through hole exposing the through-silicon via;
connecting the second connector to the through-silicon via through the second through-hole.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022052072A1 (en) * | 2020-09-11 | 2022-03-17 | 华为技术有限公司 | Fan-out type packaging structure and production method therefor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022052072A1 (en) * | 2020-09-11 | 2022-03-17 | 华为技术有限公司 | Fan-out type packaging structure and production method therefor |
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