CN111243485A - GOA circuit structure, display panel and display device - Google Patents
GOA circuit structure, display panel and display device Download PDFInfo
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- CN111243485A CN111243485A CN202010147469.3A CN202010147469A CN111243485A CN 111243485 A CN111243485 A CN 111243485A CN 202010147469 A CN202010147469 A CN 202010147469A CN 111243485 A CN111243485 A CN 111243485A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The embodiment of the invention discloses a GOA circuit structure and a display device, wherein the GOA circuit structure comprises: the GOA circuit comprises N sets of GOA circuits, wherein each set of GOA circuit comprises a plurality of GOA circuit units which are cascaded; 2 GOA circuit units in each set of GOA circuit are correspondingly connected with 2 high-frequency clock signal lines in the 2N high-frequency clock signal lines; wherein N is a positive integer. According to the embodiment of the application, the N sets of circuits are designed, so that the overlapping between the high-frequency clock signal lines and between the high-frequency clock signal line and the data line is reduced, and the load between the high-frequency clock signal lines and the parasitic capacitance between the high-frequency clock signal lines and the data line are reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a GOA circuit structure, a display panel and a display device.
Background
In response to the market demand, large-size, high-resolution display screens and extremely narrow frames (three sides are less than 0.9mm) become the market trend, and the requirement of the tiled screen is extremely demanding on the width of the four narrow sides. In order to achieve the advantages of low cost and good appearance, a technology of designing a GOA (Gate Driver on Array) Area in an AA (Active Area) Area is increasingly favored.
Fig. 1 shows a prior art GOA circuit structure, fig. 2 shows a layout diagram of a prior art GOA circuit structure, and fig. 1 shows that: in the prior art, the GOA trace and the Circuit are transferred to the AA area design, and when the GOA trace is in the display area, CK (high frequency clock signal) needs to cross many gates to be transmitted to the opposite side of COF (Chip on film), as shown in fig. 2: the Overlap between CK and CK results in an increase in CK Loading times, and also increases the Overlap between CK and DATA, resulting in a parasitic capacitance between CK and DATA, and thus a decrease in pixel charging capability of the display screen.
Therefore, a GOA circuit structure is needed to solve the technical problems in the prior art that the load between CK and CK is too large and the parasitic capacitance between CK and DATA is too large due to the Overlap between CK and the Overlap between CK and DATA, which leads to low pixel charging capability of the display screen.
Disclosure of Invention
The embodiment of the invention provides a GOA circuit structure, which reduces the overlapping of CK and CK by designing a plurality of sets of GOA circuits, greatly reduces CK Loading, avoids the overlapping between CK and DATA, and solves the technical problems that in the prior art, the charging capability of the GOA circuit structure is not high due to Overlap between CK and between CK and DATA, and overlarge parasitic capacitance between CK and DATA.
The application provides a GOA circuit structure, includes:
the GOA circuit comprises N sets of GOA circuits, wherein each set of GOA circuit comprises a plurality of GOA circuit units which are cascaded;
2 GOA circuit units in each set of GOA circuit are correspondingly connected with 2 high-frequency clock signal lines in the 2N high-frequency clock signal lines;
wherein N is a positive integer.
In some embodiments of the present application, the GOA circuit structure further includes N virtual GOA circuit units, and each virtual GOA circuit unit is cascaded with a last GOA circuit unit in each set of GOA circuits.
In some embodiments of the present application, the number of stages of the virtual GOA circuit units is the same as the number of high frequency clock signal lines.
In some embodiments of the present application, the GOA circuit structure further includes a low-frequency clock signal line, and the low-frequency clock signal line is connected to each of the GOA circuit units and the virtual GOA circuit unit in each set of the GOA circuits.
In some embodiments of the present application, the GOA circuit structure further includes a dc low voltage signal line, and the dc low voltage signal line is connected to each of the GOA circuit units and the dummy GOA circuit units in each set of the GOA circuits.
In some embodiments of the present application, the GOA circuit structure further includes a start signal line, and the start signal line is connected to a first GOA circuit unit in each set of the GOA circuits.
In some embodiments of the present application, the GOA circuit structure further includes a plurality of data lines, each of the GOA circuit units includes a plurality of thin film transistors, and the data lines correspond to the thin film transistors one to one.
In some embodiments of the present application, each of the data lines and each of the high frequency clock signal lines are parallel to each other.
The present invention also provides a display panel, which includes a GOA circuit structure, and the GOA circuit structure includes:
the GOA circuit comprises N sets of GOA circuits, wherein each set of GOA circuit comprises a plurality of GOA circuit units which are cascaded;
2 GOA circuit units in each set of GOA circuit are correspondingly connected with 2 high-frequency clock signal lines in the 2N high-frequency clock signal lines;
wherein N is a positive integer.
In some embodiments of the present application, the GOA circuit structure further includes N virtual GOA circuit units, and each virtual GOA circuit unit is cascaded with a last GOA circuit unit in each set of GOA circuits.
In some embodiments of the present application, the number of stages of the virtual GOA circuit units is the same as the number of high frequency clock signal lines.
In some embodiments of the present application, the GOA circuit structure further includes a low-frequency clock signal line, and the low-frequency clock signal line is connected to each of the GOA circuit units and the virtual GOA circuit unit in each set of the GOA circuits.
In some embodiments of the present application, the GOA circuit structure further includes a dc low voltage signal line, and the dc low voltage signal line is connected to each of the GOA circuit units and the dummy GOA circuit units in each set of the GOA circuits.
In some embodiments of the present application, the GOA circuit structure further includes a start signal line, and the start signal line is connected to a first GOA circuit unit in each set of the GOA circuits.
In some embodiments of the present application, the GOA circuit structure further includes a plurality of data lines, each of the GOA circuit units includes a plurality of thin film transistors, and the data lines correspond to the thin film transistors one to one.
In some embodiments of the present application, each of the data lines and each of the high frequency clock signal lines are parallel to each other.
The invention also provides a display device, which comprises a display panel, wherein the display panel comprises a GOA circuit structure.
In the embodiment of the invention, one set of GOA circuit in the prior art is split into a plurality of sets of GOA circuits, so that the overlapping between CK and between CK and DATA is reduced, the parasitic capacitance between CK Loading and CK and DATA is greatly reduced, and the charging capability of the pixels of the display device is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a GOA circuit in the prior art;
FIG. 2 is a schematic layout diagram of a GOA circuit structure in the prior art;
fig. 3 is a schematic diagram of a GOA circuit structure according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a GOA circuit unit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another GOA circuit unit according to an embodiment of the present invention;
fig. 6 is a schematic layout diagram of a GOA circuit structure according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the invention. In the following description, details are set forth for the purpose of explanation. It will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the invention with unnecessary detail. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
The embodiment of the invention provides a GOA circuit structure, a display panel and a display device. The following are detailed below.
As shown in fig. 3, which is a schematic diagram of a GOA circuit structure of the present invention, the GOA circuit structure includes:
the GOA circuit comprises N sets of GOA circuits, wherein each set of GOA circuit comprises a plurality of GOA circuit units which are cascaded; the cascade connection refers to that a signal output end of a previous GOA circuit unit is connected with a signal input end of a next GOA circuit unit;
2 GOA circuit units in each set of GOA circuit are correspondingly connected with 2 high-frequency clock signal lines in the 2N high-frequency clock signal lines;
wherein N is a positive integer.
The mode that every 2 high-frequency clock signal lines of the GOA circuit structure drive one set of GOA circuit provided by the embodiment of the invention can greatly reduce the overlapping of the high-frequency clock signal lines and reduce the load among the high-frequency clock signals, thereby avoiding the damage of the GOA circuit caused by large current caused by short circuit of different high-frequency clock signal lines due to the deterioration of the manufacturing process, and simultaneously being beneficial to reducing the manufacturing cost of the GOA circuit and the size of the GOA circuit structure due to the reduction of the overlapping of the high-frequency clock signal lines.
In addition, the cascade relation of the multiple cascaded GOA circuit units mentioned in the embodiments of the present application may be every other one, every other two, … …, every other multiple cascaded. That is, the embodiment of the present application does not limit the cascade relationship between the GOA circuit units, and the cascade relationship between the GOA circuit units may be set according to specific needs.
For example, the alternate cascade between the GOA circuit units is specifically: the level 1 GOA circuit unit is electrically connected with the level 2 GOA circuit unit, the level 2 GOA circuit unit is electrically connected with the level 3 GOA circuit unit, and so on, the level n-1 GOA circuit unit is electrically connected with the level n GOA circuit unit.
For another example, two stages of cascade connection between the GOA circuit units specifically include: the level 1 GOA circuit unit is electrically connected with the level 3 circuit GOA circuit unit, the level 3 GOA circuit unit is electrically connected with the level 5 GOA circuit unit, and so on, the level n-2 GOA circuit unit is electrically connected with the level n GOA circuit unit, wherein n is a positive integer greater than 2.
In some embodiments of the present application, as shown in fig. 4, each stage of the GOA circuit unit includes:
a pull-up control unit 100, a bootstrap unit 200, a pull-up unit 300, a pull-down unit, and a pull-down maintaining unit 400, 500; the GOA circuit unit is divided into 4 working stages, which are respectively: a first stage, a second stage, a third stage and a fourth stage;
the pull-up control unit 100 receives a start signal at a first stage to pull up the control node (Qn) of the nth level GOA unit to a first high level; the bootstrap unit 200 pulls up the control node (Qn) of the nth level GOA unit to a second high level according to a clock signal at the second stage; the pull-up unit 300 outputs a gate driving signal having a pulse width twice as large as that of the clock signal to a gate signal terminal (Gn) of the nth level GOA unit according to the first and second high voltages of the control node (Qn) of the nth level GOA unit and a clock signal output from the bootstrap unit; in the third stage, the pull-down unit 400 pulls down the control node (Qn) of the nth level GOA unit and the gate signal terminal (Gn) of the nth level GOA unit to a first dc low level; and the pull-down maintaining unit 500 maintains the control node (Qn) of the n-th GOA unit at the first dc low level and the potential of the gate signal terminal (Gn) of the n-th GOA unit at a second dc low level in the fourth stage.
In some other embodiments of the present application, as shown in fig. 5, each stage of the GOA circuit unit includes:
a pull-up control module 600, an output module 700, a pull-down module 800, and a pull-down maintenance module 900; and N is a positive integer, except for the first-level to fourth-level GOA units and the fourth-last-level to last-level GOA units, in the Nth-level GOA unit: the pull-up control module 600 is connected to the level transmission signal ST (N-4) and the high potential signal VDD of the fourth-level N-4 level GOA unit, and is electrically connected to the first node q (N), for pulling up the potential of the first node q (N) to the high potential signal VDD according to the level transmission signal ST (N-4) of the N-4 level GOA unit.
Specifically, the pull-up control module 600 includes an eleventh thin film transistor T11; the gate of the eleventh tft T11 is connected to the level transmission signal ST (N-4) of the fourth-level N-4 th-level GOA unit, the source is connected to the high voltage signal VDD, and the drain is electrically connected to the first node q (N). The output module 700 receives the clock signal CK and is electrically connected to the first node q (n) for outputting the scan signal g (n) and the level signal st (n) under the control of the potential of the first node q (n).
Specifically, the output module 700 includes a twenty-first thin film transistor T21, a twenty-second thin film transistor T22, and a first capacitor C1; the gate of the twenty-first thin film transistor T21 is electrically connected to the first node q (n), the source is connected to the clock signal CK, and the drain outputs the scan signal g (n); the gate of the twenty-second thin film transistor T22 is electrically connected to the first node q (n), the source is connected to the clock signal CK, and the drain outputs the stage signal st (n); one end of the first capacitor C1 is electrically connected to the first node q (n), and the other end is electrically connected to the drain of the twenty-first tft T21.
The pull-down module 800 includes a forty-first thin film transistor T41, a gate of the forty-first thin film transistor T41 is connected to a scan signal G (N +4) of the next-level N + 4-level GOA unit, a source is connected to a circuit start signal STV, and a drain is electrically connected to the first node q (N); the circuit start signal STV is a pulse signal, and the low potential of the circuit start signal STV is less than or equal to 0 and greater than the low potential of the low potential signal Vss, and further, the pull-down module 800 is configured to pull down the potential of the first node q (N) to the low potential of the circuit start signal STV according to the scanning signal G (N +4) of the N +4 th level GOA unit.
The plurality of GOA circuit units may be a plurality of identical GOA circuit units, or a plurality of different GOA circuit units,
when the plurality of GOA circuit units are a plurality of different GOA circuit units, the plurality of GOA circuit units may include at least one first type of GOA circuit unit and at least one second type of GOA circuit unit, the first type of GOA circuit unit may be the GOA circuit unit illustrated in fig. 4, and the second type of GOA circuit unit may be the GOA circuit unit illustrated in fig. 5.
When a plurality of different GOA circuit units are cascaded, the cascade mode may be: the first type of GOA circuit units and the second type of GOA circuit units are sequentially cascaded at intervals, or all the first type of GOA circuit units are sequentially cascaded, and after the first type of GOA circuit units are cascaded, the second type of GOA circuit units are cascaded behind the first type of GOA circuit units.
In an embodiment of the present invention, taking a GOA circuit with an 8K resolution of 6CK as an example, as shown in fig. 1, the GOA circuit needs 6 high-frequency clock signal lines, which are CK1, CK2, CK3, CK4, CK5 and CK6, each set of GOA circuits includes GOA circuit units numbered G0001-G4320, wherein the first set of GOA circuits is connected to CK1 and CK4, specifically, the GOA circuit units of G0001, G0007, G0014, etc. in the first set of GOA circuits are connected to CK1, and the GOA circuit units of G0005, G0008, G0015, etc. are connected to CK 4; similarly, the second set of GOA circuits is connected to CK2 and CK5, respectively, and the third set of GOA circuits is connected to CK3 and CK6, respectively.
Further, as shown in fig. 3, in some embodiments of the present application, the GOA circuit structure further includes N virtual GOA circuit units, and each virtual GOA circuit unit is cascaded with a last GOA circuit unit in each set of GOA circuits.
By arranging the virtual GOA circuit unit (last dummy), the etching of the GOA circuit in the manufacturing process can be ensured to be more uniform, and the stability and the reliability of the GOA circuit are improved.
It should be noted that: the circuit structure of the virtual GOA circuit unit is the same as that of the GOA circuit unit, and is not described herein again.
Further, in some embodiments of the present application, the number of stages of the virtual GOA circuit units is the same as the number of high frequency clock signal lines.
Further, as shown in fig. 3, the GOA circuit structure further includes a low-frequency clock signal line LC, and the low-frequency clock signal line LC is connected to each GOA circuit unit and the dummy GOA circuit unit in each set of GOA circuits.
Further, as shown in fig. 3, the GOA circuit structure further includes a dc low voltage signal line VSS, and the dc low voltage signal line VSS is connected to each GOA circuit unit and the dummy GOA circuit unit in each set of GOA circuits.
Further, as shown in fig. 3, the GOA circuit structure further includes a start signal line STV, and the start signal line STV is connected to the first GOA (G0001) circuit unit in each set of GOA circuits.
Specifically, the driving principle of the GOA circuit structure of the present invention is as follows: the first GOA circuit unit is driven under the combined action of the first high-frequency clock signal CK1, the low-frequency clock signal LC, the direct-current low-voltage signal line VSS and the start signal line STV, and at the same time, the first GOA circuit unit generates a trigger signal to be transmitted to the second GOA circuit unit, the second GOA circuit unit is driven under the combined action of the second high-frequency clock signal CK2, the low-frequency clock signal LC, the direct-current low-voltage signal line VSS and the trigger signal generated by the first GOA circuit unit, and at the same time, another trigger signal is generated to be transmitted to the third GOA circuit unit, and so on until all the GOA circuit units are driven.
Further, as shown in fig. 6, taking the third GOA circuit unit as an example, the GOA circuit structure further includes a plurality of DATA lines DATA for providing DATA signals, each GOA circuit unit includes a plurality of tfts T21, and the tfts T21 are connected in cascade, and the DATA lines DATA correspond to the tfts T21 one by one.
And further, each DATA line DATA and each high frequency clock signal line CK are parallel to each other. Namely: there is no overlap between the DATA line DATA and the high frequency clock signal line CK, so that parasitic capacitance between the DATA line DATA and the high frequency clock signal line CK is avoided, and the technical effect of improving the pixel charging capability of the display screen is achieved.
Besides the technical effects, the overline of each set of GOA circuits is sequentially overline from CK1-CK6 in the prior art, CK2, CK3, CK4, CK5 and CK6 are only overline with CK1, the overline amount is greatly reduced, and the technical problem of overhigh parasitic capacitance caused by overline is solved.
Furthermore, the scanning mode of the GOA circuit structure in the embodiment of the present invention is reverse scanning. It should be understood that the GOA circuit structures can also be forward scan, and when the GOA circuit structures are forward scan, the virtual GOA circuit cells are connected to the first circuit cell of each set of GOA circuits. Of course, the forward/reverse scanning mode of the GOA circuit structure can be progressive scanning or interlaced scanning, and is selected according to the actual situation.
The invention also provides a display panel, which comprises the GOA circuit structure in any embodiment.
The invention also provides a display device, which comprises the display panel in the embodiment, wherein the display panel comprises the GOA circuit structure in any embodiment.
The GOA circuit structure, the display panel and the display device provided by the present invention are described in detail above. It should be understood that the exemplary embodiments described herein should be considered merely illustrative for facilitating understanding of the core concepts of the present invention and not restrictive. Descriptions of features or aspects in each exemplary embodiment should generally be considered as applicable to similar features or aspects in other exemplary embodiments. While the present invention has been described with reference to exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present invention cover the modifications and variations of this invention provided they come within the spirit and scope of the appended claims and their equivalents and improvements made thereto.
Claims (10)
1. A GOA circuit architecture, comprising:
the GOA circuit comprises N sets of GOA circuits, wherein each set of GOA circuit comprises a plurality of GOA circuit units which are cascaded;
2 GOA circuit units in each set of GOA circuit are correspondingly connected with 2 high-frequency clock signal lines in the 2N high-frequency clock signal lines;
wherein N is a positive integer.
2. The GOA circuit architecture of claim 1, further comprising N virtual GOA circuit cells, each of which is cascaded with a last of the GOA circuit cells in each set of GOA circuits.
3. The GOA circuit architecture of claim 2, wherein the number of levels of the virtual GOA circuit units is the same as the number of high frequency clock signal lines.
4. The GOA circuit architecture of claim 3, further comprising a low frequency clock signal line, wherein the low frequency clock signal line is connected to each GOA circuit unit and the dummy GOA circuit unit in each set of GOA circuits.
5. The GOA circuit architecture of claim 3, further comprising a dc low voltage signal line, wherein the dc low voltage signal line is connected to each GOA circuit unit and the dummy GOA circuit unit in each set of GOA circuits.
6. The GOA circuit structure of claim 3, further comprising an enable signal line connected to a first GOA circuit unit in each set of the GOA circuits.
7. The GOA circuit structure of claim 1, further comprising a plurality of data lines, wherein each GOA circuit unit comprises a plurality of thin film transistors, and each data line corresponds to each thin film transistor.
8. The GOA circuit architecture of claim 7, wherein each data line and each high frequency clock signal line are parallel to one another.
9. A display panel comprising a GOA circuit structure, the GOA circuit structure comprising:
the GOA circuit comprises N sets of GOA circuits, wherein each set of GOA circuit comprises a plurality of GOA circuit units which are cascaded;
2 GOA circuit units in each set of GOA circuit are correspondingly connected with 2 high-frequency clock signal lines in the 2N high-frequency clock signal lines;
wherein N is a positive integer.
10. A display device comprising the display panel according to claim 9, the display panel comprising a GOA circuit structure.
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| CN111754943A (en) * | 2020-06-16 | 2020-10-09 | 武汉华星光电半导体显示技术有限公司 | Display panel |
| US11663964B2 (en) | 2020-06-16 | 2023-05-30 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel |
| CN113178159A (en) * | 2021-04-23 | 2021-07-27 | 京东方科技集团股份有限公司 | Initial signal providing module, method and splicing display device |
| WO2022222444A1 (en) * | 2021-04-23 | 2022-10-27 | 京东方科技集团股份有限公司 | Start signal providing module and method, and tiled display apparatus |
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