CN111241007B - Data reading and writing method and device and dynamic random access memory - Google Patents

Abstract

The invention provides a data read-write method, a read-write device and a dynamic random access memory, wherein a page read-write mode is entered according to a mode selection command, and the page read-write mode command is configured through a mode register of the dynamic random access memory; receiving page read-write commands, including page read-write enabling commands and cross read commands, wherein the page read-write enabling commands are configured through first reserved bits of read-write commands of the dynamic random access memory, the cross read commands are configured through second reserved bits of the read-write commands of the dynamic random access memory, and the cross read commands are used for controlling cross read-write of data in a plurality of storage block groups; and executing cross page read-write operation according to the page read-write command.

Description

Data reading and writing method and device and dynamic random access memory

Technical Field

The invention relates to the technical field of memories, in particular to a data reading and writing method, a data reading and writing device and a dynamic random access memory.

Background

With the rapid development of memories, it is expected that memories can provide faster and faster read and write rates and lower power consumption.

Generally, the data required by the command for accessing the memory is often large, and the read-write length supported by the memory is small at present, so that the processing of one access data can be completed by sending a plurality of read-write instructions, and the read-write speed is limited. In addition, when each read-write command is sent, various processing circuits in the memory perform a turning action, so that the power consumption is high, and the power consumption of the whole memory is high.

It is to be noted that the information invented in the above background section is only for enhancing the understanding of the background of the present invention, and therefore, may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a data reading and writing method, a data reading and writing device and a dynamic random access memory, and solves the problems of small reading and writing length and limited reading and writing speed of the memory in the related technology.

According to a first aspect of the present disclosure, there is provided a data reading and writing method applied to a dynamic random access memory, including:

entering a page read-write mode according to a page read-write mode command, wherein the page read-write mode is configured through a mode register of the dynamic random access memory;

receiving page read-write commands, including page read-write enabling commands and cross read commands, wherein the page read-write enabling commands are configured through first reserved bits of read-write commands of the dynamic random access memory, the cross read commands are configured through second reserved bits of the read-write commands of the dynamic random access memory, and the cross read commands are used for controlling cross read-write of data in a plurality of storage block groups;

And executing cross page read-write operation according to the page read-write command.

According to an embodiment of the present disclosure, the page read/write command further includes a page read/write length command, configured to indicate a read/write length of each page read/write operation, where the page read/write length command is configured by a burst length bit in the dram read/write command.

According to an embodiment of the present disclosure, the page read/write command further includes a page read/write length command, configured to indicate a read/write length of each page read/write operation, where the page read/write length command is configured in a burst length bit and a plurality of column address bits in the dram read/write command.

According to an embodiment of the present disclosure, the column address bits include one address bit or two address bits.

According to an embodiment of the present disclosure, the dynamic random access memory is a fifth generation double rate synchronous dynamic random access memory, wherein,

the burst length bit is a command bit corresponding to the CA5 pin;

the first reserved bit of the read-write command is a command reserved bit corresponding to a CA9 pin, and the second reserved bit of the read-write command is a command reserved bit corresponding to a CA12 pin.

According to an embodiment of the present disclosure, the dynamic random access memory is a fifth generation low power double rate synchronous dynamic random access memory, wherein,

The plurality of column address bits are column address bits corresponding to the CA0 pin, or column address bits corresponding to the CA0 pin and the CA1 pin.

According to an embodiment of the present disclosure, the page read-write operation is to read and write data of N/16 pages per read-write command, where N is greater than or equal to 1 and less than or equal to 16, and N is a natural number.

According to an embodiment of the present disclosure, N-1, N-2, N-4, or N-8.

According to an embodiment of the present disclosure, the read-write order of the page read-write operation is a linear read-write order.

According to an embodiment of the present disclosure, the page read/write operation may be read/write across pages or without page crossing.

According to a second aspect of the present disclosure, there is provided a data reading and writing apparatus including:

the mode register is used for controlling the dynamic random access memory to enter a page read-write mode according to the page read-write mode command;

the command receiving module is connected with the register and used for receiving page read-write commands and transmitting the page read-write commands to the mode register, wherein the page read-write commands are configured through reserved bits of read-write commands of the dynamic random access memory;

and the addressing module is connected with the command receiving module and the mode register and is used for cross-selecting storage addresses in a plurality of storage blocks according to the page read-write command.

According to an embodiment of the present disclosure, the data reading and writing device further includes:

and the selection module is connected with the addressing module and is used for outputting the read-write addresses in the plurality of storage block groups in a crossed manner according to the crossed read command.

According to a third aspect of the present disclosure, a data reading and writing device for a dynamic random access memory is provided.

The method takes a dynamic random access memory mode register as a switch of a page read-write mode, takes a first reserved bit of a read-write command as an enabling command of page read-write operation, and takes a second reserved bit of the read-write command as an intersecting read command, so that the data volume read and written by each read-write command is improved, and the data are alternately read and written in a plurality of storage block groups. On one hand, the data read-write time is reduced, and the read-write speed is improved. Meanwhile, the frequency of sending the read-write command is reduced, the triggering frequency of related circuits is reduced, the overall power consumption of the memory is greatly reduced, the problem that the data read-write speed and the transmission bandwidth are not matched is solved by reading and writing the data in the plurality of storage block groups in a crossed manner, and the utilization rate of the transmission bandwidth is improved. On the other hand, the function of the reserved bit of the memory is fully exerted, a new memory does not need to be designed and manufactured, and the cost is saved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

FIG. 1 is a diagram of a data access architecture;

FIG. 2 is a diagram illustrating a conventional data read/write mode;

FIG. 3 is a diagram illustrating conventional data read/write transmission;

FIG. 4 is a flow chart of a data reading and writing method of the present invention;

FIG. 5 is a diagram of a data read/write mode according to the present invention;

FIG. 6 is a schematic diagram of a memory controller and memory read and write operations;

FIG. 7 is a truth table for DDR5 read-write commands;

FIG. 8 is a diagram of a data read/write apparatus.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

As shown in fig. 1, currently, an AXI interface is mostly used in a system-on-chip as an interface for Direct Memory Access (DMA) to Access a Dynamic Random Access Memory (DRAM), for example, GPU/video/DISPLAY accesses the DRAM through the AXI interface, a bit width (AXI _ size) of data in a corresponding AXI command is usually 256 bits, and a length of the data is usually 8 or 16, that is, data required by each accessed command includes 8 or 16 data with a bit width of 256 bits.

Taking a fifth generation double data rate synchronous dynamic random access memory (hereinafter referred to as DDR5) as an example, the current DDR5 supports a burst length of 32 or 16 (i.e., BL32 or BL16), and the DQ of DDR5 has a bit width of 16 bits, so that each read/write command can read/write 32 × 16bit data or 16 × 16bit data. Taking BL16 as an example, each DDR5 read-write command can read and write 16 × 16bit data, and then 16 read-write commands need to be sent to process one AXI access command into 16 × 256bit data, as shown in fig. 2. Similarly, when the burst length is 32, 8 read and write commands need to be sent. When reading and writing commands, the input/output of the DRAM, the input/output of the system level chip and the command processing circuit of the system level chip are all overturned, and certain power is consumed. And DDR5 will turn on the termination resistor at high speed, which consumes more power. Therefore, the power consumed by the current memory during reading and writing data is high, which causes the power consumption of the whole memory to be large.

And the transmission speed of the data line bandwidth is higher than the data read-write speed when data is transmitted, so that the bandwidth is wasted. For example, when reading data, 16-bit data is read once, and at this time, as shown in fig. 3, the bandwidth of the data line is left in the read interval portion (z region in the figure), which wastes bandwidth.

The embodiment of the invention provides a data reading and writing method which can provide higher reading and writing speed and lower power consumption. The read-write method can be any one of a fifth generation double-rate synchronous dynamic random access memory (DDR5 SDRAM) and a fifth generation low-power consumption double-rate synchronous dynamic random access memory (LPDDR5 SDRAM).

As shown in fig. 4, the data read-write method according to the embodiment of the present invention is applied to data read-write operation of a dynamic random access memory, and includes:

step S410, entering a page read-write mode according to a page read-write mode command, wherein the page read-write mode is configured through a mode register of the dynamic random access memory;

step S420, receiving page read/write commands, including a page read/write enable command and a cross read command, where the page read/write enable command is configured by a first reserved bit of a read/write command of the dynamic random access memory, the cross read command is configured by a second reserved bit of the read/write command of the dynamic random access memory, and the cross read command is used to control to cross read/write data in a plurality of storage block groups (BG, bank groups);

And step S430, executing cross page read-write operation according to the page read-write command.

The data size of a page of the synchronous dynamic random access memory device is usually 1KB, 2KB and the like, and the page is divided into a plurality of parts as the read-write length of each read-write command, so that each read-write command can read and write a larger amount of data. Compared with the 32 × 16bit or 16 × 16bit data volume of the existing burst read/write, the data volume that can be read/written by the page read/write command is greatly increased, for example, it can reach 16 × 256bit, and only one read/write command needs to be sent after one access command data is read/written, as shown in fig. 5.

The existing memory is provided with reserved bits for expansion, page read-write commands are constructed by utilizing the reserved bits, the functions of the existing memory can be fully exerted, a new memory does not need to be designed and manufactured, and the cost is saved. The invention takes the dynamic random access memory mode register as a switch of a page read-write mode, takes the first reserved bit of a read-write command as an enabling command of page read-write operation, and takes the second reserved bit of the read-write command as an intersecting read command, thereby improving the read-write data volume of each read-write command and realizing the intersecting read-write data in a plurality of storage block groups. On one hand, the data read-write time is reduced, and the read-write speed is improved. Meanwhile, the frequency of sending the read-write command is reduced, the triggering frequency of related circuits is reduced, the overall power consumption of the memory is greatly reduced, the problem that the data read-write speed and the transmission bandwidth are not matched is solved by reading and writing the data in the plurality of storage block groups in a crossed manner, and the utilization rate of the transmission bandwidth is improved. On the other hand, the function of the reserved bit of the memory is fully exerted, a new memory does not need to be designed and manufactured, and the cost is saved.

The following describes the data read/write method according to the embodiment of the present invention in detail by taking DDR5 SDRAM as an example:

the data reading and writing of the invention comprises reading and writing of data, so the method of the invention can be a data reading method and a data writing method. Correspondingly, the read-write method, the read-write command, the read-write mode, and the like in this document may represent a read method, a read command, a read mode, and may also represent a write method, a write command, and a write mode. The method of the invention can be used for only reading or writing data, and can also be used for reading and writing data simultaneously.

A page as referred to in this disclosure refers to a page (page) that is composed of every row in the memory array. When the page read-write command reads and writes data, a part of the data volume of each page is used as the read-write length. The mode register is used to set the operation mode of the memory, and the operation mode of the page read/write operation needs to be set in the mode register in order to realize the page read/write operation. The operation mode of the page read and write operation utilizes the mode register as a switch for the page read and write mode.

The page read and write commands are sent to the DRAM through a memory controller (DRAM controller) which is used to coordinate the exchange of signals between the Central Processing Unit (CPU) of the control system and its DRAM to take advantage of the efficient data transfer, as shown in fig. 6. The memory controller establishes all row addresses, column addresses, access timing sequences, refreshing requirements, timing parameters and the like, and can establish read-write commands according to read-write operation requests so as to realize data transmission. Of course, the read/write command that can be constructed by the memory controller may only include a page read/write command, or may include both a page read/write command and a burst read/write command, that is, the memory may use a page read/write operation method when reading and writing data, or may select another read/write method, such as a burst read/write method.

In the present exemplary embodiment, in step S410, the page read/write mode is configured by a mode register of the dynamic random access memory.

Specifically, a page read/write operation mode command may also be set in a mode register, which is used as a page read/write mode switch, and the page read/write mode is triggered when the command bit in the mode register is 1. Of course, in practical applications, the page read/write mode may also be triggered when the command bit in the mode register is 0, which is not specifically limited in the embodiment of the present disclosure.

In step S420, the read/write enable command in the page read/write command is used to provide a command whether to execute the page read/write operation, and is configured by the first reserved bit of the read/write command of the dynamic random access memory, and the cross read command is configured by the second reserved bit of the read/write command of the dynamic random access memory, so as to fully utilize the spare position of the read/write command. And writing data into the memory or reading data from the memory according to the page read-write command.

For example, in the DDR5 command, as shown in fig. 7, the command bit corresponding to the CA9 pin in the read/write command is the first reserved bit, which is used as the page read/write enable (PP) bit in the present embodiment, when a high level is received, page read/write is performed, and when the enable command is a low level, burst read/write is performed. Taking an AXI command of reading a 16 × 256bit as an example, if the pin CA9 is set low, a burst read operation is performed, and if the pin CA9 is set high, a page read operation is performed. The command bit corresponding to the CA12 pin in the read/write command is the second reserved bit, which is used as an interleaved read command (IPP) bit in the present embodiment, and when receiving a high level, the interleaved read/write is performed, and if the CA12 pin is set high, the interleaved read operation is performed on a plurality of BGs. For example, for two BGs, data is alternately read from BG1 and BG2 by an interleaving read command, if data is read from BG1 first, a command of a second reserved bit is used to indicate that one data in BG1 is read and written, and then one data needs to be read and written in BG2, and after one data in BG2 is read and written, one data needs to be read and written in BG1 again, and so on.

In the present exemplary embodiment, the page read/write command of step S420 further includes a page read/write length command for indicating the read/write length of each page read/write operation, and the page read/write length command is configured by a burst length bit in the dynamic random access memory read/write command. In burst read and write mode, burst length bits are used to select burst length, and in page read and write mode, burst length bits are used to select page read and write length.

The command bit corresponding to the CA5 pin in the DDR5 controller read-write command is a Burst Length (BL) bit, and this embodiment uses this as a command bit of the page read-write length to select the page read-write length. The page read/write length command of this embodiment includes two different read/write lengths. For example, in page read/write mode of operation, when the burst length bit is high, 1/4 pages of data are read/written per page read/write command. For example, for an AXI access command to read 16 × 256-bit data, since the 16 × 256-bit is 512B, 1/4 pages, the total length of the data is 1/4 pages, and thus, only one page read command is needed to read the data, thereby greatly reducing the number of times of sending commands. When the burst length bit is low, 1/8 pages of data are read per read command, and two paging read commands are required to read the data. The same applies to the writing method. In addition, the page read-write length represented by the burst length bit may be other lengths, for example, the page read-write length at the high level is 1/8 pages, and the page read-write length at the low level is 3/8 pages; or the low level page read-write length is 5/16 pages, the high level page read-write length is 1/8 pages, and so on; as long as the two are different, two different page read-write lengths can be selected to meet the requirements of different sizes of access command data volume.

The example of reading an AXI access command of 16 × 256 bits is further described as how the page read/write is performed. When reading data, when the page reading mode command bit in the mode register is configured as 1, page reading can be adopted, if the reading position corresponding to the CA9 pin is high, page reading is executed, if the reading length command position of the CA5 pin is low, the page reading length is 1/8 pages, and 2 times of commands are needed to complete data reading; if the position of the read length command on the pin of CA5 is high, the read length is 1/4 pages, and 1 command needs to be sent to complete data reading. It can be seen that the number of reads can be greatly reduced with the page read operation.

Because the read-write length of the above embodiment is only selected in two kinds, the applicable occasion is single, and if the data volume of the access command is changed more, the settable range of the page read-write length can be increased to provide more suitable selections. For example, for DDR5, the page read/write length only includes 1/16 pages and 1/8 pages, if the data size of one access command is 1/4 pages, at least two page read/write commands are required to complete the entire read/write task, and if the page read/write length of 1/4 pages can be set, only one page read/write command is required to complete the task, which can further reduce the read/write power consumption. Therefore, in the present exemplary embodiment, the page read/write length command is configured with a burst length bit and several column address bits in the dynamic random access memory read/write command. In the page read/write operation mode, the column address bits are used as the access length code, and the burst length bits in the page read/write command form binary numbers of two, three or more bits, so that more page read/write length selections can be provided. One column address bit and burst length bit form a two-bit binary number, and three or four page read-write lengths can be set; two column address bits and burst length bits form a three-bit binary number, and four to eight kinds of page read-write lengths can be set; three column address bits and burst length bits constitute a four-bit binary number, nine to sixteen page read and write lengths may be set, and so on. Therefore, the more appropriate page read-write length can be selected according to the access commands with different data volumes, so that the times of page read-write commands are reduced as much as possible, the read-write speed is improved, and the power consumption is reduced.

In the present exemplary embodiment, the number of column address bits is one or two, and the read/write length command includes three to eight different read/write lengths for the current dynamic random access memory. For example, in an exemplary embodiment, as shown in fig. 7, C2 column address bits corresponding to CA0 pin of DDR5 and C3 column address bits corresponding to CA1 pin may be used together to encode page read/write length, and combined with the burst length bits of CA5 pin into three bits to support the selection of up to eight page read/write lengths. Or only the C2 column address bit corresponding to the CA0 pin and the burst length bit of the CA5 pin can be selected to be combined into two bits to support the selection of up to four page read and write lengths, and then the C3 column address bit corresponding to the CA1 pin can be used for column addressing.

In the exemplary embodiment, the page read/write operation is to read/write data of N/16 pages per read/write command, where N is greater than or equal to 1 and less than or equal to 16, and N is a natural number. The data of one page is divided into 16 parts, and the data of 1/16 can be read and written at least once, and the data of one page can be read at most once. N may be an even number or an odd number. The page read/write length command configuration can be specifically utilized according to read/write needs.

In the present exemplary embodiment, N may be equal to 1, 2, 4 or 8, that is, the data length that can be read and written by each page read and write command is 1/16 pages, 1/8 pages, 1/4 pages or 1/2 pages. This arrangement can well meet the data transmission requirements of the existing DDR 5. For example, in DDR5, a data size of a page is usually 1KB or 2KB, when a data size of a page is 2KB and a single AXI access command is 16 × 256bit data, since 16 × 256bit equals 512B equals 1/4 pages, the total length of the data is 1/4 pages, the page read/write length of the page read/write command in this embodiment is set to 1/4 pages, that is, N equals 4 pages, and the data only needs one page read/write command to complete the transmission; if the read-write length of the page read-write command in this embodiment is set to 1/8 pages, that is, N is 8, the data needs two page read-write commands to complete the transmission. Similarly, when the size of a page of data is 1KB and an AXI access command is 8 × 256-bit data, since 8 × 256-bit equals 256B equals 1/8 pages, the total length of the data is 1/8 pages, then the read-write length of the page read-write command in the embodiment is set to 1/8 pages, that is, N equals 8, and the data can be transmitted only by one page read-write command; if the read-write length of the page read-write command in this embodiment is set to 1/16 pages, that is, N is 16, then the data needs two page read-write commands to complete the transmission. For example, when a page data size is 1KB and an AXI access command is 16 × 256bit data, since 16 × 256bit is 512B 1/2 page, the total length of the data is 1/2 page, the read-write length of the page read-write command in this embodiment is set to 1/2 page, that is, N is 2 page, the data can be transferred only by one page read-write command; if the read-write length of the page read-write command in this embodiment is set to 1/4 pages, that is, N is 4, then the data needs two page read-write commands to complete the transmission. In other embodiments of the present invention, N may also be equal to 1, 2, 4, or 8 for LPDDR5, which is not listed here.

In the present exemplary embodiment, the read-write order of the page read-write operation may be a linear read-write order. A large amount of data is read and written from a certain initial address according to a certain sequence, namely, one byte of data in a data stream can be received or one byte of data can be written in by automatically adding 1 to the address each time, and the linear burst transmission can more effectively use the bandwidth of a bus to transmit the data so as to reduce meaningless address operation. In other embodiments of the present invention, the read/write order of the page read/write operations may be an interleaved read/write order.

In the present exemplary embodiment, the page read and write operation may be read and written across pages or without pages. The reading and writing method can be used for a memory supporting cross-page reading and writing, and only after reading and writing one page of data, if the reading and writing command of the current page is not finished, reading and writing are continuously carried out from the new page until the reading and writing task is finished. For example, the page read/write length is 5/8 pages, the first page read/write command reads/writes 5/8 data of the current page, and when the second page data read/write is performed, the remaining 3/8 pages of data of the current page can be completely read/written, and the previous 2/8 data of the next page can be continuously read/written. The reading and writing method of the present invention can also be used in a memory that does not support cross-page reading and writing, where each data read or written continuously can only be on the same page, but cannot exceed the current page, for example, the page reading and writing length is 5/8 pages, the first reading and writing command reads and writes 5/8 data of the current page, and if the second reading and writing is performed, 5/8 data need to be read and written from the next page.

It can be understood by those skilled in the art that, in the above embodiments, the read/write mode and the read/write length represented by the level state can be completely interchanged, and the present invention is not limited to this.

The embodiment of the invention also provides a data reading and writing device so as to realize the data reading and writing method. In order to make the memory adopt a page read-write mode. For example, as shown in fig. 8, the read/write device may include a command receiving module 100, a command decoding module 200, a mode register 300, and an addressing module 400. The mode register 300 is used for controlling the dynamic random access memory to enter a page read-write mode according to a page read-write mode command; the command receiving module 100 is connected to the register, and configured to receive a page read/write command, and transmit the page read/write command to the mode register 300, where the page read/write command is configured by a reserved bit of a read/write command of the dram; the addressing module 400 is connected to the command receiving module and the mode register, and is configured to cross-select storage addresses in a plurality of storage blocks according to the page read/write command.

Further, the data reading/writing device further includes a selection module 500, where the selection module 500 is connected to the addressing module 400, and is configured to output the reading/writing addresses in multiple storage block groups according to the cross reading command in a cross manner.

The addressing module 400 includes an array selection module and a column address addressing module. The array selection module is connected with the command decoding module and the page read-write mode selection module and is used for selecting an array for reading and writing data according to the data read-write command and the read-write mode. The column address addressing module is connected with the command decoding module and the page read-write mode selection module and is used for selecting a column address for reading and writing data according to the data read-write command and the read-write mode. The corresponding selection module 500 includes two Selectors (MUXs) respectively connected to the array selection module and the column address addressing module.

The reading and writing device receives and decodes the page reading and writing command, enters a page reading and writing mode, selects one piece of reading and writing data in a plurality of storage block groups according to the page reading and writing enabling command and the cross reading command, determines the reading and writing storage block groups, selects a reading and writing array through an array selection module, selects a reading and writing column through a column address addressing module, and further reads and writes. And after each array is selected, keeping reading and writing data in the current array. After the column address addressing module selects a column of data, 1 is automatically added to carry out automatic and continuous data reading and writing. The number of times of automatic addition of 1 is determined according to the page read-write length, namely the read-write length represented by the read-write command bit and the column address bit of the CA5 pin. And after the command is read, reading and writing data in another BG according to the cross reading command.

The embodiment of the invention also provides a dynamic random access memory, which comprises the data read-write device, and the memory can read and write a large amount of data at one time, and has the advantages of less read-write times, high read-write speed and low overall power consumption.

The dynamic random access memory can be any one of a fifth generation double rate synchronous dynamic random access memory (DDR5 SDRAM) and a fifth generation low power consumption double rate synchronous dynamic random access memory (LPDDR5 SDRAM).

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the invention and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Claims (11)

1. A data read-write method is applied to a dynamic random access memory and is characterized by comprising the following steps:

entering a page read-write mode according to a page read-write mode command, wherein the page read-write mode command is configured through a mode register of the dynamic random access memory;

receiving page read-write commands, wherein the page read-write commands comprise page read-write enabling commands and cross read commands, the page read-write enabling commands are configured through first reserved bits of read-write commands of the dynamic random access memory, the cross read commands are configured through second reserved bits of the read-write commands of the dynamic random access memory, and the cross read commands are used for controlling data to be read and written in a plurality of storage block groups in a cross mode;

According to the page read-write command, executing cross page read-write operation;

the page read-write command also comprises a page read-write length command which is used for indicating the read-write length of each page read-write operation, and the page read-write length command is configured through a burst length bit in the dynamic random access memory read-write command; or, the page read-write command further includes a page read-write length command for indicating the read-write length of each page read-write operation, and the page read-write length command is configured by a burst length bit and a plurality of column address bits in the dynamic random access memory read-write command.

2. The method of claim 1, wherein the column address bits comprise one address bit or two address bits.

3. The data reading and writing method according to claim 2, wherein the DRAM is a fifth generation double data rate synchronous DRAM, wherein,

the burst length bit is a command bit corresponding to the CA5 pin;

the first reserved bit of the read-write command is a command reserved bit corresponding to a CA9 pin, and the second reserved bit of the read-write command is a command reserved bit corresponding to a CA12 pin.

4. The method as claimed in claim 3, wherein the column address bits are corresponding to CA0 pin or CA0 pin and CA1 pin.

5. The method according to claim 1, wherein the page read/write operation is to read/write data of N/16 pages per read/write command, where N is 1 ≦ N ≦ 16, and N is a natural number.

6. The method according to claim 5, wherein N =1, N =2, N =4, or N = 8.

7. A method as claimed in claim 1, wherein the read-write order of the page read-write operation is a linear read-write order.

8. A method for reading and writing data according to claim 1, wherein said page read and write operation can be read and written across pages or without pages.

9. A data reading and writing apparatus, comprising:

the mode register is used for controlling the dynamic random access memory to enter a page read-write mode according to a page read-write mode command;

the command receiving module is connected with the register and used for receiving page read-write commands and transmitting the page read-write commands to the mode register, the page read-write commands comprise page read-write enabling commands and cross read commands, the page read-write enabling commands are configured through first reserved bits of the read-write commands of the dynamic random access memory, the cross read commands are configured through second reserved bits of the read-write commands of the dynamic random access memory, and the cross read commands are used for controlling cross read-write data in a plurality of storage block groups;

The addressing module is connected with the command receiving module and the mode register and is used for cross-selecting storage addresses in a plurality of storage blocks according to the page read-write command;

the page read-write command also comprises a page read-write length command which is used for indicating the read-write length of each page read-write operation, and the page read-write length command is configured through a burst length bit in the dynamic random access memory read-write command; or, the page read-write command further includes a page read-write length command for indicating the read-write length of each page read-write operation, and the page read-write length command is configured by a burst length bit and a plurality of column address bits in the dynamic random access memory read-write command.

10. A data writing and reading apparatus according to claim 9, further comprising:

and the selection module is connected with the addressing module and is used for outputting the read-write addresses in the plurality of storage block groups in a crossed manner according to the crossed read command.

11. A dynamic random access memory comprising the data reading and writing apparatus according to claim 9 or 10.

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