CN111240921A - Method, equipment and readable medium for DUT function verification - Google Patents
Method, equipment and readable medium for DUT function verification Download PDFInfo
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Abstract
The invention discloses a method for verifying DUT function, which comprises the following steps: reading and analyzing the data packet to obtain a first data frame, and generating a first excitation signal based on the first data frame; sending the first excitation signal to a message processing module of the DUT, and receiving a first output message which is processed and sent by the DUT on the first excitation signal; and comparing the first output message with the reference output message, and determining that the DUT message processing function is normal in response to the first output message being consistent with the reference output message. The invention also discloses a computer device and a readable storage medium. The invention provides a multi-level excitation signal interface, which is convenient for monitoring and verifying the DUT output by layers and modules of the DUT, realizes quick fault positioning, compares data in time, reduces the storage requirement of files, improves the storage requirement of the files, and can realize the function verification of the DUT by large data volume.
Description
Technical Field
The present invention relates to the field of storage technologies, and in particular, to a method, device, and readable medium for DUT function verification.
Background
The development of the existing accelerating system applies a general FPGA development flow, the investment in system simulation is less, the problems possibly existing in the design are found and solved mainly by means of unit simulation and upper board debugging of key modules, the time required for comprehensively verifying the system design is longer, and the rapid positioning and the problem solving are not facilitated.
In the existing development process, a simplified simulation verification technology is generally used, a board-loading test is started only by finishing the workload equivalent to unit simulation, the problem to be solved by simulation verification is left to the board-loading test stage, and in order to solve the found problem, higher cost is actually spent.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a method, device and readable medium for DUT function verification
In view of the above, an aspect of the embodiments of the present invention provides a method for DUT function verification, including the following steps: reading and analyzing the data packet to obtain a first data frame, and generating a first excitation signal based on the first data frame; sending the first excitation signal to a message processing module of the DUT, and receiving a first output message which is processed by the DUT and returned by the DUT; and comparing the first output message with the reference output message, and determining that the DUT message processing function is normal in response to the first output message being consistent with the reference output message.
In some embodiments, the benchmark output message is obtained based on the steps comprising: repackaging the first data frame based on a defined format of a functional reference model of the DUT; and processing the first data frame to obtain a reference output message.
In some embodiments, reading and parsing the data packet to obtain the first data frame comprises: reading and analyzing the data packet to obtain a third data frame, generating a third excitation signal based on the third data frame, and sending the third excitation signal to the DUT; performing message analysis on the third data frame to obtain a second data frame, generating a second excitation signal based on the second data frame, and sending the second excitation signal to the DUT; and decoding the second data frame to obtain the first data frame.
In some embodiments, further comprising: receiving a second output message which is processed by the DUT on the second excitation signal and returned; and comparing the second output message with the reference output message, and responding to the second output message and the reference output message to further determine that the DUT decoding function is normal.
In some embodiments, further comprising: receiving an encapsulation output message which is processed and returned by the DUT on the third excitation signal; and comparing the third output message with the reference output message, and responding to the third output message being consistent with the reference output message, and further determining that the DUT message analysis function is normal.
In some embodiments, the DUT further comprises: a message processing module of the DUT receives a first excitation signal to obtain a first data frame; the first data frame is processed and a first output message is generated.
In some embodiments, the DUT further comprises: a message deframing module of the DUT receives the second excitation signal to obtain a second data frame, and deframes the second data frame to obtain a first data frame; and the message processing module processes the first data frame to obtain a second output message.
In some embodiments, the DUT further comprises: the MAC layer processing module of the DUT receives the third excitation signal to obtain a third data frame; the protocol analysis module analyzes the third data frame to obtain a second data frame; the message deframing module deframes the second data frame to obtain a first data frame; and the message processing module processes the first data frame and encapsulates the first data frame to obtain an encapsulated output message.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to implement the method steps as above.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: by providing a multi-level excitation signal interface, the DUT output can be monitored and verified in a layered and modular manner, rapid fault location is realized, data comparison is timely performed, the storage requirement of files is reduced, and the function verification of a large amount of data on the DUT can be realized.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of a method of DUT functional verification provided by the present invention;
fig. 2 is a connection block diagram of a DUT function verification system according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above objects, a first aspect of embodiments of the present invention proposes an embodiment of a method for DUT functional verification. FIG. 1 is a schematic diagram illustrating an embodiment of a method for DUT functional verification provided by the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
s1, reading and analyzing the data packet to obtain a first data frame, and generating a first excitation signal based on the first data frame;
s2, sending the first excitation signal to a message processing module of the DUT, and receiving a first output message sent by the DUT after processing the first excitation signal; and
and S3, comparing the first output message with the reference output message, and determining that the DUT message processing function is normal in response to the first output message being consistent with the reference output message.
In some embodiments of the invention, the DUT is an FPGA on a hardware accelerator card. The market information issuing system for stock exchange generally comprises a DCS (data center server), a DDS (data distribution server), a DRS (data reconstruction server), a VDE (data interface program of market information issuing system), and a VSS (information entropy access system), information issued from the VDE to the VSS is communicated with a TCP protocol, and a data format is encapsulated by a STEP protocol (stock exchange protocol). Except system messages such as login and logout, other service data are basically embedded into the STEP messages in the form of STEP RawData through tag96, market data are encoded in a FAST format, other service data formats are defined by related services, and a market publishing system only performs STEP format encapsulation and forwarding. Because the market data is compressed and encoded by using the FAST protocol, the market data needs to be decoded before being used by an end user, and in order to reduce the time overhead of the user and reduce the time delay, a hardware accelerator card is generally arranged at the VSS and the decoded data is sent to the user. The core chip FPGA on the hardware accelerator card is particularly important, the invention can efficiently solve the problems of functionality and logicality in chip design, avoid the interference of timing sequence and environmental problems in upper board test, and present a working interface which highly imitates the real environment and deeply explores internal logic signals for designers. The output of the reference model is automatically compared, the alarm information is given out when the problem is found, and the waste of simulation time is avoided.
In some embodiments of the present invention, the data packet pcap is read and parsed to obtain a first data frame, where the first data frame is a valid field and a market update instruction, and a first excitation signal is generated based on the first data frame and sent to a message processing module of the DUT through the sequential logic interface; a message processing module of the DUT receives the first excitation signal to obtain a first data frame, and processes the first data frame to obtain a first output message; the verification module compares the first output message with a reference output message, and in response to the first output message being consistent with the reference output message, the message processing function of the DUT is normal. In response to the first output message not being consistent with the baseline output message, a message handling function of the DUT is abnormal.
In some embodiments of the invention, the verification module is connected to the stimulus signal interface of the sequential logic, compares the message frame or encapsulated message output by the DUT with the reference output message, and counts the functional coverage. Meanwhile, a socket interface of a system library function is called, a message frame or an encapsulation message output by the DUT is sent to software of the client, so that the collaborative simulation of the DUT design and the system software can be realized, the simulation strength of the system is further enhanced before the upper board test, and the system client software can be debugged in advance.
In some embodiments of the present invention, the code corresponding to the implementation of the method may be implemented by C language, and is called through a DPI interface of systeverilog.
In some embodiments of the invention, the benchmark output message is obtained based on the following steps, including: repackaging the first data frame based on a defined format of a functional reference model of the DUT; and processing the first data frame to obtain a reference output message.
In some embodiments of the present invention, reading and parsing the data packet to obtain the first data frame comprises: reading and analyzing the data packet to obtain a third data frame, generating a third excitation signal based on the third data frame, and sending the third excitation signal to the DUT; performing message analysis on the third data frame to obtain a second data frame, generating a second excitation signal based on the second data frame, and sending the second excitation signal to the DUT; and decoding the second data frame to obtain the first data frame.
In some embodiments of the invention, further comprising: receiving a second output message which is processed by the DUT on the second excitation signal and returned; and comparing the second output message with the reference output message, and responding to the second output message and the reference output message to further determine that the DUT decoding function is normal.
In some embodiments of the invention, further comprising: receiving an encapsulation output message which is processed and returned by the DUT on the third excitation signal; and comparing the third output message with the reference output message, and responding to the third output message being consistent with the reference output message, and further determining that the DUT message analysis function is normal.
In some embodiments of the present invention, the DUT further comprises: a message processing module of the DUT receives a first excitation signal to obtain a first data frame; the first data frame is processed and a first output message is generated.
In some embodiments of the present invention, the DUT further comprises: a message deframing module of the DUT receives the second excitation signal to obtain a second data frame, and deframes the second data frame to obtain a first data frame; and the message processing module processes the first data frame to obtain a second output message.
In some embodiments of the invention, the DUT further comprises: the MAC layer processing module of the DUT receives the third excitation signal to obtain a third data frame; the protocol analysis module analyzes the third data frame to obtain a second data frame; the message deframing module deframes the second data frame to obtain a first data frame; and the message processing module processes the first data frame and encapsulates the first data frame to obtain an encapsulated output message.
Fig. 2 is a connection block diagram of the DUT function verification system provided by the present invention. As shown in fig. 2, the DUT function verification system includes:
an excitation signal generation module M10 configured to read and parse the data packet pcap into a first data frame z1And based on the first data frame z1Generating a first excitation signal j1The first stimulus signal is transmitted to the message processing module M20 of the DUT, and the first stimulus signal j is received by the message processing module M20 of the DUT1Obtaining a first data frame z1And for the first data frame z1Processing to obtain a first output message o1A verification module M30, receiving the first output message o1And sends the first output message o1And a reference output message o0By comparison, in response to the first output message o1And a reference output message o0Agree withThe message processing function of the DUT is normal.
Also included is a DUT functional reference model module M40 configured to reference the first data frame z based on a defined format of the DUT functional reference model1Repackaging; for the first data frame z1Processing and obtaining a reference output message o0。
The excitation signal generation module M10 comprises M11, M12 and M13, wherein M13 reads and parses the data packet pcap to obtain a third data frame z3And a third data frame z3Sent to M12, M12 for the third data frame z3Analyzing the message to obtain a second data frame z2And a second data frame z2Sent to M11, M11 for the second data frame z2Decoding to obtain a first data frame z1And the first data frame z1To the DUT functional reference model module M40.
M13 reads and parses the packet pcap to obtain a third data frame z3And a third data frame z3Sent to M12, M12 for the third data frame z3Analyzing the message to obtain a second data frame z2Based on the second data frame z2Generating a second excitation signal j2And a second excitation signal j2The message deframing module D21 for sending to the DUT, the message deframing module D21 receives the second excitation signal j2Obtaining a second data frame z2And for the second data frame z2Performing de-framing to obtain a first data frame z1(ii) a And the first data frame z1Sent to the message processing module D20, the message processing module D20 processes the first data frame z1Is processed to obtain a second output message o2And a second output message o2To the authentication module M30. The authentication module M30 sends a second output message o2And a reference output message o0By comparison, in response to the second output message o2And a reference output message o0And if the data is consistent with the data, further determining that the unframing function of the DUT is normal.
M13 reads and parses the packet pcap to obtain a third data frame z3Based on the third data frame z3Generating a third excitation signal j3And will be firstThree excitation signals j3The MAC layer processing module D22 sending to the DUT, the MAC layer processing module D22 receiving the third excitation signal j3To obtain a third data frame z3The parsing protocol module D23 processes the third data frame z3Analyzing the message to obtain a second data frame z2And will send to the message de-framing module D21, the message de-framing module D21 receives the second data frame z2And for the second data frame z2Deframing to obtain a first data frame z1(ii) a And the first data frame z1Sent to the message processing module D20, the message processing module D20 processes the first data frame z1Processed and encapsulated by a protocol framing module D24 and a MAC layer processing module D22 to obtain an encapsulated output message o3(ii) a And will encapsulate the outgoing message o3To the authentication module M30. The authentication module M30 will encapsulate the outgoing message o3And a reference output message o0By contrast, in response to encapsulating the output message o3And a reference output message o0And if the data is consistent with the data, further determining that the DUT message analysis function is normal.
It should be particularly noted that, the steps in the embodiments of the method for verifying DUT function described above can be mutually intersected, replaced, added, or deleted, so that these methods for verifying DUT function with reasonable permutation and combination conversion also belong to the scope of the present invention, and should not limit the scope of the present invention to the embodiments.
In view of the above object, in another aspect of the embodiments of the present invention, a computer device is provided, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to implement the method steps as above.
The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for DUT function verification can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
Furthermore, the methods disclosed according to embodiments of the present invention may also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. Which when executed by a processor performs the above-described functions defined in the methods disclosed in embodiments of the invention.
Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.
The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method of DUT functional verification, comprising the steps of:
reading and analyzing a data packet to obtain a first data frame, and generating a first excitation signal based on the first data frame;
sending the first excitation signal to a message processing module of a DUT, and receiving a first output message which is processed and returned by the DUT on the first excitation signal; and
and comparing the first output message with a reference output message, and determining that the DUT message processing function is normal in response to the first output message being consistent with the reference output message.
2. The method of claim 1, wherein the benchmark output message is obtained based on the steps comprising:
repackaging the first data frame based on a defined format of a functional reference model of the DUT;
and processing the first data frame to obtain the reference output message.
3. The method of claim 1, wherein reading and parsing the data packet to obtain the first data frame comprises:
reading and analyzing a data packet to obtain a third data frame, generating a third excitation signal based on the third data frame, and sending the third excitation signal to the DUT;
performing message analysis on the third data frame to obtain a second data frame, generating a second excitation signal based on the second data frame, and sending the second excitation signal to the DUT;
and decoding the second data frame to obtain a first data frame.
4. The method of claim 3, further comprising:
receiving a second output message processed and returned by the DUT on the second excitation signal;
and comparing the second output message with a reference output message, and responding to the second output message and the reference output message in a consistent manner to further determine that the DUT de-framing function is normal.
5. The method of claim 3, further comprising:
receiving a package output message processed and returned by the DUT on the third excitation signal;
and comparing the third output message with a reference output message, and responding to the third output message and the reference output message being consistent, and further determining that the DUT message analysis function is normal.
6. The method of claim 1, wherein the processing of the first stimulus signal by the DUT further comprises:
a message processing module of the DUT receives the first excitation signal to obtain the first data frame;
processing the first data frame and generating the first output message.
7. The method of claim 4, wherein the processing of the second stimulus signal by the DUT further comprises:
a message deframing module of the DUT receives the second excitation signal to obtain the second data frame, and deframes the second data frame to obtain the first data frame;
and the message processing module processes the first data frame to obtain the second output message.
8. The method of claim 5, wherein the processing of the third stimulus signal by the DUT further comprises:
a MAC layer processing module of the DUT receives the third excitation signal to obtain a third data frame;
the protocol analysis module analyzes the third data frame to obtain the second data frame;
the message deframing module deframes the second data frame to obtain the first data frame;
and the message processing module processes the first data frame and encapsulates the first data frame to obtain the encapsulated output message.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of any of the methods 1-8.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 8.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113760761A (en) * | 2021-09-07 | 2021-12-07 | 上海金仕达软件科技有限公司 | Automatic testing method and device based on software and hardware stock market system |
| CN118012686A (en) * | 2024-04-10 | 2024-05-10 | 沐曦科技(北京)有限公司 | Chip verification system |
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2020
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113760761A (en) * | 2021-09-07 | 2021-12-07 | 上海金仕达软件科技有限公司 | Automatic testing method and device based on software and hardware stock market system |
| CN118012686A (en) * | 2024-04-10 | 2024-05-10 | 沐曦科技(北京)有限公司 | Chip verification system |
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