CN111240459A - System-on-chip power consumption management method, computer device and computer readable storage medium - Google Patents
System-on-chip power consumption management method, computer device and computer readable storage medium Download PDFInfo
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Abstract
The invention provides a power consumption management method of a system on chip, a computer device and a computer readable storage medium, wherein the method comprises the following steps of dividing more than two power utilization modules into a power domain: when each power utilization module enters an idle state, acquiring an idle state running time length set by the power utilization module, and if the idle state running time length is greater than an entry time threshold of a primary power saving mode, entering the primary power saving mode by the power utilization module; and calculating the remaining time length of the power utilization module in the idle state, and comparing the remaining time length with the entry time threshold of the deep power saving mode, wherein if the remaining time length is greater than the entry time threshold of the deep power saving mode, the power utilization module enters the deep power saving mode. The invention also provides a computer device and a computer readable storage medium for realizing the method. The invention can reduce the power consumption of the electronic equipment.
Description
Technical Field
The invention relates to the technical field of power management of a system on chip, in particular to a power consumption management method of the system on chip, a computer device for realizing the method and a computer readable storage medium.
Background
Electronic devices such as smart phones, tablet computers, set-top boxes, automobile data recorders, and the like are common electronic devices. In general, with the miniaturization of electronic devices, many electronic devices start to use a system on chip, which generally includes a plurality of modules, for example, modules including a CPU (central Processing Unit), a GPU (Graphics Processing Unit), a DDR (double data rate synchronous dynamic random access memory), and the like, and further, if the electronic devices also have image capturing and image displaying functions, modules such as a Display Engine (DE), a Video Decoding Engine (VDE), a Video Encoding Engine (VEE), and the like are provided.
Because the endurance of the electronic equipment is greatly influenced by more and more electricity consumption of each module of the electronic equipment, people consider to manage the power consumption of each electricity consumption module to reduce the energy consumption of the electronic equipment and prolong the endurance of the electronic equipment.
At present, the following two methods are mainly adopted in a common adaptive power consumption management method for electronic equipment: one mode is a CPU idle mode, which mainly manages power consumption of the CPU, for example, after the electronic device enters an idle state, an operation time of the CPU entering the idle state is set, and the CPU enters different power saving levels according to a preset operation time of entering the idle state. Specifically, a plurality of different power saving levels are preset, and the longer the running time of the CPU entering the idle state is, the deeper the power saving mode of the CPU is, and the more obvious the power saving effect is. When the electronic CPU receives a timing interrupt signal or other interrupt signals, the CPU will quit each power saving level one by one passively and awaken to the running state to perform related interrupt processing. The power management method is only used for power management of the CPU at present, and does not relate to power management of non-CPU modules and power domains of the non-CPU modules of the system on chip.
The other mode is to let the power utilization module passively enter a higher power saving level mode, that is, after the power utilization module enters an idle state, the power utilization module gradually enters a deeper power saving level, but the deeper power saving level is determined according to the fact that the residence time of the power utilization module in a certain power saving level is larger than a certain threshold value, and then the deeper power saving level is entered. For example, the power module needs to stay below the power saving level of the first level for more than 30 seconds before entering the power saving level of the second level. The disadvantage of this method is that the power module needs to stay in the primary power saving state for a sufficient time to enter the deeper power saving level, and the power module does not enter the deeper power saving level as soon as possible, so the power saving effect is not ideal.
Disclosure of Invention
The invention mainly aims to provide a system-on-chip power consumption management method capable of effectively reducing the power consumption of electronic equipment.
Another object of the present invention is to provide a computer apparatus for implementing the above method for managing power consumption of a system on a chip.
It is still another object of the present invention to provide a computer-readable storage medium for implementing the above-mentioned system-on-chip power consumption management method.
In order to achieve the main object of the present invention, the method for managing power consumption of a system on chip provided by the present invention comprises dividing more than two power utilization modules into a power domain: when each power utilization module enters an idle state, acquiring an idle state running time length set by the power utilization module, and if the idle state running time length is greater than an entry time threshold of a primary power saving mode, entering the primary power saving mode by the power utilization module; and calculating the remaining time length of the power utilization module in the idle state, and comparing the remaining time length with the entry time threshold of the deep power saving mode, wherein if the remaining time length is greater than the entry time threshold of the deep power saving mode, the power utilization module enters the deep power saving mode.
According to the scheme, after the plurality of power utilization modules are divided into the same power domain, the power supply of the plurality of power utilization modules can be conveniently managed, and whether each power utilization module enters a deeper power saving mode is not determined by the residence time of the power saving mode of the previous level, but by the remaining running time length in the idle state, so that the long-time running in the lower power saving mode can be avoided, and the power consumption of each power utilization module of the system on chip can be reduced.
In a preferred embodiment, the deep power saving mode has two or more levels; the power utilization module entering the deep power saving mode comprises the following steps: and comparing the remaining time length with the entry time thresholds of the plurality of deep power saving modes, and if the remaining time length is greater than the entry time threshold of a certain deep power saving mode, entering the deep power saving mode of the corresponding level by the power utilization module.
Therefore, the deep power saving modes have a plurality of different levels, and the power utilization module can enter different deep power saving modes according to actual conditions, so that the power utilization module can be prevented from being only resident in the deep power saving mode of one level, and the power consumption of the power utilization module is reduced.
The further scheme is that the power utilization module enters a deep power saving mode of multiple levels from shallow to deep step by step. Therefore, the power utilization module can not enter a high-level deep power saving mode at a time, and the impact on the operation of the power utilization module is avoided.
Further, after the power utilization module enters the deep power saving mode, the following steps are also executed: and comparing the remaining time length with an exit time threshold of the deep power saving mode, and if the remaining time length is smaller than the exit time threshold of the deep power saving mode, exiting the deep power saving mode by the power utilization module.
Therefore, the power utilization module exits from the deep power saving mode by comparing the remaining time length in the idle state with the exit time threshold of each level of deep power saving mode, so that the power utilization module can automatically exit from the deep power saving mode of the corresponding level according to the remaining time length in the idle state, and the power utilization module exits from the deep power saving mode more flexibly.
In a preferred scheme, the power utilization module exits from a deep power saving mode of multiple levels from deep to shallow step by step. Therefore, the power utilization module does not exit from the deep power saving mode at a deep level at a time, and the running stability of the power utilization module is ensured.
Further, after the power utilization module exits the deep power saving mode, the following steps are further performed: and comparing the remaining time length with an exit time threshold of the primary power saving mode, and if the remaining time length is smaller than the exit time threshold of the primary power saving mode, exiting the primary power saving mode by the power utilization module.
Therefore, the fact that the power utilization module exits the primary power saving mode and recovers to the normal working mode is also determined by the remaining time length of the idle state, the power utilization module is prevented from being awakened when the awakening time arrives, and the power utilization module can be ensured to be in the working state when the awakening time arrives.
According to a further scheme, after all power utilization modules in the same power domain enter a deep power saving mode at a preset level, the power of the power domain is turned off, and the power domain enters a power-down state.
Therefore, after all the power utilization modules enter a deeper power saving mode, the power domain can also enter the power saving mode, and therefore the power consumption of the power domain is saved.
In a further aspect, when any power-consuming module in the same power domain exits the deep power-saving mode of the preset level, the power supply in the power domain is powered on.
Therefore, only if any one power utilization module in the power domain exits the deep power saving mode at the preset level, it is indicated that one power utilization module in the power domain needs the power domain to provide electric energy, and the power domain is powered on, so that on one hand, the power domain can be in a power-down state as long as possible, and on the other hand, the operation of the power utilization module cannot be influenced.
In order to achieve the above another object, the present invention provides a computer apparatus including a processor and a memory, wherein the memory stores a computer program, and the computer program implements the steps of the above system-on-chip power consumption management method when executed by the processor.
To achieve the above-mentioned further object, the present invention provides a computer program stored on a computer readable storage medium, wherein the computer program, when executed by a processor, implements the steps of the above-mentioned system-on-chip power consumption management method.
Drawings
FIG. 1 is a block diagram of a power domain design of a system-on-chip to which an embodiment of a method for power management of the system-on-chip of the invention is applied.
FIG. 2 is a first portion of a flow chart of an embodiment of a system-on-chip power management method of the present invention.
FIG. 3 is a second portion of a flowchart of a method for system-on-chip power management according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating a transition of operating modes of a power consuming module according to an embodiment of the power consumption management method of the system on chip.
The invention is further explained with reference to the drawings and the embodiments.
Detailed Description
The power consumption management method of the system on chip is applied to electronic equipment with the system on chip, such as an automobile data recorder, a set top box and the like. Preferably, the electronic device is provided with a processor and a memory, the memory having stored thereon a computer program, and the processor implements the system-on-chip power consumption management method by executing the computer program.
The embodiment of the system-on-chip power consumption management method comprises the following steps:
the embodiment is applied to an electronic device with a system on chip, the system on chip is provided with a CPU, a memory, and the like, and may further be provided with a GPU (Graphics Processing Unit, image processor) and modules such as a Display Engine (DE), a Video Decoding Engine (VDE), and a video coding engine (VEE), and as functions of the electronic device become more and more powerful, power consumption of the modules becomes higher and higher.
Since the power consumption of the modules such as the CPU, the GPU, the display engine, the video decoding engine, and the video encoding engine is large, the power consumption of these modules is mainly managed in the present embodiment, and therefore, the modules are also referred to as power consumption modules. In order to manage a plurality of power utilization modules conveniently, in this embodiment, power domains of the power utilization modules of the system on chip need to be divided, and the power utilization modules depending on the same basic module are divided into the same power domain. The display engine, the video decoding engine and the video coding engine all depend on the iommu basic module, and then the three power utilization modules are all divided into the same power domain.
Meanwhile, the operation mode of the power utilization module needs to be set, for example, the power utilization module can be in a normal operation state, i.e., a non-idle state, and the power utilization module does not enter the power saving mode. Only the power utilization module enters the idle state, then according to specific conditions, the power utilization module can enter different levels of power saving modes, such as a primary power saving mode and a deep power saving mode, and the deep power saving mode can include a plurality of different levels of deep power saving modes, the higher the level of the power saving mode is, the less electric energy the power utilization module consumes under the power saving mode, that is, the more the purpose of power saving can be achieved.
In this embodiment, whether each power consumption module enters or exits the power saving mode of a certain level is determined depending on the remaining time length in the idle state after the power consumption module enters the idle state, and therefore, a wakeup time needs to be set when each power consumption module enters the idle state, and a timer is set at the same time, and is a countdown timer for the remaining time length in the idle state, and once the power consumption module enters the idle state, the timer immediately starts to count down. And gradually quitting the power saving modes of all levels until all the power saving modes are quitted and recovering to a normal running state along with the gradual reduction of the remaining time length of the power utilization module in the idle state.
One idea of this embodiment is that, when all power consuming modules in the same power domain enter a deep power saving mode at a preset level, the power domain is triggered to enter a deeper power saving state, for example, the power of the power domain is turned off, so that the power domain enters a power-down state. When the remaining time length output by the timer of any power utilization module in the power domain meets the preset requirement, the power domain is triggered to exit the power saving mode, and the power domain is powered on.
It should be noted that the operation modes of the electronic device can be divided into a synchronous mode and an asynchronous mode, in the synchronous mode, the power utilization modules periodically enter a normal operation state and an idle state, for example, the display time of each frame of the power utilization modules such as the display engine and the image processor is fixed under the condition of frame rate determination, therefore, the idle time of each display period of the power utilization modules can be predicted, that is, the operation time of each idle state can be determined.
In the asynchronous mode, the time for the power module to enter the normal operation state again is unknown, so the remaining time length after entering the idle state is often uncertain, and the following two cases mainly exist: the first situation is that when the upstream and downstream modules in the system on chip initiate a service request to the power utilization module, the power utilization module enters a normal operation state. In the second case, the power consuming module enters a running state, such as an interface module, when the system-on-chip peripheral device issues a service request to the power consuming module.
Under the asynchronous mode, the power utilization module automatically triggers the state machine to gradually exit from the current power saving mode to a normal operation state. If the asynchronous wake-up time of the power consumption module is too close to the time of entering the idle state, the power consumption module may not achieve the power saving effect. For the duration of the idle stage of the power utilization module in the asynchronous mode, working models of the power utilization module in different working scenes can be summarized through strategies such as data induction, scene analysis, intelligent prediction and the like, and data which are closest to the actual duration of the idle state are obtained. If the asynchronous wake-up time and frequency of the power utilization module are irregular, the power saving effect may not be achieved by adopting the embodiment, and the power utilization module can be forcibly prohibited from entering the power saving mode.
Therefore, a power saving mode enabling register is required to be arranged for each power utilization module and used for storing a control word, the control word is used for controlling whether the power utilization module is started to automatically enter a power saving function, if the function is started, the power utilization module automatically enters a corresponding power saving mode when the condition is met, and if the function is closed, the power utilization module cannot enter the power saving mode.
For each power utilization module, an idle state time length register is needed, and the idle state time length register is used for storing the preset idle state running time length after the power utilization module enters an idle state. As shown in fig. 1, three power utilization modules are arranged under a power domain 0, including a power utilization module 0, a power utilization module 1 and a power utilization module 2, each power utilization module is provided with a plurality of registers, and one of the registers is an idle state time length register.
In this embodiment, the power saving mode of the power consuming module is set to multiple levels, for example, the C0 mode is set to a normal operation state of the power consuming module, that is, a state of not entering the power saving mode, the C1 mode is a primary power saving mode, and the power consuming module enters a Clock gating state at this time, and in the power saving mode of this level, the power of the power consuming module is saved compared with that in the C0 mode. In addition, a plurality of levels of deep Power saving modes are set, including a C2 mode, a C3 'mode and a C3 mode, wherein the C2 mode is a Power gating mode which cannot be converted into the C3 mode, the C3' mode is a Power gating mode which can be converted into the C3 mode, and the C3 mode is a mode in which the Power domain enters the Power gating mode. Therefore, the power consumption of the power utilization modules is reduced in the C2 mode, the C3 'mode and the C3 mode in sequence, namely, the power saving levels of the C2 mode, the C3' mode and the C3 mode are gradually increased.
For this purpose, the register corresponding to each power utilization module further includes a time for storing the time consumed by the process of entering the power utilization module from the C0 mode to the C1 mode, that is, the time consumed for entering the C1 mode (C1 Entry-latency). In addition, there is a register for storing the time consumed by the process of exiting the power utilization module from the C1 mode to the C0 mode, that is, the time consumed by exiting the C1 mode (C1 Exit-latency).
Taking power module 0 as an example, it is necessary to calculate the shortest time that power module 0 resides in the C1 mode to compensate for the energy consumed by entering and exiting the C1 mode through a power consumption model. The power consumption model is as follows: suppose that the energy consumed by the process of the electricity utilization module 0 from the C0 mode to the C1 mode is E01entThe energy consumed by the process of exiting from the C1 mode to the C0 mode is E01extThe power consumption module 0 operates at W in the C0 mode00The operating power in the C1 mode is W01The shortest time for the electricity utilization module to stay in the C1 mode to compensate the energy consumption for entering and exiting the C1 mode is T01resThen, the power consumption model is:
E01ent+E01ext＝(W00-W01)×T01res(formula 1)
The shortest residence time T corresponding to the C1 mode can be calculated according to the formula 101res＝(E01ent+E01ext)/(W00-W01)。
Accordingly, the register corresponding to each power utilization module further includes a time for storing the time consumed by the process of entering the power utilization module from the C1 mode to the C2 mode, that is, the time consumed for entering the C2 mode (C2 Entry-latency). In addition, there is a register for storing the time consumed by the process of exiting the power utilization module from the C2 mode to the C1 mode, that is, the time consumed by exiting the C2 mode (C2 Exit-latency).
In this embodiment, a power consumption model is used to calculate the shortest time that the power consumption module 0 can stay in the C2 mode to compensate for the energy consumption of entering and exiting the C2 mode. The power consumption model is as follows: suppose that the energy consumed by the process of the electricity utilization module 0 from the C1 mode to the C2 mode is E02entThe energy consumed by the process of exiting from the C2 mode to the C1 mode is E02extThe power consumption module 0 operates at W in the C2 mode02The shortest time that the electricity utilization module 0 resides in the C2 mode to compensate for the energy consumed by entering and exiting the C2 mode is T02resThen, the power consumption model is:
E02ent+E02ext＝(W00-W02)×T02res(formula 2)
The shortest residence time T corresponding to the C2 mode can be calculated according to the formula 202res＝(E02ent+E02ext)/(W00-W02)。
In this way, data of the entry time, the exit time, and the shortest residence time in the C1 mode and the C2 mode are stored for each electricity consumption module.
For each power domain, a power management unit is provided, for example, power domain 0 is in power management unit 0, for example, power domain N is in power management unit N, and so on. A plurality of registers are also arranged in the power management unit and used for storing different time thresholds. For example, the setting corresponds to the time consumed by the power-down process of the power domain in the mode C3, i.e., the time consumed by the power-down process (C3 Entry-latency), and corresponds to the time consumed by the power-up process of the power domain in the mode C3, i.e., the time consumed by the power-up process (C3 Exit-latency).
In addition, in the embodiment, a power consumption model is used to calculate the shortest time for the power module to stay in the power-down state of the power domain, which can make up the energy consumption for entering and exiting the power-down state of the power domain, that is, the shortest stay time in the C3 mode. The power consumption model is as follows: suppose the power domain consumes E during the process of entering the C3 mode from the C3' modedentThe energy consumed by the power module 0 to exit from the C3 mode to the C3' mode is EdextThe power of the power module 0 in the C3' mode is Wd0The power of the power module 0 in the C3 mode is Wd1The shortest time that the power consumption module 0 obtained by calculation of the power consumption model is resident in the power-down state of the power domain and can compensate the energy consumed by entering and exiting the power-down state of the power domain is T0dresThen, the power consumption model is:
Edent+Edext＝(W00+Wd0-Wd1)×T0dres(formula 3)
The shortest residence time T corresponding to the C3 mode can be calculated according to the formula 30dres＝(Edent+Edext)/(W00+Wd0-Wd1)。
In addition, for each power utilization module, a corresponding idle state remaining time timer is arranged in the power management unit, and when one power utilization module enters an idle state, the timer acquires the idle state running time length of the power utilization module, takes the idle state running time length as the initial timing value of the timer, and starts to count down.
In this embodiment, a plurality of count values of the timer are set in advance, and table 1 shows various times and signs of the timer.
TABLE 1 symbols for various times and timers
The following describes a conversion process of the power module in a plurality of modes with reference to fig. 2 to 4. First, step S1 is executed to divide the power utilization modules into one power domain, preferably, multiple power domains may be set in the electronic device, and multiple power utilization modules belonging to the same power domain depend on the same basic module.
Then, step S2 is executed to determine whether the power module enters an idle state, if so, step S3 is executed, and if the power module does not enter the idle state, indicating whether the power module is in a normal operation state, the power module does not enter the power saving mode.
If the power utilization module enters an idle state, the power saving mode is gradually entered from shallow to deep, specifically, the primary power saving mode is entered first, then the deep power saving mode with lower grade is entered, and finally the deep power saving mode with higher grade is entered. Specifically, step S3 is executed to obtain the idle-state operation time length set by the power consumption module, that is, the preset idle-state operation time length of the power consumption module is obtained from the register of the power consumption module.
Then, step S4 is executed to determine whether the operation time length of the idle state of the power consumption module is greater than the entering time threshold of the primary power saving mode, if so, step S6 is executed to enter the primary power saving mode from the normal operation state. Referring to fig. 4, if the process of the power utilization module entering the primary power saving mode C1 from the normal operation state C0 is L0, the following conditions are required to be satisfied: t is0setting>T01ent+T01res+T01extWherein, T01ent+T01res+T01extIs the entry time threshold for the primary power saving mode of power module 0.
If the operation time length of the idle state of the power consumption module is less than the entering time threshold of the primary power saving mode, step S5 is executed, and the power consumption module maintains the normal operation state, i.e. does not enter the power saving mode. If the operation time length of the idle state of the power utilization module is greater than the entering time threshold of the primary power saving mode, step S6 is executed, and the power utilization module enters the primary power saving mode from the C0 mode, i.e. the C1 mode, at which time T is required to be set0settingIs loaded to t0idleNamely, the running time length of the power utilization module in the idle mode is used as the initial timing value of the idle state remaining time timer, and the idle state remaining time timer starts to count down.
Then, step S7 is executed, the remaining operation time length of the power module in the idle state needs to be calculated as the idle state remaining time timer keeps counting, and step S8 is executed to determine whether the remaining operation time is greater than the entering time threshold of a certain deep power saving mode. In this embodiment, the power module enters the deep power saving mode of each level from shallow to deep, for example, the deep power saving mode C2 of the lower level is entered from the primary power saving mode C1, i.e., the L2 process in fig. 4.
Specifically, the condition that the electricity utilization module enters the C2 mode from the C1 mode needs to be satisfied is that: t is t0idle>(E01ent+E01ext)/(W00-W02)+T01ext+T02ent+T02res+T02extWherein (E)01ent+E01ext)/(W00-W02)+T01ext+T02ent+T02res+T02extIs the entry time threshold for power module 0 corresponding to the C2 mode.
If the remaining operation time of the power consumption module in the idle state is less than the entry time threshold of a certain deep power saving mode, step S9 is executed to maintain the power saving mode at the current state, i.e. not enter the power saving mode of a deeper level, and if the remaining operation time of the power consumption module in the idle state is greater than the entry time threshold of a certain deep power saving mode, step S10 is executed to enter the corresponding deep power saving mode, e.g. enter the C2 mode.
Accordingly, the conditions that the power utilization module needs to enter the C3' mode (L4 process) from the deep power saving mode C2 are as follows: t is t0idle>(E01ent+E01ext)/(W00+Wd0-Wd1)+T01ext+(E02ent+E02ext)/(W00+Wd0-Wd1)+T02ext+Tdent+T0dres+TdextWherein (E)01ent+E01ext)/(W00-W02)+T01ext+T02ent+T02res+T02extIs the entry time threshold for power module 0 corresponding to the C3' mode.
If all the power modules in the same power domain enter the deeper deep power saving mode, the power domain may also enter the power saving mode to save electric energy, and therefore, step S11 needs to be executed to determine whether all the power modules in the same power domain enter the deep power saving mode at the preset level. If all the power utilization modules enter the C3 'mode, the power domain enters the power saving mode, at this time, step S12 is executed, the power of the power domain is turned off, the power domain is in a power-down state, at this time, all the power utilization devices in the power domain enter a higher power saving mode, i.e., the C3 mode, from the C3' mode, and this process is the L7 process.
With the running time of the power utilization module in the idle state not being short, the power utilization module needs to exit the power saving modes of each level step by step, and firstly, the power domain needs to exit the power-down state, that is, the power domain needs to be powered on. Therefore, step S13 needs to be executed to determine whether the preset power domain power-on condition is satisfied, if yes, the power domain exits the power-down state, and as shown in fig. 4, the power utilization module can directly exit from the C3 mode to the C2 mode, i.e., the L8 process.
For the L8 process, assuming that the first power module 0 in the power domain to trigger this transition, the following condition is satisfied: t is t0idle<＝T01ext+T02ext+TdextWherein T is01ext+T02ext+TdextPower module 0 corresponds to the exit time threshold of the C3 mode. If the above condition is satisfied, the power domain is powered on, and the power module 0 is switched from the C3 mode to the C2 mode. It can be seen that one condition for power domain power-up is that the remaining run-time length of any powered module in the idle state is less than the exit time threshold of the C3 mode. It can be seen that if the power domain meets the preset power-on condition, step S14 is executed to power onThe source domain is powered up, and the corresponding power utilization module converts the C3 mode into the C2 mode.
The powered module may also exit from the C3 mode to the C3' mode, i.e., the L6 process. Suppose that other power utilization modules do not satisfy the condition of the L8 process in the same power domain, e.g., the power utilization module 1 does not satisfy t1idle<＝T11ext+T12ext+TdextHowever, when the power domain is powered on, other power modules in the same power domain will be switched from the C3 mode to the C3' mode.
After the power module is powered on the power domain, step S15 is executed to determine whether the remaining time length of the power module in the idle state is less than the exit time threshold of the deep power saving mode of a certain level, if not, the power module continues to wait and maintain the current deep power saving mode, and if the remaining time length of the power module in the idle state is less than the exit time of the deep power saving mode of a certain level, step S16 is executed to enable the power module to exit the deep power saving mode of a corresponding level.
For example, if the other power utilization modules in the power domain, such as the power utilization module 1 or the power utilization module 2, respectively satisfy the condition of the L8 procedure, the power utilization module correspondingly exits from the C3' mode to the C2 mode, i.e., the L5 procedure. It can be seen that when the remaining time length of the power module 1 or the power module 2 in the idle state is less than the exit time threshold of the C3 mode, the power module exits the C3' mode and returns to the C2 mode.
As another example, if power module 0 is in C2 mode, the condition for exiting C2 mode is t0idle<＝T01ext+T02extWherein T is01ext+T02extIs the exit time threshold for the power module 0 for the C2 mode, if the above conditions are met, the power module 0 exits from the C2 mode to the C1 mode, i.e., the L3 process.
As the operation time of the power utilization module in the idle state continues to decrease, step S17 is executed to determine whether the remaining time length in the idle state is less than the exit time threshold of the primary power saving mode, i.e. t0idle<＝T01extWherein T is01extFor the exit time threshold of power module 0 for primary power saving mode C1, if the above bar is satisfiedIf yes, the power utilization module 0 executes the step S18 to exit from the C1 mode to the C0 mode, i.e., the L1 process, i.e., the normal operation state is returned, and the counting value T of the idle state remaining time timer is counted0settingAnd clearing, and stopping the countdown operation by the idle state remaining time timer.
Of course, if the power consumption module is asynchronously awakened, the state machine is triggered to be switched by clearing the timing value of the idle state remaining time timer of the power consumption module, so that the state machine is gradually quitted from the current deepest power consumption level to the normal operation state.
As mentioned above, if the asynchronous wake-up time and frequency of the power consumption module are irregular, the power saving effect may not be achieved by using the present embodiment, and the power consumption module may be forcibly prohibited from entering the power saving mode, specifically, if the residence time of the power consumption module 0 in the idle state is mostly less than T01ent+T01res+T01extThat is, the entry time is smaller than the entry time threshold of the primary power saving mode, the power utilization module 0 may be forcibly prohibited from entering the power saving modes of each stage in this embodiment.
This embodiment is through constantly getting into deeper level's power saving mode or withdraw from each level's power saving mode gradually with the electric module remaining time length under idle state to realize reducing the purpose of power consumption module consumption, avoid the power consumption module to need can get into higher level's power saving mode after long-time residing under lower level's power saving mode, the power saving effect is better.
The embodiment of the computer device comprises:
the computer apparatus of this embodiment may be an electronic device, and the computer apparatus includes a processor, a memory, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the computer apparatus implements the steps of the above-mentioned system-on-chip power consumption management method.
For example, a computer program may be partitioned into one or more modules that are stored in a memory and executed by a processor to implement the modules of the present invention. One or more of the modules may be a series of computer program instruction segments capable of performing certain functions, which are used to describe the execution of the computer program in the terminal device.
The Processor may be a Central Processing Unit (CPU), or may be other general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, a discrete hardware component, or the like. The general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor being the control center of the terminal device and connecting the various parts of the entire terminal device using various interfaces and lines.
The memory may be used to store computer programs and/or modules, and the processor may implement various functions of the terminal device by running or executing the computer programs and/or modules stored in the memory and invoking data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. In addition, the memory may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
A computer-readable storage medium:
the computer program stored in the computer device may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, all or part of the flow in the method according to the above embodiments may also be implemented by a computer program, which may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of the above system-on-chip power consumption management method.
Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, U.S. disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution media, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, in accordance with legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunications signals.
Finally, it should be emphasized that the present invention is not limited to the above-described embodiments, such as the change of the time length of the setting of each time threshold, or the change of the power saving mode level, and such changes should be included in the protection scope of the claims of the present invention.
Claims (10)
1. The method for managing the power consumption of the system on chip is characterized by comprising the following steps:
more than two power utilization modules are divided into a power domain:
when each power utilization module enters an idle state, acquiring an idle state running time length set by the power utilization module, and if the idle state running time length is larger than an entry time threshold of a primary power saving mode, the power utilization module enters the primary power saving mode;
calculating the remaining time length of the power utilization module in an idle state, and comparing the remaining time length with an entry time threshold of a deep power saving mode, wherein if the remaining time length is greater than the entry time threshold of the deep power saving mode, the power utilization module enters the deep power saving mode.
2. The system-on-chip power consumption management method according to claim 1, characterized in that:
the deep power saving mode has more than two levels;
the power utilization module entering a deep power saving mode comprises: and comparing the remaining time length with the entry time thresholds of a plurality of deep power saving modes, wherein if the remaining time length is greater than the entry time threshold of one deep power saving mode, the power utilization module enters the deep power saving mode of the corresponding level.
3. The system-on-chip power consumption management method according to claim 2, characterized in that:
the power utilization module enters the deep power saving modes of multiple levels from shallow to deep step by step.
4. The system-on-chip power consumption management method according to claim 2, characterized in that:
after the power utilization module enters a deep power saving mode, the following steps are also executed:
and comparing the remaining time length with an exit time threshold of the deep power saving mode, and if the remaining time length is smaller than the exit time threshold of the deep power saving mode, the power utilization module exits the deep power saving mode.
5. The system-on-chip power consumption management method according to claim 4, wherein:
the power utilization module exits the deep power saving modes of multiple levels step by step from deep to shallow.
6. The system-on-chip power consumption management method according to claim 4, wherein:
after the power utilization module exits the deep power saving mode, the following steps are also executed:
comparing the remaining time length with an exit time threshold of a primary power saving mode, and if the remaining time length is less than the exit time threshold of the primary power saving mode, the power utilization module exits the primary power saving mode.
7. The system-on-chip power consumption management method according to any one of claims 1 to 6, characterized by:
and after all the power utilization modules in the same power domain enter a deep power saving mode at a preset level, the power of the power domain is turned off, and the power domain enters a power-down state.
8. The system-on-chip power consumption management method of claim 7, wherein:
and when any power utilization module in the same power domain exits the deep power saving mode at the preset level, the power supply of the power domain is powered on.
9. Computer arrangement, characterized in that it comprises a processor and a memory, said memory storing a computer program that, when executed by the processor, performs the steps of the system-on-chip power consumption management method according to any of claims 1 to 8.
10. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program when executed by a processor implementing the steps of the system-on-chip power consumption management method according to any of claims 1 to 8.
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