CN111230350A - Method for testing chip solderability - Google Patents
Method for testing chip solderability Download PDFInfo
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- CN111230350A CN111230350A CN201811434057.7A CN201811434057A CN111230350A CN 111230350 A CN111230350 A CN 111230350A CN 201811434057 A CN201811434057 A CN 201811434057A CN 111230350 A CN111230350 A CN 111230350A
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- chip
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K31/00—Processes relevant to this subclass, specially adapted for particular articles or purposes, but not covered by only one of the preceding main groups
- B23K31/12—Processes relevant to this subclass, specially adapted for particular articles or purposes, but not covered by only one of the preceding main groups relating to investigating the properties, e.g. the weldability, of materials
Abstract
The application relates to the technical field of component solderability test, in particular to a chip solderability test method, which comprises the following steps: printing solder paste on the ceramic substrate; placing the welding end of the chip to be tested on the solder paste to form a substrate to be welded; performing reflow soldering treatment on the substrate to be soldered so that the chip to be soldered is soldered on the ceramic substrate; removing the chip to be tested from the ceramic substrate; and detecting the state of the solder paste on the welding end of the chip to be detected so as to determine the weldability of the chip to be detected. The test method can reduce the influence on the chip to be tested in the test process, improve the test accuracy and reduce the test difficulty and the test cost.
Description
Technical Field
The application relates to the technical field of component solderability testing, in particular to a testing method for chip solderability.
Background
In the assembly welding process of electronic products, the welding quality directly affects the quality of packaged products. Therefore, in order to improve the soldering quality, in addition to strict control of process parameters, scientific solderability testing of chips is required.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present application and therefore may include information that does not constitute prior art known to a person of ordinary skill in the art.
Disclosure of Invention
The application aims to provide a method for testing the weldability of a chip, which can reduce the influence on the chip to be tested in the testing process, improve the testing accuracy and reduce the testing difficulty and the testing cost.
The application provides a testing method for chip solderability in a first aspect, which comprises the following steps:
printing solder paste on the ceramic substrate;
placing the welding end of the chip to be tested on the solder paste to form a substrate to be welded;
performing reflow soldering treatment on the substrate to be soldered so that the chip to be soldered is soldered on the ceramic substrate;
removing the chip to be tested from the ceramic substrate;
and detecting the state of the solder paste on the welding end of the chip to be detected so as to determine the weldability of the chip to be detected.
In one exemplary embodiment of the present application, the solder paste includes solder and flux,
the detecting the state of the solder paste on the welding end of the chip to be detected so as to determine the weldability of the chip to be detected comprises the following steps:
confirming whether the soldering flux remains on the soldering terminal of the chip to be tested;
removing the soldering flux when the residual soldering flux is confirmed on the soldering terminal of the chip to be tested;
and detecting the state of tin solder on the welding end of the chip to be detected so as to determine the weldability of the chip to be detected.
In an exemplary embodiment of the present application, the detecting a state of solder on a bonding terminal of the chip to be tested to determine solderability of the chip to be tested includes:
detecting whether the coverage rate of the tin solder on the welding end exceeds a first preset value and detecting whether tin balls with the diameter larger than or equal to a second preset value exist on the welding end of the chip to be detected;
when the fact that the coverage rate of the tin solder on the welding end exceeds the first preset value and no tin bead with the diameter larger than or equal to the second preset value exists on the welding end is detected, the fact that the weldability of the chip to be tested passes a test standard is determined;
and when the coverage rate of the tin solder on the welding end is detected to be less than or equal to the first preset value and/or the welding end is detected to have tin beads with the diameter exceeding the second preset value, determining that the weldability of the chip to be tested does not pass the test standard.
In an exemplary embodiment of the present application, while detecting a state of solder on a bonding terminal of the chip to be tested to determine solderability of the chip to be tested, the testing method further includes:
and detecting whether the ceramic substrate has tin beads with the diameter larger than or equal to the second preset value or not so as to determine the weldability of the chip to be detected.
In an exemplary embodiment of the present application, the first preset value is 0.95, and the second preset value is 0.13 mm.
In an exemplary embodiment of the present application, after printing solder paste on a ceramic substrate and before placing a bonding terminal of a chip to be tested on the solder paste to form a substrate to be bonded, the testing method further includes;
detecting whether the shape and the size of the solder paste printed on the ceramic substrate are consistent with the shape and the size of the welding end of the chip to be detected,
and when the shape and the size of the solder paste are consistent with those of the welding ends, the step of placing the welding ends of the chip to be tested on the solder paste to form the substrate to be welded is executed.
In an exemplary embodiment of the present application, the placing the bonding end of the chip to be tested on the solder paste includes:
and superposing the welding end of the chip to be tested and the solder paste in the thickness direction of the ceramic substrate.
In an exemplary embodiment of the present application, the performing a reflow soldering process on the substrate to be soldered to solder the chip to be soldered on the ceramic substrate includes:
and placing the substrate to be welded in a reflow soldering furnace to sequentially perform preheating treatment, reflow treatment and cooling treatment so as to weld the chip to be tested on the ceramic substrate.
In one exemplary embodiment of the present application, the solder paste is a lead-free solder paste.
In an exemplary embodiment of the present application, the preheating process includes preheating the substrate to be welded at a temperature of 150 ℃ to 180 ℃;
the reflow treatment comprises reflowing the substrates to be welded at a temperature of 230 ℃ to 250 ℃.
In an exemplary embodiment of the present application, before placing the bonding end of the chip to be tested on the solder paste to form the substrate to be bonded, the testing method further includes:
and carrying out steam aging treatment on the chip to be tested.
In an exemplary embodiment of the present application, the water in the steam aging process is distilled water or deionized water.
In an exemplary embodiment of the present application, the ceramic substrate is provided with a temperature measuring hole, and a temperature measuring joint of a temperature measuring element is placed in the temperature measuring hole.
In an exemplary embodiment of the present application, the temperature measuring hole is located at a central region of the ceramic substrate.
In an exemplary embodiment of this application, ceramic substrate is the rectangle, four bights of ceramic substrate are provided with the location identification structure respectively, the location identification structure is used for the location the tin cream with position and location between the ceramic substrate the tin cream with the position between the bonding terminal of the chip that awaits measuring.
In an exemplary embodiment of the present application, the positioning mark structure is a positioning hole, a positioning groove or a positioning patch adhered to the surface layer of the ceramic substrate.
In an exemplary embodiment of the present application, the positioning indication structure is a circle or a cross.
In an exemplary embodiment of the present application, the chip to be tested is a ball grid array package chip.
The technical scheme provided by the application can achieve the following beneficial effects:
the application provides a chip solderability's test method, through using ceramic substrate as with the chip welded carrier that awaits measuring, can reduce the condition that the tin cream takes place the bonding with the carrier in reflow soldering processing procedure to the chip that awaits measuring is dismantled from ceramic substrate, thereby is convenient for detect the state of tin cream on the welding end of the chip that awaits measuring, with the solderability of confirming the chip that awaits measuring, thereby has improved the degree of accuracy of chip solderability test. According to the test method, the X-ray is not needed for detection, so that the influence on the chip to be tested in the test process can be reduced, the damage probability of the chip to be tested is reduced, the test difficulty is reduced, and in addition, the ceramic substrate can be repeatedly used in the test process, and the test cost is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a flowchart of a method for testing the solderability of a chip according to an embodiment of the present application;
FIG. 2 is a flowchart of step S50 in the embodiment of the present application;
FIG. 3 is a schematic plan view of a ceramic substrate according to an embodiment of the present disclosure;
fig. 4 is a schematic view after completion of step S10;
fig. 5 is a schematic plan view of a chip to be tested according to an embodiment of the present application;
fig. 6 is a schematic view after completion of step S20;
description of reference numerals:
in fig. 3 to 6:
1. a ceramic substrate; 10. positioning the identification structure; 11. a temperature measuring hole; 2. tin paste; 3; a chip to be tested; 30. and (7) welding ends.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first" and "second", etc. are used merely as labels, and are not limiting on the number of their objects.
In the assembly welding process of electronic products, the welding quality directly affects the quality of the whole machine. Therefore, in order to improve the soldering quality, in addition to strict control of process parameters, scientific solderability testing of chips is required.
At present, a tin dipping method and a simulated reflow soldering method are mainly adopted when the solderability of the chip is tested. The tin dipping method is mainly suitable for the chip with pins, such as: QFP (Plastic Quad Flat Package) chips, SOP (Small Out-Line Package) chips, and the like; the simulated reflow method can be applied to the chip with the pin and the chip without the pin, for example: LCC (lead Chip Carriers, Leadless Chip carrier components) type chips, and the like.
In the related technology, the tin dipping method is mainly used for judging the solderability of a chip coated with soldering flux and provided with a pin by immersing the chip into a molten tin furnace and then observing the covering condition of solder on the pin, but the method has low test accuracy and is easily influenced by external factors; the simulated reflow soldering method is mainly characterized in that solder paste is Printed on a pad of a Printed Circuit Board (PCB), a soldering terminal of a chip to be tested (namely a chip with a pin or a chip without a pin) is placed on the solder paste and subjected to reflow soldering treatment, so that the chip to be tested is soldered on the PCB, and then the solderability of the chip to be tested is judged by detecting the coverage condition of the solder paste on the soldering terminal of the chip to be tested; however, since the solder paste is easily bonded with the bonding pad, the chip to be tested soldered on the PCB is not easily removed, and the coverage condition of the solder paste on the soldering terminal of the chip to be tested needs to be detected by using X-rays, but this method easily affects the functions of the chip, is not favorable for the repeated use of the PCB, and increases the testing cost.
In order to solve the above technical problems, embodiments of the present application provide a method for testing the solderability of a chip, where the method is applicable to testing the solderability of a chip with a pin and a chip without a pin, and is particularly applicable to testing the solderability of a Ball Grid Array (BGA) chip.
As shown in fig. 1, the method for testing the solderability of the chip may include:
step S10, printing solder paste on the ceramic substrate;
step S20, placing the welding end of the chip to be tested on the solder paste to form a substrate to be welded;
step S30, carrying out reflow soldering treatment on the substrate to be soldered so as to solder the chip to be soldered on the ceramic substrate;
step S40, removing the chip to be tested from the ceramic substrate;
and step S50, detecting the state of the solder paste on the welding end of the chip to be detected so as to determine the weldability of the chip to be detected.
In this embodiment, through using ceramic substrate as with the chip welded carrier that awaits measuring, can reduce the condition that the tin cream takes place the bonding with the carrier in reflow soldering processing procedure to the chip that awaits measuring is dismantled from ceramic substrate, thereby the state of tin cream on the welding end of the chip that awaits measuring of being convenient for visual detection, with the solderability of confirming the chip that awaits measuring, thereby the degree of accuracy of chip solderability test has been improved. According to the test method, the X-ray is not needed for detection, so that the influence on the chip to be tested in the test process can be reduced, the damage probability of the chip to be tested is reduced, the test difficulty is reduced, and in addition, the ceramic substrate can be repeatedly used in the test process, and the test cost is reduced.
The method for testing the solderability of the chip in this embodiment is described in detail below with reference to the drawings.
As shown in fig. 1, 3, and 4, in step S10, the solder paste 2 is printed on the ceramic substrate 1. In order to meet environmental requirements, the solder paste 2 may be a lead-free solder paste. The solder paste 2 comprises solder and soldering flux, and the soldering performance of the solder paste 2 is improved by adding the soldering flux into the solder.
In this embodiment, the process of printing the solder paste 2 on the ceramic substrate 1 may be: firstly, smoothly printing solder paste 2 on a ceramic substrate 1 through a steel mesh; and then slowly moving the steel mesh away to avoid the situation that the steel mesh scratches the printed solder paste 2 in the moving away process to cause the phenomenon of sharpening, thereby improving the printing quality of the solder paste 2.
For example, when the chip 3 to be tested is a BGA type chip, the solder terminal 30 of the chip is spherical, so that the opening of the steel mesh can be circular, and the diameter of the opening is consistent with that of the spherical solder terminal 30, so that the shape and size of the solder paste 2 printed on the ceramic substrate 1 are consistent with those of the solder terminal 30. It should be noted that the spacing between the openings on the steel mesh and the spacing between the bonding pads 30 on the chip need to be equal to ensure that the spacing between the printed solder pastes 2 and the spacing between the bonding pads 30 on the chip are equal.
For example, the ceramic substrate 1 may be rectangular, but not limited thereto, and may also be circular. And the ceramic substrate 1 may be provided with a positioning mark structure 10 to facilitate positioning with a steel mesh, thereby facilitating positioning between the solder paste 2 and the ceramic substrate 1.
Since the steel mesh is generally rectangular, the ceramic substrate 1 in the present embodiment is preferably a rectangular substrate as shown in fig. 3 to 6. When the ceramic substrate 1 is rectangular, the positioning mark structures 10 can be respectively arranged at four corners of the ceramic substrate 1, so that the positioning difficulty of the steel mesh and the ceramic substrate 1 can be reduced, and the position between the solder paste 2 and the ceramic substrate 1 can be conveniently positioned.
It should be noted that the positions and the number of the positioning mark structures 10 are not limited to the above. In addition, the positioning mark structure 10 may be a positioning hole or a positioning groove formed on the ceramic substrate 1, or a positioning patch adhered to the surface layer of the ceramic substrate 1. The positioning indication structure 10 may be circular or cross-shaped, but not limited thereto.
As shown in fig. 1, 5 and 6, in step S20, the bonding terminals 30 of the chip 3 to be tested are placed on the solder paste 2 to form a substrate to be bonded.
For example, the step of placing the bonding pads 30 of the chip 3 to be tested on the solder paste 2 includes: the bonding terminal 30 of the chip 3 to be tested and the solder paste 2 are overlapped in the thickness direction of the ceramic substrate 1. The thickness direction refers to a direction perpendicular to the surface of the ceramic substrate 1 on which the solder paste 2 is printed.
In an embodiment of the present disclosure, the solder terminal 30 of the chip 3 to be tested is placed on the solder paste 2 through a positioning process, wherein the positioning process between the solder terminal 30 of the chip 3 to be tested and the solder paste 2 may be: the aforementioned steel mesh can be positioned by the positioning mark structure 10, so that the position of the solder paste 2 can be positioned, that is, the position of the solder paste 2 is determined; after the position of the solder paste 2 is determined, the position of the soldering terminal 30 of the chip 3 to be tested is positioned by the positioning identification structure 10, so that the position of the soldering terminal 30 of the chip 3 to be tested coincides with the position of the solder paste 2, and the soldering terminal 30 of the chip 3 to be tested is positioned on the solder paste 2 to form a substrate to be welded.
It should be noted that, after the soldering terminal 30 of the chip 3 to be tested is positioned on the solder paste 2, whether the soldering terminal 30 of the chip 3 to be tested is overlapped with the solder paste 2 can be further detected through the magnifying lens, and if not, the chip is repositioned; if the two are overlapped, the next step is carried out.
In order to ensure the testing precision of the chip solderability, it is necessary to ensure that the solder paste 2 on the ceramic substrate 1 matches with the solder terminals 30 of the chip 3 to be tested in this embodiment. However, since the steel mesh needs to be removed after the solder paste 2 is printed on the ceramic substrate 1 using the steel mesh, there is a possibility that the solder paste 2 may be damaged during the removal of the steel mesh, and therefore, the method for testing the solderability of the chip may further include step S12 after the solder paste 2 is printed on the ceramic substrate 1 and before the solder terminals 30 of the chip 3 to be tested are placed on the solder paste 2 to form a substrate to be soldered. In step S12, it is detected whether or not the shape and size of the solder paste 2 printed on the ceramic substrate 1 match the shape and size of the bonding end 30 of the chip 3 to be tested. When it is detected that the shape and size of the solder paste 2 are consistent with those of the solder terminals 30, step S20 is executed; when it is detected that the shape and size of the solder paste 2 do not conform to the shape and size of the solder terminal 30, step S10 is executed again, that is: the solder paste 2 is reprinted.
In step S30, the substrate to be soldered is subjected to a reflow process to solder the chip 3 to be soldered to the ceramic substrate 1.
For example, the step S30 may include placing the substrate to be soldered in a reflow oven to perform a preheating process, a reflow process, and a cooling process in sequence, so that the chip 3 to be soldered is soldered on the ceramic substrate 1. The preheating treatment can comprise heating treatment and heat preservation treatment, namely, the substrates to be welded can be subjected to heating treatment, heat preservation treatment, reflux treatment and cooling treatment in sequence in a reflow soldering furnace; in the embodiment, the substrate to be soldered is heated to evaporate the solvent and the gas in the solder paste 2, and meanwhile, the soldering flux in the solder paste 2 wets the ceramic substrate 1 and the soldering terminal 30 of the chip 3 to be tested, so that the solder paste 2 melts, collapses and covers the part of the ceramic substrate 1 corresponding to the soldering terminal 30 of the chip 3 to be tested, and the part and the soldering terminal 30 of the chip 3 to be tested are isolated from oxygen; then, heat preservation treatment is carried out, so that the ceramic substrate 1 and the chip 3 to be tested are fully preheated, and the situation that the chip 3 to be tested is damaged due to sudden entering of a high-temperature environment in the reflux treatment process is prevented; then, carrying out reflow treatment, wherein in the reflow treatment process, the temperature is rapidly increased to enable the solder paste 2 to reach a molten state, and the liquid tin solder wets, diffuses and reflows the welding ends 30 of the ceramic substrate 1 and the chip 3 to be tested to form a tin soldering joint; finally, cooling treatment is carried out to solidify the tin soldering joint, thus completing reflow soldering.
Since the foregoing mentions that the solder paste 2 is a lead-free solder paste, the preheating treatment in the reflow soldering process may be performed at a temperature of 150 ℃ to 180 ℃ for the lead-free solder paste, that is: preheating a substrate to be welded at the temperature of 150-180 ℃, wherein the preheating time can be 60-120 s, in one embodiment of the disclosure, the preheating temperature can be 155 ℃, 160 ℃, 165 ℃, 170 ℃ or 175 ℃, and the preheating time can be 70s, 80s, 90s, 100s or 110 s; the reflow process in the reflow soldering process may be performed at a temperature of 230 ℃ to 250 ℃, that is: reflowing the substrate to be welded at 230-250 deg.C for 30-60 s, in one embodiment of the disclosure, 235 deg.C, 240 deg.C or 245 deg.C, and 35, 40, 45, 50 or 55 s; the cooling process in the reflow process may be performed at room temperature until the soldered joint is solidified.
It should be noted that the aforementioned preheating temperature, preheating time, refluxing temperature and refluxing time are not limited to the above values, as the case may be.
In the reflow soldering process of the substrate to be soldered, the temperatures of the ceramic substrate 1 and the chip 3 to be soldered need to be monitored in real time, and therefore, in order to accurately monitor the temperatures of the surfaces of the ceramic substrate 1 and the chip 3 to be soldered, as shown in fig. 3 to 6, a temperature measurement hole 11 can be formed in the ceramic substrate 1, a temperature measurement connector of a temperature measurement element is placed in the temperature measurement hole 11, the temperature measurement element can monitor the temperatures of the ceramic substrate 1 and the chip 3 to be soldered in real time and record and store the temperatures, and after the reflow soldering is completed, the temperature measurement element is connected with a computer terminal device to present a temperature curve recorded by the temperature measurement element, so that the temperature of each processing area in the reflow soldering furnace can be controlled according to the temperature measurement curve, and the requirements of the reflow soldering process can be met.
Optionally, the temperature measuring hole 11 is located in the central region of the ceramic substrate 1 to improve the detection accuracy of the temperature measuring element located in the temperature measuring hole 11.
In step S40, the chip 3 to be tested is removed from the ceramic substrate 1. For example, the chip 3 to be tested can be carefully detached from the ceramic substrate 1 by using a removing device.
In step S50, the state of the solder paste 2 on the bonding terminal 30 of the chip 3 to be tested is detected to determine the solderability of the chip 3 to be tested.
For example, the solder paste 2 mentioned above includes tin solder and flux, but when evaluating the solderability of the chip 3 to be tested, only the state of the tin solder on the bonding pads 30 of the chip 3 to be tested is generally evaluated, and the flux is not within the evaluation range, so as shown in fig. 2, the step S50 may include steps S502, S504, and S506, where:
in step S502, it is determined whether flux remains on the bonding end 30 of the chip 3 to be tested; since the solder is generally dark gray and the flux is generally white, it is easy to confirm whether or not the flux remains at the bonding terminals 30 of the chip 3 after the chip 3 is removed from the ceramic substrate 1.
In step S504, when it is confirmed that the flux remains on the bonding terminals 30 of the chip 3 to be tested, the flux is removed. It should be noted that care is taken to avoid damaging the tips 30 and the solder on the tips 30 during the flux removal process.
In step S506, the state of the tin solder on the bonding terminal 30 of the chip 3 to be tested is detected to determine the solderability of the chip 3 to be tested. Wherein, the step S506 may specifically be: detecting whether the coverage rate of the tin solder on the welding end 30 exceeds a first preset value and detecting whether tin beads with the diameter larger than or equal to a second preset value are arranged on the welding end 30 of the chip 3 to be detected; when the coverage rate of the tin solder on the welding end 30 is detected to exceed a first preset value and no tin bead with the diameter larger than or equal to a second preset value exists on the welding end 30, determining that the weldability of the chip 3 to be tested passes the test standard, and determining that the chip 3 to be tested is a qualified product; and when the coverage rate of the tin solder on the welding end 30 is detected to be less than or equal to a first preset value and/or the welding end 30 is detected to have tin beads with the diameter exceeding a second preset value, determining that the weldability of the chip 3 to be tested does not pass the test standard, and determining that the chip 3 to be tested is unqualified.
In addition, since the size of the chip 3 to be tested is usually small, the size of the bonding terminal 30 of the chip 3 to be tested is also small, so that it is not easy to check the size of the solder ball on the bonding terminal 30 of the chip 3 to be tested, that is, a certain error may occur in detecting the size of the solder ball on the bonding terminal 30 of the chip 3 to be tested. Since the ceramic substrate 1 and the chip 3 to be tested are soldered together by the solder paste 2 during the reflow process, when the chip 3 to be tested is removed from the ceramic substrate 1, not only the solder 30 of the chip 3 to be tested is covered with the solder, but also a part of the solder remains on the ceramic substrate 1. Therefore, whether the solder balls with the diameter greater than or equal to the second preset value exist on the soldering end 30 of the chip 3 to be tested can be reflected by detecting whether the solder balls with the diameter greater than or equal to the second preset value exist on the ceramic substrate 1, that is: if the ceramic substrate 1 has the tin beads with the diameter larger than or equal to the second preset value, the solder terminal 30 of the chip 3 to be tested also has the tin beads with the diameter larger than or equal to the second preset value; if the ceramic substrate 1 does not have the solder balls with the diameter greater than or equal to the second preset value, the solder terminal 30 of the chip 3 to be tested does not have the solder balls with the diameter greater than or equal to the second preset value.
As can be seen from the above description, in an embodiment of the present disclosure, in order to improve the accuracy of the solderability test of the chip 3 to be tested, while detecting the state of the tin solder on the bonding terminal 30 of the chip 3 to be tested to determine the solderability of the chip 3 to be tested, the chip solderability test method may further include: and step 60, detecting whether the ceramic substrate 1 has tin beads with the diameter larger than or equal to a second preset value so as to further determine the weldability of the chip 3 to be detected.
Specifically, when it is detected that the coverage rate of the tin solder on the soldering terminal 30 exceeds a first preset value and no tin bead with the diameter larger than or equal to a second preset value exists on the soldering terminal 30 and the ceramic substrate 1, it is determined that the solderability of the chip 3 to be tested passes the test standard, and the chip 3 to be tested is a qualified product; when the coverage rate of the tin solder on the welding end 30 is detected to be less than or equal to a first preset value and/or the welding end 30 and/or the ceramic substrate 1 has tin beads with the diameter exceeding a second preset value, determining that the weldability of the chip 3 to be tested does not pass the test standard, and determining that the chip 3 to be tested is unqualified.
It should be noted that the first preset value may be 0.95, but not limited thereto, as the case may be. The second preset value can be 0.13mm, but is not limited thereto, as the case may be.
In an embodiment, before positioning the bonding terminals 30 of the chip 3 to be tested on the solder paste 2 to form the substrate to be bonded, the method for testing the reliability of the chip may further include performing a steam aging process on the chip 3 to be tested. The solderability of the chip 3 to be tested after long-time storage is simulated by carrying out steam aging treatment on the chip 3 to be tested. That is, the testing method can test the weldability of the chip 3 to be tested after long-time storage, and the testing range is improved, so that the weldability of the chip 3 to be tested can be evaluated in many aspects.
The water in the steam aging treatment is distilled water or deionized water. Furthermore, the temperature in the steam aging process is inversely proportional to the altitude, namely: the higher the altitude, the lower the temperature; the lower the altitude, the higher the temperature.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
Claims (18)
1. A method for testing the solderability of a chip, comprising:
printing solder paste on the ceramic substrate;
placing the welding end of the chip to be tested on the solder paste to form a substrate to be welded;
performing reflow soldering treatment on the substrate to be soldered so that the chip to be soldered is soldered on the ceramic substrate;
removing the chip to be tested from the ceramic substrate;
and detecting the state of the solder paste on the welding end of the chip to be detected so as to determine the weldability of the chip to be detected.
2. The method for testing the solderability of the chip of claim 1, wherein the solder paste includes solder and flux,
the detecting the state of the solder paste on the welding end of the chip to be detected so as to determine the weldability of the chip to be detected comprises the following steps:
confirming whether the soldering flux remains on the soldering terminal of the chip to be tested;
removing the soldering flux when the residual soldering flux is confirmed on the soldering terminal of the chip to be tested;
and detecting the state of tin solder on the welding end of the chip to be detected so as to determine the weldability of the chip to be detected.
3. The method for testing the solderability of the chip according to claim 2, wherein the detecting the state of the solder on the bonding terminal of the chip to be tested to determine the solderability of the chip to be tested comprises:
detecting whether the coverage rate of the tin solder on the welding end exceeds a first preset value and detecting whether tin balls with the diameter larger than or equal to a second preset value exist on the welding end of the chip to be detected;
when the fact that the coverage rate of the tin solder on the welding end exceeds the first preset value and no tin bead with the diameter larger than or equal to the second preset value exists on the welding end is detected, the fact that the weldability of the chip to be tested passes a test standard is determined;
and when the coverage rate of the tin solder on the welding end is detected to be less than or equal to the first preset value and/or the welding end is detected to have tin beads with the diameter exceeding the second preset value, determining that the weldability of the chip to be tested does not pass the test standard.
4. The method for testing the solderability of the chip according to claim 3, wherein the method for testing the solderability of the chip under test further comprises the following steps of, while detecting the state of the solder on the bonding terminal of the chip under test to determine the solderability of the chip under test:
and detecting whether the ceramic substrate has tin beads with the diameter larger than or equal to the second preset value or not so as to determine the weldability of the chip to be detected.
5. The method for testing the solderability of the chip of claim 3, wherein the first predetermined value is 0.95 mm and the second predetermined value is 0.13 mm.
6. The method for testing the solderability of the chip according to claim 1, wherein after the solder paste is printed on the ceramic substrate and before the solder terminals of the chip to be tested are placed on the solder paste to form a substrate to be soldered, the method further comprises;
detecting whether the shape and the size of the solder paste printed on the ceramic substrate are consistent with the shape and the size of the welding end of the chip to be detected,
and when the shape and the size of the solder paste are consistent with those of the welding ends, the step of placing the welding ends of the chip to be tested on the solder paste to form the substrate to be welded is executed.
7. The method for testing the solderability of the chip according to claim 1, wherein the placing the bonding terminal of the chip to be tested on the solder paste comprises:
and superposing the welding end of the chip to be tested and the solder paste in the thickness direction of the ceramic substrate.
8. The method for testing the solderability of the chip according to claim 1, wherein the reflow soldering process is performed on the substrate to be soldered so that the chip to be soldered is soldered on the ceramic substrate, and the method comprises the following steps:
and placing the substrate to be welded in a reflow soldering furnace to sequentially perform preheating treatment, reflow treatment and cooling treatment so as to weld the chip to be tested on the ceramic substrate.
9. The method for testing the solderability of the chip of claim 8, wherein the solder paste is a lead-free solder paste.
10. The method for testing the solderability of a chip according to claim 9,
the preheating treatment comprises preheating the substrate to be welded at the temperature of 150-180 ℃;
the reflow treatment comprises reflowing the substrates to be welded at a temperature of 230 ℃ to 250 ℃.
11. The method for testing the solderability of the chip according to claim 1, wherein before the solder terminals of the chip to be tested are placed on the solder paste to form a substrate to be soldered, the method further comprises:
and carrying out steam aging treatment on the chip to be tested.
12. The method for testing the solderability of the chip of claim 11, wherein the water in the steam aging process is distilled or deionized water.
13. The method for testing the solderability of a chip according to claim 1,
the ceramic substrate is provided with a temperature measuring hole, and a temperature measuring joint of a temperature measuring element is placed in the temperature measuring hole.
14. The method for testing the solderability of a chip of claim 13,
the temperature measuring hole is positioned in the central area of the ceramic substrate.
15. The method for testing the solderability of the chip according to claim 1, wherein the ceramic substrate is rectangular, and four corners of the ceramic substrate are respectively provided with a positioning identification structure, and the positioning identification structures are used for positioning the position between the solder paste and the ceramic substrate and positioning the position between the solder paste and the soldering terminal of the chip to be tested.
16. The method for testing the solderability of the chip as claimed in claim 15, wherein the positioning mark structure is a positioning hole, a positioning groove or a positioning patch adhered to the surface layer of the ceramic substrate.
17. The method for testing the solderability of the chips of claim 16, wherein the positioning identification structures are circular or cross-shaped.
18. The method for testing the solderability of the chip according to claim 1, wherein the chip to be tested is a ball grid array package type chip.
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| CN113319454A (en) * | 2021-04-29 | 2021-08-31 | 中国电子科技集团公司第二十九研究所 | Solder presetting method for welding end of surface-mounted self-contained solid solder connector |
| CN115302121A (en) * | 2022-07-26 | 2022-11-08 | 德中（天津）技术发展股份有限公司 | Reflow soldering test method for testing solderability of printed circuit board |
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