CN111223774A - Method for wafer planarization and image sensor manufactured by the same - Google Patents

Method for wafer planarization and image sensor manufactured by the same Download PDF

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Publication number
CN111223774A
CN111223774A CN201910800373.XA CN201910800373A CN111223774A CN 111223774 A CN111223774 A CN 111223774A CN 201910800373 A CN201910800373 A CN 201910800373A CN 111223774 A CN111223774 A CN 111223774A
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China
Prior art keywords
layer
region
polishing
insulating layer
scribe line
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CN201910800373.XA
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CN111223774B (en
Inventor
蒋妵希
金石镐
罗勋奏
文光辰
朴宰亨
李圭夏
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

A wafer planarization method includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe line region; forming a first via hole in the polishing layer in the chip region and the scribe line region and a second via hole in the second insulating layer in the chip region, wherein the second via hole meets the first via hole in the chip region; forming a pad metal layer in the first and second vias and on the upper surface of the polishing layer; the polishing layer and the pad metal layer are polished by a Chemical Mechanical Polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe line region.

Description

Method for wafer planarization and image sensor manufactured by the same
Technical Field
Exemplary embodiments of the inventive concept relate to a method for wafer planarization and an image sensor manufactured thereby.
Background
An image sensor may be formed by bonding a lower substrate wafer including logic circuits to an upper substrate including pixels. The upper and lower substrates may be separate wafers that are bonded to each other by wafer-to-wafer bonding.
The wafer typically includes chip areas arranged in a grid and scribe line areas located between the chip areas. The chip region includes a plurality of devices and a plurality of lines disposed under the insulating layer and a plurality of vias (via) electrically connected to the devices or the lines and exposed to a surface of the wafer. Thus, the chip region is formed such that the via hole passes through the insulating layer and is exposed at the surface of the wafer. The scribe line region is formed only by the insulating layer at the wafer surface.
In wafer-to-wafer bonding, the surfaces of wafers to be bonded (hereinafter, referred to as "bonding surfaces") are first planarized by Chemical Mechanical Polishing (CMP). In order to ensure the bonding strength, the planarization should form the bonding surface as a completely flat surface. However, since the chip region and the scribe line region have different surface characteristics, a step between the chip region and the scribe line region may be formed during planarization.
Disclosure of Invention
According to an exemplary embodiment of the inventive concept, there is provided a method for wafer planarization, including: forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe region; forming a first via hole in the polishing layer in the chip region and the scribe line region and a second via hole in the second insulating layer in the chip region, wherein the second via hole meets the first via hole in the chip region; forming a pad metal layer in the first and second vias and on the upper surface of the polishing layer; the polishing layer and the pad metal layer are polished by a Chemical Mechanical Polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe line region.
According to an exemplary embodiment of the inventive concept, there is provided a method for wafer planarization, including: forming an insulating layer and a polishing layer on a substrate having a chip region and a scribe region; forming a first via hole in the polishing layer in the chip region and the scribe line region using the first photoresist pattern formed on the upper surface of the polishing layer as an etching mask, and forming a second via hole connected to the first via hole in the insulating layer in the chip region; forming a pad metal layer inside the first and second via holes and on an upper surface of the polishing layer; the polishing layer and the pad metal layer are polished by a CMP process to expose upper surfaces of the insulating layer in the chip region and the scribe line region, wherein the first via hole formed in the scribe line region is formed with a horizontal sectional area smaller than that of the first via hole formed in the chip region.
According to an exemplary embodiment of the inventive concept, there is provided an image sensor including: a lower substrate including a lower main substrate having a chip region and a scribe region, and a lower line layer disposed on the lower main substrate; an upper substrate including an upper main substrate having a chip region and a scribe region, and an upper line layer disposed on the upper main substrate, wherein the upper substrate is disposed on a lower substrate, wherein the lower line layer has a lower insulating layer disposed at an uppermost portion of the lower substrate, the upper line layer has an upper insulating layer disposed at a lowermost portion of the upper substrate, an upper surface of the lower insulating layer and a lower surface of the upper insulating layer are bonded to each other, the lower insulating layer has a lower insulating groove in an upper surface of the scribe region of the lower substrate, and the upper insulating layer has an upper insulating groove in a lower surface of the scribe region of the upper substrate.
According to an exemplary embodiment of the inventive concept, there is provided a method for wafer planarization, including: forming a substrate including a chip region and a scribe line region; forming an insulating layer on a substrate; forming a polishing layer on the insulating layer; forming a first via in the polished layer of the scribe line region; forming a second through hole in the insulating layer of the chip region; forming a pad metal layer in the first and second vias and on the polishing layer; and polishing the pad metal layer to expose a surface of the insulating layer in the chip region and the scribe line region.
Drawings
Fig. 1A is a plan view of a wafer, fig. 1B is a partially enlarged view of a portion a of fig. 1A, and fig. 1C is a vertical sectional view taken along a line B-B of fig. 1B.
Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, and 2H are vertical sectional views illustrating processes of a wafer planarization method according to an exemplary embodiment of the inventive concept.
Fig. 3A and 3B are vertical sectional views of lower and upper substrates formed by a wafer planarization method according to an exemplary embodiment of the inventive concept, and fig. 3C is a vertical sectional view of an image sensor formed by bonding.
Fig. 4A and 4B are vertical sectional views illustrating processes of a wafer planarization method according to an exemplary embodiment of the inventive concept.
Fig. 5 is a vertical sectional view illustrating a process of a wafer planarization method according to an exemplary embodiment of the inventive concept.
Fig. 6A and 6B are vertical sectional views illustrating processes of a wafer planarization method according to an exemplary embodiment of the inventive concept.
Detailed Description
Hereinafter, a method for wafer planarization and an image sensor manufactured thereby according to an exemplary embodiment of the inventive concept will be described.
A wafer to which the wafer planarization method according to the exemplary embodiment of the inventive concept is applied will be described.
Fig. 1A is a plan view of a wafer, fig. 1B is a partially enlarged view of a portion a of fig. 1A, and fig. 1C is a vertical sectional view taken along a line B-B of fig. 1B.
The wafer 10, which will be described below, may be a wafer for a Complementary Metal Oxide Semiconductor (CMOS) image sensor. The wafer 10 may be a lower substrate 20 or an upper substrate 40 of an image sensor (see fig. 3A to 3C). Hereinafter, a case where the wafer 10 is the lower substrate 20 of the image sensor will be described. In the following description, the wafer 10 may be identically or similarly applied to the upper substrate 40.
Referring to fig. 1A to 1C, a wafer 10 includes a chip region 11 and a scribe line region 12 with respect to a horizontal direction. The chip regions 11 are arranged in a grid while being spaced apart from each other in a horizontal direction on the wafer 10. The chip region 11 may include a pixel region 11a and a transition region (transfer region)11 b. The wafer 10 may include a first surface and a second surface. The first surface of the wafer 10 may be the upper surface of the wafer 10. The second surface of the wafer 10 may be the lower surface of the wafer 10.
Wafer 10 may include a substrate body 13 (also referred to as a "primary substrate") and a wire layer 14. In the wafer 10, the wire layer 14 may be disposed on the main substrate 13. The wire layer 14 may face upward in the wafer 10, and the lower surface of the main substrate 13 may face downward. Wafer 10 may also include transistor 15. Wafer 10 may also include additional components along with host substrate 13, wire layer 14, and transistors 15.
The primary substrate 13 may include a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The main substrate 13 may be a first conductive type substrate. The chip region 11 of the main substrate 13 includes a plurality of source/drain regions 13 a. The scribe line region 12 of the main substrate 13 does not include the source/drain region 13 a. A plurality of source/drain regions 13a may form the transistor 15.
The wire layer 14 may include a plurality of insulating layers 14 a. Chip region 11 of wire layer 14 may also include a plurality of conductive pads 14b and a plurality of conductive vias 14 c. Scribe area 12 of wire layer 14 does not include a plurality of conductive pads 14b and a plurality of conductive vias 14 c. For example, the scribe line region 12 may include only the insulating layer 14a and the primary substrate 13.
A plurality of insulating layers 14a may be formed on the primary base plate 13. The conductive pad 14b may be disposed on an upper side or a lower side of each of the plurality of insulating layers 14a and exposed to an upper surface or a lower surface of each of the plurality of insulating layers 14 a. A plurality of conductive pads 14b may be exposed to the upper surface of line layer 14. The conductive pads 14b may be exposed to an upper surface of the insulating layer 14a, which is located at an uppermost portion of the wafer 10. In this case, the upper surface of the conductive pad 14b may be coplanar with the upper surface of the insulating layer 14 a. The insulating layer 14a may be formed of an insulating material such as SiCN, SiN, or SiOCN. The conductive via 14c may vertically pass through the insulating layer 14 a. The conductive via 14c may electrically connect the upper conductive pad 14b and the lower conductive pad 14b, or may electrically connect the upper conductive pad 14b or the lower conductive pad 14b to the transistor 15.
The transistor 15 may be formed in the main substrate 13 and the insulating layer 14 a. The transistor 15 may include a source/drain region 13a formed in the main substrate 13 and a gate electrode 13b formed in the insulating layer 14 a. The source/drain region 13a may be disposed adjacent to the upper surface of the main substrate 13. The transistor 15 may be a logic transistor. The transistor 15 may be a transistor of different conductivity types. For example, the transistor 15 may include an n-type transistor and a p-type transistor.
After a Chemical Mechanical Polishing (CMP) process is performed on the wafer 10, the wafer 10 may be wafer-bonded to another wafer 10 forming the upper substrate 40 and including the image sensor (see fig. 3A to 3C). Wafer bonding is performed such that the wire layers of the wafer 10 forming the lower substrate 20 are in contact with and bonded to the wire layers of the wafer 10 forming the upper substrate 40. In this case, the conductive pads 14b exposed to the upper surface of the wire layer 14 of the wafer 10 forming the lower substrate 20 may be bonded and electrically connected to the conductive pads 14b exposed to the lower surface of the wire layer of the wafer 10 forming the upper substrate 40. The wafer bonding must completely bond the conductive pads 14b formed in the chip regions 11 of the two wafers 10 to prevent generation of voids. In wafer bonding, when a void is formed in the chip region 11, physical contact and bonding between the conductive pads 14b becomes incomplete, so that wafer bonding characteristics and reliability of the image sensor may be degraded.
In the wafer 10 shown in fig. 1A to 1C, the insulating layer 14a located above the chip region 11 and the scribe line region 12 is simultaneously planarized by CMP to be formed as a bonding surface. The bonding surface includes an upper surface of the insulating layer 14a located at the uppermost portion of the chip region 11 and an upper surface of the insulating layer 14a located at the uppermost portion of the scribe line region 12. Since the conductive pad 14b is exposed at the upper surface of the insulating layer 14a of the chip region 11, the polishing degree may be different from that of the insulating layer 14a of the scribe line region 12 excluding the conductive pad 14b exposed at the upper surface thereof. Therefore, a CMP planarization process may be employed to prevent a step between the bonding surfaces of the chip region 11 and the scribe line region 12.
A wafer planarization method according to an exemplary embodiment of the inventive concept will be described below.
Fig. 2A to 2H are vertical sectional views illustrating processes of a wafer planarization method according to an exemplary embodiment of the inventive concept.
The wafer planarization method according to the present embodiment is a method of planarizing the bonding surface of the wafer 10 to bond the wafer 10. Hereinafter, the method of wafer planarization will be described mainly with respect to a process of forming the insulating layer 14a located at the uppermost portion of the wafer 10 and the conductive pads 14b located on the insulating layer 14a of the chip region 11. The method of wafer planarization will be shown and described with respect to the insulating layer 14a located at the uppermost portion of the wafer 10 and from which the conductive pads 14b are exposed. The main substrate 13 and the additional insulating layer 14a formed on the main substrate 13 may not be shown, and thus a description thereof will be omitted. The wafer planarization method described below prevents a step or a bend from being generated between the bonding surfaces of the chip region 11 and the scribe line region 12.
Referring to fig. 2A, a second insulating layer 120 and a polishing layer 130 are formed on an upper surface of a first insulating layer 110. The first insulating layer 110 and the second insulating layer 120 are formed in both the chip region 11 and the scribe line region 12. The first insulating layer 110 may be formed by being deposited on an upper surface of an insulating layer located on an upper surface or a lower portion of the primary base plate. The conductive via 111 is formed in the first insulating layer 110. The second insulating layer 120 is formed by being deposited on the upper surface of the first insulating layer 110. The second insulating layer 120 may be formed of an insulating material such as SiCN, SiN, or SiOCN. The second insulating layer 120 may be formed to a height depending on the height of the conductive pad 180. The second insulating layer 120 may be formed by a process such as a sputtering process.
A polishing layer 130 having a predetermined thickness is formed on the upper surface of the second insulating layer 120. Since the polishing layer 130 is to be polished by CMP, the polishing layer 130 may be formed to have a suitable thickness in consideration of CMP efficiency. The polishing layer 130 may be formed to have a thickness less than that of the second insulating layer 120. Polishing layer 130 may be formed of, for example, Tetraethylorthosilicate (TEOS), SiO2SiCN, SiN or SiOCN. Polishing layer 130 may be formed of a non-metallic material such as TaN. The polishing layer 130 may be formed of, for example, siloxane spin-on glass (SOG), silicate SOG, phosphosilicate glass (PSG), or the likePlasma Enhanced Oxide (PEOX) or Undoped Silicate Glass (USG).
Referring to fig. 2B, a first via hole 130a is formed in the polishing layer 130 using the first photoresist pattern 140 formed on the upper surface of the polishing layer 130 as an etching mask. The first photoresist pattern 140 may be formed by applying a photoresist layer onto the upper surface of the polishing layer 130 and then exposing and developing the photoresist layer using a photomask. An anti-reflection layer for a photoresist process may be formed under the first photoresist pattern 140. A hard mask pattern may be formed instead of the first photoresist pattern 140. The first photoresist pattern 140 may include a first opening 140a corresponding to the first via 130a formed in the polishing layer 130. The first through hole 130a is formed through the upper surface of the polishing layer 130 to the lower surface of the polishing layer 130. The first via hole 130a may expose an upper surface of the second insulating layer 120. The first via hole 130a may be formed to further extend from the upper surface of the polishing layer 130 to a lower portion of the first insulating layer 110 by a predetermined depth.
The first via 130a may be formed to receive a conductive pad 180 (see fig. 2H) formed in the second insulating layer 120 of the chip region 11. For example, the first through hole 130a may have a top view of a circular shape. The first through holes 130a may be formed in the chip region 11 and the scribe line region 12 at the same size and the same interval. The first through holes 130a may be formed in the chip region 11 and the scribe line region 12 at the same hole density. The hole density may refer to an area of the first through holes 130a per unit area of the bonding surface. For example, the pore density may refer to every 1cm2The aperture area of the bonding surface of (a). According to an exemplary embodiment of the inventive concept, the bonding surface of the chip region 11 and the bonding surface of the scribe line region 12 may be formed in the same state to be polished identically during CMP.
The first through hole 130a may be formed to have the same top view in the chip region 11 and the scribe line region 12. For example, all the first through holes 130a may be formed to have a top view showing a circular shape. In this case, the first through hole 130a formed in the chip region 11 and the first through hole 130a formed in the scribe line region 12 may have the same diameter. The first through hole 130a formed in the chip region 11 and the first through hole 130a formed in the scribe line region 12 may be formed at the same separation distance and spaced apart from each other.
The first through hole 130a may be formed to have different top views in the chip region 11 and the scribe line region 12. For example, the first through hole 130a formed in the chip region 11 may have a shape corresponding to the shape of the conductive pad 180, and the first through hole 130a formed in the scribe line region 12 may have an oval shape, a quadrangular shape, or a cross shape. However, even in this case, the first through holes 130a may be formed in the chip region 11 and the scribe line region 12 at the same hole density.
The first through hole 130a may be formed in different horizontal sectional shapes in the chip region 11 and the scribe line region 12. However, even in this case, the first through holes 130a may be formed in the chip region 11 and the scribe line region 12 at the same hole density.
Referring to fig. 2C, a sacrificial layer 150 is deposited on the upper surface of the polishing layer 130 and inside the first via hole 130a, and a second photoresist pattern 160 is formed on the upper surface of the sacrificial layer 150. The first photoresist pattern 140 is removed before the sacrificial layer 150 is deposited. The first photoresist pattern 140 may be removed by an ashing stripping process. A hard mask pattern may be formed instead of the first photoresist pattern 140. In this case, the hard mask pattern may not be removed before the sacrificial layer 150 is deposited.
The sacrificial layer 150 is formed in the entire chip region 11 and the scribe line region 12. The sacrificial layer 150 may cover the upper surface of the polishing layer 130 and fill the inside of the first via 130a in the chip region 11 and the scribe line region 12. The sacrificial layer 150 may be formed of a material having an etch selectivity with respect to the polishing layer 130. The sacrificial layer 150 may be formed of a material having no etch selectivity with respect to the second insulating layer 120. The sacrificial layer 150 may be formed of, for example, TEOS, SiO2SiCN, SiN or SiOCN. The sacrificial layer 150 may be formed of a non-metallic material such as TaN. The sacrificial layer 150 may be formed of a material such as siloxane SOG, silicate SOG, PSG, PEOX, or USG. The sacrificial layer 150 mayFormed of an organic material or an inorganic material. The sacrificial layer 150 may be formed of a polyarylether-based material, a polymethylmethacrylate-based material, or a spin-on polymer (SOP) such as a vinylether methacrylate-based material. The sacrificial layer 150 may be formed of an inorganic material, such as Hydrogen Silsesquioxane (HSQ) -based material or Methyl Silsesquioxane (MSQ) -based material.
The second photoresist pattern 160 may be formed by applying a photoresist layer onto the upper surface of the sacrificial layer 150 and then exposing and developing the photoresist layer using a photomask. The second photoresist pattern 160 may include a second opening 160a formed at a position corresponding to the first via 130a formed in the polishing layer 130 of the chip region 11. The second opening 160a may be formed to have the same top view as that of the first opening 140 a. The second opening 160a may be formed only in a region corresponding to the chip region 11 in the second photoresist pattern 160.
Referring to fig. 2D, a second via hole 120a is formed in the sacrificial layer 150, the polishing layer 130, and the second insulating layer 120 of the chip region 11 using the second photoresist pattern 160 as an etching mask. The second via 120a may have the same top view as that of the first via 130a formed in the chip region 11. The top view of the second through-hole 120a may be the same as the shape and size of the first through-hole 130 a. For example, the second through hole 120a may have a top view having a circular shape with the same diameter as that of the first through hole 130 a. The second via 120a may have a top view corresponding to the conductive pad 180. The second via 120a is formed at the same position as the first via 130a in the chip region 11 with respect to the horizontal surface of the polishing layer 130. The second via 120a may include a first via 130a formed in the polishing layer 130. The second via hole 120a may expose the upper surface of the first insulating layer 110 and the upper surface of the conductive via 111 by passing through the second insulating layer 120.
Referring to fig. 2E, the second photoresist pattern 160 and the sacrificial layer 150 are removed to expose the first via hole 130a of the scribe line region 12. A second via hole 120a passing through the polishing layer 130 and the second insulating layer 120 is formed in the chip area 11, and a first via hole 130a passing through the polishing layer 130 is formed in the scribe line area 12. The second via hole 120a may expose the upper surface of the first insulating layer 110 and the upper surface of the conductive via 111.
Referring to fig. 2F, a diffusion preventing layer 170, a pad seed layer 175, and a pad metal layer 180a are formed in an area including the insides of the first and second via holes 130a and 120a and the upper surface of the first polishing layer 130. The diffusion preventing layer 170 is formed in an area including the upper surface of the conductive via 111 exposed by the second via 120a, the inner surface of the second via 120a, and the upper surface of the polishing layer 130 in the chip area 111. The diffusion preventing layer 170 is formed in a region of the scribe line region 12 including the upper surface of the second insulating layer 120 exposed by the first through hole 130a, the inner surface of the first through hole 130a, and the upper surface of the polishing layer 130 exposed by the first through hole 130 a. The pad seed layer 175 may be deposited on the surface of the diffusion preventing layer 170. A pad metal layer 180a is formed on the surface of the pad seed layer 175 to fill the first and second via holes 130a and 120 a. The pad metal layer 180a may also be formed on the upper surface of the polishing layer 130.
The diffusion preventing layer 170 may be formed of a material such as titanium, titanium nitride, tungsten nitride, titanium tungsten alloy, chromium nitride, tantalum, or tantalum nitride. The diffusion preventing layer 170 may be formed to have
Figure BDA0002182154030000081
To
Figure BDA0002182154030000082
Is measured. The diffusion preventing layer 170 may be formed by a process such as a Chemical Vapor Deposition (CVD) process, a sputtering process, or an atomic layer deposition process. The diffusion preventing layer 170 prevents the copper material of the pad metal layer 180a from diffusing to the surroundings thereof. The pad seed layer 175 may be formed of a copper material. The pad seed layer 175 is formed by being deposited on the surface of the diffusion preventing layer 170. The pad seed layer 175 may be formed by a CVD process or an electroless plating process. The pad seed layer 175 may be formed to have
Figure BDA0002182154030000083
To
Figure BDA0002182154030000084
Is measured.
The pad metal layer 180a may be formed of a copper material. The pad metal layer 180a is formed such that the copper material fills the first and second via holes 130a and 120a and is plated on the surface of the polishing layer 130. A pad metal layer 180a is formed on the inner sides of the first and second via holes 130a and 120a and on the upper surface of the polishing layer 130 in the chip area 11 and the scribe line area 12. The pad metal layer 180a is formed in the same pattern density in the chip region 11 and the scribe line region 12. The pattern density may be similar to the hole density described above. The pad metal layer 180a may be formed in the same horizontal area per unit horizontal area in the chip region 11 and the scribe line region 12 with respect to the upper surface of the polishing layer 130. The pad metal layer 180a may be formed by an electroplating process.
Referring to fig. 2G, in the chip region 11 and the scribe line region 12, the pad metal layer 180a may be polished and removed by a CMP process. The pad metal layer 180a formed on the upper surface of the polishing layer 130 is selectively removed through a CMP process. In this case, a portion of the pad metal layer 180a formed on the polishing layer 130 and a portion of the pad metal layer 180a formed on the first and second vias 130a and 120a are removed. A portion of the pad metal layer 180a may remain inside the first and second vias 130a and 120 a. The diffusion preventing layer 170 and the pad seed layer 175 in the interiors of the first and second through holes 130a and 120a are also not removed. The polishing slurry used for the CMP process may be a slurry that polishes the pad metal layer 180a relatively well.
Referring to fig. 2H, the pad metal layer 180a positioned within the first and second via holes 130a and 120a is polished to have a height completely exposing the upper surface of the second insulating layer 120 by an additional CMP process, and then removed together with the polishing layer 130. The upper surface of the second insulating layer 120 is exposed in the chip region 11 and the scribe line region 12 to form a bonding surface. The pad metal layer 180a located within the first via hole 130a is formed at the upper surface of the second insulating layer 120 such that the pad metal layer 180a can be completely removed from the first via hole 130 a. The pad metal layer 180a positioned within the second via hole 120a is formed at a lower portion of the second insulating layer 120 so that the pad metal layer 180a can be removed only to a height corresponding to an upper surface of the second insulating layer 120. The slurry used for the CMP process may be an alkaline colloidal silica slurry having a metal selection ratio in the range of 1:1.4 to 1:1.8, and an abrasive having a particle size of 50 nm.
The chip region 11 and the scribe line region 12 have the same or similar internal structure from the upper surface of the polishing layer 130 to a predetermined depth or lower surface of the polishing layer 130. The chip region 11 and the scribe line region 12 also have the same or similar internal structure from the upper surface of the polishing layer 130 to the upper surface of the second insulating layer 120 located on the lower surface of the polishing layer 130. The polishing layer 130 will be polished at the same speed in the chip area 11 and the scribe line area 12. To achieve this, the polishing layer 130 having the same layer structure or pattern is formed in the chip region 11 and the scribe line region 12. For example, the pad metal layer 180a may be formed in the polishing layer 130 in the same pattern density in the chip area 11 and the scribe line area 12. When the polishing layer 130 is polished by the CMP process, the polishing layer 130 is polished and removed at the same speed or at the same height in the chip region 11 and the scribe line region 12. Since the second insulating layer 120 exposed after polishing the polishing layer 130 is polished until the upper surface thereof is completely exposed, the second insulating layer 120 can be polished to have the same height in the chip region 11 and the scribe line region 12 even if the chip region 11 and the scribe line region 12 are in different states. Therefore, no step is formed on the joining surface of the chip region 11 and the scribe line region 12. After the CMP process, the conductive pad 180 is formed in the second via 120 a.
In the second insulating layer 120, after the CMP process, a second insulating groove 120b may be formed in the upper surface of the scribe line region 12. The second insulation groove 120b may be formed at a position corresponding to the first via hole 130 a. As shown in fig. 2G and 2H, a second insulation groove 120b may be formed in the upper surface of the second insulation layer 120, and the CMP process is performed in two stages. As described above, when the polishing slurry used in the CMP process of fig. 2H is a slurry having a selectivity ratio to metal in the range of 1:1.4 to 1:1.8, the second insulating recesses 120b may be formed. During the CMP process, in the scribe line region 12, the pad metal layer 180a is polished to expose the diffusion preventing layer 170 and the polishing layer 130. Since the diffusion preventing layer 170 is polished relatively faster than the polishing layer 130 or removed during the polishing process, the surface of the second insulating layer 120 is first exposed. Accordingly, in a subsequent CMP process, the polishing layer 130 and the second insulating layer 120 are polished together, and a second insulating groove 120b may be formed at the position of the pad metal layer 180a on the upper surface of the second insulating layer 120 of the scribe line region 12. The second insulation groove 120b may have a shape corresponding to a top view of the diffusion preventing layer 170 formed on the lower surface of the first through hole 130 a. Since the scribe line region 12 is not bonded during wafer bonding, the second insulation groove 120b does not affect the bonding characteristics of the chip region 11. Since the second insulation groove 120b is formed while the scribe line region 12 becomes completely flat, the second insulation groove 120b is not formed to be completely recessed in the chip region 11.
An oxide layer may be further formed on the upper surface of the second insulating layer 120. The oxide layer may be formed by oxidizing the second insulating layer 120. The oxide layer may be formed by oxidizing the upper surface of the second insulating layer 120 during the CMP process of the second insulating layer 120.
A bonding process of a wafer manufactured by a wafer planarization method and an image sensor manufactured thereby according to an exemplary embodiment of the inventive concept will be described below.
Fig. 3A and 3B are vertical sectional views of lower and upper substrates formed of a wafer manufactured by a wafer planarization method according to an exemplary embodiment of the inventive concept, and fig. 3C is a vertical sectional view of an image sensor formed by bonding.
Referring to fig. 3A to 3C, the lower substrate 20 and the upper substrate 40 formed of the wafer manufactured by the wafer planarization method according to the exemplary embodiment of the inventive concept may be combined by wafer-to-wafer bonding. The upper surface of the lower substrate 20 and the lower surface of the upper substrate 40 are planarized by the wafer planarization method of the present inventive concept. Each of the lower substrate 20 and the upper substrate 40 is divided into a chip region 11 and a scribe line region 12. Each of the lower substrate 20 and the upper substrate 40 may be formed in various internal structures. Thus, the lower substrate 20 and the upper substrate 40 shown in fig. 3A to 3C are example structures.
Referring to fig. 3A, the lower substrate 20 may include a chip region 11 and a scribe line region 12. The chip region 11 may include a pixel region 11a and a transition region 11 b.
The lower substrate 20 may include a lower main substrate 21 and a lower wiring layer 23. In the lower substrate 20, a lower line layer 23 may be disposed above the lower main substrate 21. In the lower substrate 20, the upper surface of the lower wiring layer 23 may face upward, and the lower surface of the main substrate 21 may face downward. The lower primary substrate 21 and the lower wire layer 23 are parts corresponding to the primary substrate 13 and the wire layer 14 of fig. 1C.
The lower host substrate 21 may include a bulk silicon substrate or an SOI substrate. The lower host substrate 21 may be a first conductive type substrate. The chip region 11 of the lower host substrate 21 includes a plurality of lower transistors 22. The scribe line region 12 of the lower host substrate 21 does not include the lower transistor 22. The lower transistor 22 may be a logic transistor. The lower transistor 22 may be a transistor of a different conductivity type. For example, the lower transistor 22 may include an n-type transistor and a p-type transistor.
The lower line layer 23 may include a plurality of insulating layers 24 (also referred to as "lower insulating layers 24"). The lower line layer 23 may include a lower oxide layer 25. The chip region 11 of the lower wire layer 23 may further include a plurality of lower conductive pads 26 and a plurality of lower conductive vias 27. The scribe line region 12 of the lower line layer 23 does not include the plurality of lower conductive pads 26 and the plurality of lower conductive vias 27. Scribe area 12 of lower wire layer 23 may also include a lower insulating recess 28. The lower insulating layer 24, the lower conductive pad 26, and the lower conductive via 27 are parts corresponding to the insulating layer 14a, the conductive pad 14b, and the conductive via 14C of fig. 1C.
A plurality of lower insulating layers 24 may be formed on the lower primary substrate 21 with a predetermined thickness. The lower conductive pad 26 may be disposed on an upper or lower side of the lower insulating layer 24 to be exposed to an upper or lower surface of the lower insulating layer 24. A plurality of lower conductive pads 26 are exposed at the upper surface of the lower line layer 23. The lower conductive pad 26 is also exposed at the upper surface of the lower insulating layer 24 located at the uppermost portion of the lower substrate 20. In this case, the upper surface of the lower conductive pad 26 may be coplanar with the upper surface of the lower insulating layer 24. The upper surface of the lower conductive pad 26 may be coplanar with the upper surface of the lower oxide layer 25 located on the lower insulating layer 24. The lower insulating layer 24 may be formed of an insulating material such as SiCN, SiN, or SiOCN.
The lower conductive via 27 is formed vertically through the lower insulating layer 24. The lower conductive via 27 may electrically connect the lower conductive pad 26 located at the upper and lower portions of the lower insulating layer 24, or the lower conductive via 27 may electrically connect the lower conductive pad 26 to the lower transistor 22.
The lower oxide layer 25 may be formed on an upper surface of the lower insulating layer 24 positioned at an uppermost portion of the lower substrate 20. The lower oxide layer 25 may be formed by oxidizing the lower insulating layer 24. The lower oxide layer 25 may be formed by oxidizing the lower insulating layer 24 during a CMP process of the lower insulating layer 24.
A lower insulation groove 28 is formed on an upper surface of the lower insulation layer 24 located at an upper portion in the scribe region 12 of the lower line layer 23. The lower insulation groove 28 may not be formed in the chip region 11. For example, the lower insulation groove 28 may be formed only in the scribe line region 12. The lower insulation groove 28 may be formed to have a concave shape toward the primary base plate 21 in a downward direction from the upper surface of the lower insulation layer 24. The lower insulation groove 28 may be formed such that the upper portion thereof is open and the vertical section thereof is arc-shaped or rectangular in shape. The lower insulation recess 28 may have a polyhedral shape, for example, a hemispherical shape or a hexahedral shape. Alternatively, since the lower insulation groove 28 is formed by etching the lower insulation layer 24, the upper portion of the lower insulation groove 28 may be open, and the vertical section thereof may have an irregular shape instead of an arc shape or a rectangular shape.
The lower insulation groove 28 may be formed to have the same area density as that of the lower conductive pad 26 exposed to the upper portion of the lower insulation layer 24 in the chip region 11. Here, the area density may be an area of the lower insulation groove 28 per unit area. For example, the area density may be per cm of the lower insulating layer 242Or the area of lower insulating recess 28 or the area of lower conductive pad 26. Since the lower insulation groove 28 is formed by the CMP process of the lower insulation layer 24, the lower insulation groove 28 may be formed to have a smaller area density than the lower conductive pad 26The area density of (a). The area of the lower insulation groove 28 may decrease as the lower insulation layer 24 is polished.
Referring to fig. 3B, the upper substrate 40 may include a chip region 11 and a scribe line region 12, similar to the lower substrate 20. The chip region 11 may include a pixel region 11a and a transition region 11 b. The upper substrate 40 may include a plurality of pixels Px in the chip region 11.
The upper substrate 40 may include an upper main substrate 41 and an upper line layer 43. In the upper substrate 40, an upper line layer 43 may be disposed under the upper main substrate 41. In the upper substrate 40, the lower surface of the upper line layer 43 may face downward, and the upper surface of the upper main substrate 41 may face upward. In the upper substrate 40, the buffer layer BL, the color filter CF, the grid pattern GP, and the microlenses ML may be disposed on the upper main substrate 41. The color filters CF and the microlenses ML of the upper substrate 40 may form pixels Px.
The upper primary substrate 41 may include a bulk silicon substrate or an SOI substrate. The upper primary substrate 41 may have the same conductivity type as the lower primary substrate 21. The chip region 11 of the upper main substrate 41 includes a plurality of upper transistors 42. The upper transistor 42 may be a picture transistor. The scribe line region 12 of the upper main substrate 41 does not include the upper transistor 42. A plurality of device isolation patterns TR and a plurality of photoelectric conversion regions PD1 and PD2 may be provided within the upper main substrate 41. The device isolation pattern TR may include an insulating material. The device isolation pattern TR may include a material having a refractive index lower than that of the upper primary substrate 41. The photoelectric conversion regions PD1 and PD2 may be regions doped with first conductivity type impurities or second conductivity type impurities. The upper main substrate 41 may include a floating diffusion region FD and a source/drain region SDR. The floating diffusion region FD and the source/drain region SDR may be regions doped with first conductive type impurities or second conductive type impurities.
The upper line layer 43 may include a plurality of upper insulating layers 44. The upper line layer 43 may include an upper oxide layer 45. The chip region 11 of the upper wire layer 43 may also include a plurality of upper conductive pads 46 and a plurality of upper conductive vias 47. Scribe line region 12 of upper line layer 43 may not include a plurality of upper conductive pads 46 and a plurality of upper conductive vias 47. Scribe line region 12 of upper line layer 43 may further include an upper insulation groove 48.
A plurality of upper insulating layers 44 may be formed below the upper primary substrate 41 with a predetermined thickness. The upper conductive pad 46 may be disposed on an upper or lower side of the upper insulating layer 44 to be exposed to an upper or lower surface of the upper insulating layer 44. A plurality of upper conductive pads 46 may be exposed at a lower surface of upper line layer 43. An upper conductive pad 46 exposed to the lower surface of the upper insulating layer 44 may be disposed at the lowermost portion of the upper insulating layer 44. In this case, the lower surface of the upper conductive pad 46 may be coplanar with the lower surface of the upper insulating layer 44. The lower surface of the upper conductive pad 46 may be coplanar with the lower surface of the upper oxide layer 45 located at the lower portion of the upper insulating layer 44. The upper insulating layer 44 may be formed of an insulating material such as SiCN, SiN, or SiOCN.
The upper oxide layer 45 may be formed on a lower surface of the upper insulating layer 44 located at the lowermost portion of the upper substrate 40. The upper oxide layer 45 may be formed by oxidizing the upper insulating layer 44. The upper oxide layer 45 may be formed by oxidizing the upper insulating layer 44 during a CMP process of the upper insulating layer 44.
An upper conductive via 47 is formed vertically through the upper insulating layer 44. The upper conductive via 47 may electrically connect the upper conductive pad 46 located at the upper and lower portions of the upper insulating layer 44, or the upper conductive via 47 may electrically connect the upper conductive pad 46 located at the upper portion of the upper insulating layer 44 to the upper transistor 42.
An upper insulation groove 48 is formed on the lower surface of the upper insulation layer 44 located at the lower portion in the scribe line region 12 of the upper line layer 43. For example, the upper insulation groove 48 may be formed at the lowermost portion of the upper substrate 40. The upper insulation groove 48 may not be formed in the chip region 11. For example, the upper insulation groove 48 may be formed only in the scribe line region 12. The upper insulation groove 48 may be formed in the same shape as the lower insulation groove 28 with respect to the horizontal direction. The upper insulation groove 48 may be formed at the same position as that of the lower insulation groove 28. The upper insulation groove 48 may be positioned above the lower insulation groove 28 when the upper substrate 40 and the lower substrate 20 are wafer bonded. In this case, the upper insulation groove 48 and the lower insulation groove 28 may form a gap together. The upper insulation groove 48 may be formed at a position different from that of the lower insulation groove 28 with respect to the horizontal direction. The upper insulation groove 48 may be formed to have an area density less than or equal to that of the upper conductive pad 46 exposed to the lower portion of the upper insulation layer 44 in the chip region 11. The upper insulation groove 48 may be formed to have a density equal to that of the lower insulation groove 28.
Referring to fig. 3C, the lower insulating layer 24 of the lower substrate 20 and the upper insulating layer 44 of the upper substrate 40 are bonded to contact each other. In this case, when the lower oxide layer 25 is formed on the upper surface of the lower insulating layer 24 and the upper oxide layer 45 is formed on the lower surface of the upper insulating layer 44, the lower oxide layer 25 and the upper oxide layer 45 are in contact with and bonded to each other. The upper conductive pads 46 located in the chip region 11 of the upper substrate 40 contact and are bonded to the lower conductive pads 26 located in the chip region 11 of the lower substrate 20. Since the insulating layer of the chip region 11 is planarized without a step with the insulating layer of the scribe line region 12, the upper and lower substrates 40 and 20 are uniformly in contact with each other, so that a void is not formed. The upper insulation groove 48 located in the scribing region 12 of the upper substrate 40 together with the lower insulation groove 28 located in the scribing region 12 of the lower substrate 20 may form an empty space. When the upper substrate 40 and the lower substrate 20 are bonded to each other, the scribing region 12 may be cut, so that an image sensor may be formed.
In the method for wafer planarization, an etch stop layer may be formed between the second insulating layer 120 and the polishing layer 130. According to exemplary embodiments of the inventive concept, the etch stop layer may be applied to a method of wafer planarization, which will be described below.
A method of planarizing a wafer according to an exemplary embodiment of the inventive concept will be described below.
Fig. 4A and 4B are vertical sectional views illustrating processes of a wafer planarization method according to an exemplary embodiment of the inventive concept. Fig. 4A and 4B are vertical sectional views corresponding to fig. 2B and 2D.
Compared to the wafer planarization method according to fig. 2A to 2H, the order of the wafer planarization method according to the present embodiment is different from the order of forming the first and second through holes 130a and 120 a. According to the current wafer planarization method, the second via 120a is formed first, and then the first via 130a is formed.
Referring to fig. 4A, a first via hole 130a is formed in the polishing layer 130 of the chip region 11, and a second via hole 120a is formed in the second insulating layer 120, using the first photoresist pattern 140 formed on the upper surface of the polishing layer 130 as an etching mask. The first photoresist pattern 140 may include a first opening 140a corresponding to a top view of the first via 130a formed in the polishing layer 130. The first via hole 130a is formed by passing through the polishing layer 130 in the chip region 11. The second through hole 120a is formed by penetrating the second insulating layer 120 in the chip region 11. The first through hole 130a and the second through hole 120a may be sequentially formed.
Referring to fig. 4B, a sacrificial layer 150 is deposited on the upper surface of the polishing layer 130 and within the first and second vias 130a and 120 a. A second photoresist pattern 160 is formed on the upper surface of the sacrificial layer 150. The second photoresist pattern 160 is provided with a second opening 160a in the scribe line region 12. The second opening 160a is formed at a position corresponding to the first and second through holes 130a and 120a in the scribe line region 12.
Subsequently, as shown in fig. 2E, the second photoresist pattern 160, the sacrificial layer 150, and the polishing layer 130 are removed to expose the first and second via holes 130a and 120a in the chip region 11. The subsequent processes may be performed according to the processes of fig. 2F to 2H.
A wafer planarization method according to an exemplary embodiment of the inventive concept will be described below.
Fig. 5 is a vertical sectional view illustrating a process of a wafer planarization method according to an exemplary embodiment of the inventive concept. Fig. 5 is a vertical sectional view corresponding to fig. 2F.
The wafer planarization method according to the present embodiment is different from the wafer planarization method according to fig. 2A to 2H in that the diffusion preventing layer 170 and the pad seed layer 175 are not formed before the pad metal layer 180 a. Therefore, differences of the wafer planarization method will be mainly described below. A detailed description of the configuration according to the current wafer planarization method, which is the same as or similar to the wafer planarization method of fig. 2A to 2H, will be omitted.
In the wafer planarization method according to the present embodiment, the process is performed according to fig. 2A to 2E. The process then continues according to fig. 5.
Referring to fig. 5, a pad metal layer 180a is formed within the first and second vias 130a and 120 a. In this embodiment, the diffusion preventing layer 170 and the pad seed layer 175 are not formed within the first and second via holes 130a and 120 a. The pad metal layer 180a may be formed of a material such as copper, nickel, or titanium. The pad metal layer 180a may be formed of a metal material that is not diffused into the first insulating layer 110 during a manufacturing process or use. The pad metal layer 180a may be formed of a copper material so that there is no adverse effect even when the metal material is diffused into the second insulating layer 120 during a process or use. The pad metal layer 180a may be formed by a method such as plating or CVD process.
Since the diffusion preventing layer 170 is not formed within the first via hole 130a in the scribe line region 12, the second insulation groove 120b shown in fig. 2H may not be formed during the CMP process.
A wafer planarization method according to an exemplary embodiment of the inventive concept will be described below.
Fig. 6A and 6B are vertical sectional views illustrating processes of a wafer planarization method according to an exemplary embodiment of the inventive concept.
The wafer planarization method according to the present embodiment is different in that the first through hole 130a and the second through hole 120a are formed to have different diameters, compared to the wafer planarization method according to fig. 2A to 2H.
Referring to fig. 6A, a second insulating layer 120 and a polishing layer 130 are formed on an upper surface of a first insulating layer 110, a first via hole 130a is formed in the polishing layer 130 using a first photoresist pattern 140 formed on the upper surface of the polishing layer 130 as an etching mask, and a second via hole 120a is formed in the second insulating layer 120. The first through hole 130a is simultaneously formed in the chip region 11 and the scribe line region 12 using the first photoresist pattern 140 as an etching mask. The first photoresist pattern 140 is provided with a first opening 140a at a position corresponding to the first via 130 a. The second via hole 120a is formed in the second insulating layer 120 in the chip region 11 and connected to the first via hole 130 a. Accordingly, the first via 130a formed in the polishing layer 130 of the chip region 11 and the scribe line region 12 and the second via 120a formed in the second insulating layer 120 in the chip region 11 may be simultaneously formed during the same process. The first through hole 130a formed in the scribe line region 12 is formed to have a horizontal sectional area smaller than that of the first through hole 130a formed in the chip region 11. The first photoresist pattern 140 is provided with a first opening 140a and a second opening 140 b. The first opening 140a is formed in a region corresponding to the first via 130a formed in the scribe line region 12, and the second opening 140b is formed in a region corresponding to the first via 130a formed in the chip region 11. The horizontal sectional area of the first opening 140a is smaller than that of the second opening 140 b. For example, the diameter or area of the first opening 140a is smaller than the diameter or area of the second opening 140 b. Accordingly, the first via 130a formed by the first opening 140a has a depth shallower than that of the second via 120a formed by the second opening 140 b. The diameters or areas of the first and second openings 140a and 140b may be determined in consideration of the thicknesses of the polishing layer 130 and the second insulating layer 120.
The first and second openings 140a and 140b are formed to have the same hole density. In order to have the same hole density, the number of the first openings 140a may be increased instead of having a relatively small area. For example, four first openings 140a may be formed, and one second opening 140b may be formed based on the same area.
Referring to fig. 6B, the diffusion preventing layer 170, the pad seed layer 175, and the pad metal layer 180a are formed in a region including the inside of the first and second via holes 130a and 120a and the upper surface of the polishing layer 130.
The vertical sectional area of the pad metal layer 180a formed in the polishing layer 130 in the scribe line region 12 is smaller than the vertical sectional area of the pad metal layer 180a formed in the polishing layer 130 in the chip region 11. However, it should be understood that the pattern densities of the pad metal layer 180a in the scribe line region 12 and the chip region 11 may be equal to each other. The pad metal layer 180a formed in the polishing layer 130 in the scribe line region 12 may have the same total area as the pad metal layer 180a formed in the polishing layer 130 in the chip region 11. Accordingly, the scribe line region 12 and the chip region 11 may be uniformly polished during the CMP process of the polishing layer 130.
According to exemplary embodiments of the inventive concept, a step between a chip region and a scribe line region becomes small, and an unbonded region of bonding surfaces that contact each other during a wafer-to-wafer bonding process becomes small or non-existent, so that wafer bonding characteristics and reliability of an image sensor may be improved.
While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the inventive concept as defined by the appended claims.
Korean patent application No. 10-2018-0146663, entitled "METHOD FOR wafer planarization AND AN IMAGE SENSOR master BY SAME (METHOD FOR wafer planarization and image SENSOR MADE therefrom)" filed BY THE korean intellectual property office on 23/11/2018, is hereby incorporated BY reference in its entirety.

Claims (25)

1. A wafer planarization method comprises:
forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe region;
forming a first via in the polished layer in the chip region and the scribe line region and a second via in the second insulating layer in the chip region, wherein the second via meets the first via in the chip region;
forming a pad metal layer within the first and second vias and on an upper surface of the polishing layer; and
polishing the polishing layer and the pad metal layer by a Chemical Mechanical Polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe line region.
2. The method of claim 1, wherein forming the first via comprises:
forming the first via hole in the polishing layer using a first photoresist pattern formed on the upper surface of the polishing layer as an etching mask;
depositing a sacrificial layer on the upper surface of the polishing layer and within the first via and forming a second photoresist pattern on an upper surface of the sacrificial layer;
forming the second via hole through the sacrificial layer and the second insulating layer of the chip region using the second photoresist pattern as an etching mask; and
removing the second photoresist pattern and the sacrificial layer to expose the first via hole in the scribe line region.
3. The method of claim 1, further comprising:
forming a diffusion preventing layer and a pad seed layer between the diffusion preventing layer and the pad metal layer in the first and second through holes and on the upper surface of the polishing layer,
wherein polishing the polishing layer and the pad metal layer by the chemical mechanical polishing process comprises:
removing a pad metal layer formed on the upper surface of the polishing layer; and
and removing the polishing layer and the pad metal layer positioned in the first through hole and the second through hole.
4. The method of claim 3, wherein an insulating recess is formed in the second insulating layer at a location corresponding to the first via in the scribe line region.
5. The method of claim 1, further comprising forming an oxide layer on the upper surface of the second insulating layer during the chemical mechanical polishing process.
6. The method of claim 1, wherein the first via formed in the chip region and the first via formed in the scribe line region have the same hole density.
7. The method of claim 1, wherein the first via formed in the chip region and the first via formed in the scribe line region have the same top view and the same separation distance.
8. The method of claim 1, wherein the first via formed in the chip region and the first via formed in the scribe line region have different top views and the same hole density.
9. The method of claim 1, wherein the first via formed in the chip region and the first via formed in the scribe line region have different shapes of vertical cross-sectional areas and the same hole density.
10. The method of claim 1, wherein forming the first and second vias comprises:
forming the first via hole in the polishing layer of the chip region and the second via hole in the second insulating layer using a first photoresist pattern formed on the upper surface of the polishing layer as an etching mask;
depositing a sacrificial layer on the upper surface of the polishing layer and within the first and second vias and forming a second photoresist pattern on the upper surface of the sacrificial layer;
forming the first via hole in the polished layer in the scribe line region using the second photoresist pattern as an etching mask; and
removing the second photoresist pattern and the sacrificial layer to expose the first via hole and the second via hole in the chip region.
11. The method of claim 10, further comprising forming a diffusion prevention layer and a pad seed layer between the diffusion prevention layer and the pad metal layer within the first and second vias and on the upper surface of the polishing layer.
12. The method of claim 10, wherein polishing the polishing layer and the pad metal layer by the chemical mechanical polishing process comprises:
removing a pad metal layer formed on the upper surface of the polishing layer; and
and removing the polishing layer and the pad metal layer positioned in the first through hole and the second through hole.
13. The method as claimed in claim 10, wherein an insulating groove is formed in the upper surface of the second insulating layer at a position corresponding to the first via hole in the scribe line region.
14. A wafer planarization method comprises:
forming an insulating layer and a polishing layer on a substrate having a chip region and a scribe region;
forming a first via hole in the polishing layer in the chip region and the scribe line region using a first photoresist pattern formed on an upper surface of the polishing layer as an etching mask, and forming a second via hole connected to the first via hole in the insulating layer in the chip region;
forming a pad metal layer on the inside of the first and second via holes and the upper surface of the polishing layer; and
polishing the polishing layer and the pad metal layer by a Chemical Mechanical Polishing (CMP) process to expose an upper surface of the insulating layer in the chip region and the scribe line region,
wherein the first through hole formed in the scribe line region is formed with a horizontal sectional area smaller than that of the first through hole formed in the chip region.
15. An image sensor, comprising:
a lower substrate including a lower main substrate having a chip region and a scribe region, and a lower line layer disposed on the lower main substrate; and
an upper substrate including an upper main substrate having a chip region and a scribe region, and an upper line layer disposed on the upper main substrate, wherein the upper substrate is disposed on the lower substrate,
wherein the lower line layer has a lower insulating layer disposed at an uppermost portion of the lower substrate,
the upper line layer has an upper insulating layer disposed at a lowermost portion of the upper substrate,
an upper surface of the lower insulating layer and a lower surface of the upper insulating layer are bonded to each other,
the lower insulating layer has a lower insulating groove in an upper surface of the scribe line region of the lower substrate, an
The upper insulating layer has an upper insulating groove in a lower surface of the scribing region of the upper substrate.
16. The image sensor of claim 15, wherein the lower insulation groove and the upper insulation groove are located at the same position with respect to a horizontal direction.
17. The image sensor of claim 15, wherein the lower insulation groove and the upper insulation groove are located at different positions with respect to a horizontal direction.
18. The image sensor of claim 15, wherein each of the lower insulation groove and the upper insulation groove includes an open upper portion and has a vertical cross-section of an arc shape, a rectangular shape, or an irregular shape.
19. The image sensor of claim 15, wherein:
the lower substrate further includes a lower oxide layer formed on the upper surface of the lower insulating layer; and
the upper substrate further includes an upper oxide layer formed on the lower surface of the upper insulating layer.
20. The image sensor of claim 19 wherein the lower oxide layer and the upper oxide layer are in contact with each other and are bonded to each other.
21. A wafer planarization method comprises:
forming a substrate including a chip region and a scribe line region;
forming an insulating layer on the substrate;
forming a polishing layer on the insulating layer;
forming a first via in the polishing layer in the scribe line region;
forming a second via hole in the insulating layer in the chip region;
forming a pad metal layer in the first and second vias and on the polishing layer; and
polishing the pad metal layer to expose a surface of the insulating layer in the chip region and the scribe line region.
22. The method of claim 21, wherein the pad metal layer is polished by a Chemical Mechanical Polishing (CMP) process.
23. The method of claim 21, wherein the entire surface of the insulating layer is exposed by polishing the pad metal layer.
24. The method of claim 21, wherein the surface of the insulating layer includes a recess in the scribe line region and the surface of the insulating layer does not include a recess in the chip region.
25. The method of claim 21, wherein the first via and the second via form an opening to receive the pad metal layer in the chip area.
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