CN111221690A - Model determination method and device for integrated circuit design and terminal - Google Patents
Model determination method and device for integrated circuit design and terminal Download PDFInfo
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- CN111221690A CN111221690A CN201911324062.7A CN201911324062A CN111221690A CN 111221690 A CN111221690 A CN 111221690A CN 201911324062 A CN201911324062 A CN 201911324062A CN 111221690 A CN111221690 A CN 111221690A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The embodiment of the application provides a method, a device, a terminal and a storage medium for determining a model of integrated circuit design. The method comprises the following steps: determining a gate-level netlist corresponding to an integrated circuit design to be tested; matching the gate-level netlist with a pre-stored model library to determine a plurality of sub-time information flow models, wherein the model library comprises the plurality of sub-time information flow models and a corresponding query table, and the query table comprises the corresponding relation between the plurality of sub-time information flow models and the corresponding basic logic units; and connecting the plurality of sub-time information flow models based on the connection relation among the plurality of basic logic units in the gate-level netlist to obtain the time information flow model designed for the integrated circuit. The embodiment of the application simplifies the generation step of the time flow output model, and transplants the test step of the integrated circuit to the research and development stage, thereby solving the problems of high test cost and low test efficiency caused by testing the finished product in the prior art.
Description
Technical Field
The present application relates to the field of information security technologies, and in particular, to a method, an apparatus, and a terminal for determining a model for an integrated circuit design.
Background
With the development of computers and electronic information technologies, smart phones and wearable devices gradually move to people's daily life. The devices store important personal information such as identification numbers, social security numbers, bank account numbers, and the like. In order to prevent confidential information from being illegally accessed, a cryptographic algorithm is usually introduced for protection. But cryptographic algorithms face a serious threat in terms of time side channels because they are implemented using software and hardware programs, which may consume different times when the programs execute different statements. An attacker can extract the key-related information by observing the running time of the cipher using statistical analysis techniques, thereby cracking the key.
However, the related method for testing hardware devices generally directly tests the finished product, and therefore, if the test effect is poor, the hardware devices need to be redesigned and generated, and thus the existing method for testing hardware devices has the problems of high cost and low efficiency.
Disclosure of Invention
In order to solve any one of the above technical problems, the present application provides a method, an apparatus, a terminal and a storage medium for determining a model of an integrated circuit design, so as to reduce the test cost of hardware devices and improve the test efficiency.
In a first aspect, the present application provides a method for determining a model of an integrated circuit design, where the test model is used to test an integrated circuit to be designed, and the method includes:
determining a gate-level netlist corresponding to an integrated circuit design to be tested;
matching the gate-level netlist with a pre-stored model library to determine a plurality of sub-time information flow models, wherein the model library comprises the plurality of sub-time information flow models and a corresponding query table, and the query table comprises the corresponding relation between the plurality of sub-time information flow models and the corresponding basic logic units;
and connecting the plurality of sub-time information flow models based on the connection relation among the plurality of basic logic units corresponding to the gate-level netlist to obtain the time information flow model designed for the integrated circuit.
In a second aspect, the present application provides a model determination apparatus for an integrated circuit design, the test model being used for testing an integrated circuit to be designed, the apparatus comprising:
the netlist determining module is used for determining a gate-level netlist corresponding to the integrated circuit design to be tested;
the model matching module is used for matching the gate-level netlist with a pre-stored model library to determine a plurality of sub-time information flow models, the model library comprises a plurality of sub-time information flow models and a corresponding query table, and the query table comprises the corresponding relation between the plurality of sub-time information flow models and the corresponding basic logic units;
and the model determining module is used for connecting the plurality of sub-time information flow models based on the connection relation among the plurality of basic logic units corresponding to the gate-level netlist to obtain the time information flow model designed for the integrated circuit.
In a third aspect, an embodiment of the present application provides a terminal, where the terminal includes:
a memory, a processor and a computer program stored on the memory and executable on the processor, the processor when executing the computer program to implement the above-described method of model determination for an integrated circuit design.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium storing computer-executable instructions for performing the above-described model determination method for an integrated circuit design.
The beneficial effects of the embodiment of the application are as follows: by constructing a plurality of sub-time flow output models, a plurality of sub-time information flow models which are completely matched with a gate-level netlist can be determined directly according to the gate-level netlist corresponding to the integrated circuit design to be tested, so that the plurality of sub-time information flow models replace a plurality of basic logic units in the gate-level netlist and are connected to obtain the time information flow models for the integrated circuit design, the purpose of transplanting the testing steps of the integrated circuit design to a research and development stage is achieved, and the problems of high testing cost and low efficiency caused by the fact that the integrated circuit design is required to be firstly hardwired into hardware equipment and then tested in the prior art are solved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments of the present application will be briefly described below.
Fig. 1 is a schematic flowchart of a model determination method for an integrated circuit design according to an embodiment of the present disclosure;
fig. 2 is a schematic flowchart of an embodiment of a method for determining an operation rule corresponding to any basic logic unit in a model determination manner for an integrated circuit design according to the present application;
fig. 3 is a schematic diagram illustrating an and gate basic logic unit operation rule in a model determination method for an integrated circuit design according to an embodiment of the present application;
FIG. 4 is a schematic diagram illustrating operation rules of basic logic units of an OR gate in a model determination method for an integrated circuit design according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram illustrating operation rules of basic logic units of NOT gates in a model determination method for an integrated circuit design according to an embodiment of the present disclosure;
FIG. 6 is a diagram illustrating operation rules of basic logic units of a flip-flop in a model determination method for an integrated circuit design according to an embodiment of the present disclosure;
fig. 7 is a schematic block diagram illustrating a structure of a model determining apparatus for an integrated circuit design according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It should be noted that although functional blocks are partitioned in a schematic diagram of an apparatus and a logical order is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the partitioning of blocks in the apparatus or the order in the flowchart.
Example one
The embodiment of the present application provides a model determination method for an integrated circuit design, as shown in fig. 1, the method includes step S101, step S102, and step S103.
And S101, determining a gate-level netlist corresponding to the integrated circuit design to be tested.
In the embodiment of the present application, the gate-level netlist is composed of two parts, i.e., a Standard logic unit in an integrated circuit Standard technology library (Standard technology library) and a connection relationship between the Standard logic units, and the gate-level netlist generally has a uniform format, which is convenient for subsequent processing and analysis, and specifically, different Standard logic units correspond to different operation rules, such as different operation rules of an and gate, a not gate, an or gate, a flip-flop, and the like. Specifically, the gate-level netlist is used to characterize the integrated circuit design of the Hardware device to be designed, which is described in Hardware Description Language (HDL).
In a specific application, the gate-level netlist can be determined by parsing the gate-level netlist file, for example, by parsing the gate-level netlist to determine that the gate-level netlist includes an adder and a multiplier connected in sequence.
Step S102, matching the gate-level netlist with a pre-stored model library to determine a plurality of sub-time information flow models, wherein the model library comprises a plurality of sub-time information flow models and a query table, and the query table comprises a corresponding relation between the plurality of sub-time information flow models and the corresponding basic logic units.
In the embodiment of the present application, the basic logic unit is used to characterize an arithmetic unit in a digital circuit, for example, the basic logic unit may be an adder, a multiplier, or the like.
In particular applications, multiple sub-time-stream output models may be stored locally in a sorted manner so as to be directly retrieved during use, and more particularly, tags (such as numerical tags, text tags, etc.) may be used to characterize different sub-time-stream output models so as to be selected during subsequent determination of a model for an integrated circuit design.
When the method is applied specifically, the model library is generally stored locally, and the method is directly matched with the model library after the gate-level netlist is determined; in addition, during specific application, an updating and upgrading request can be sent to the remote model server, so that an updating data packet fed back by the remote model server according to the updating and upgrading request is obtained, the local model library is updated according to the updating data packet, and the timely updating of the sub-time information flow model in the model library is achieved.
Specifically, any sub-time information flow model in the lookup table and the basic logic unit corresponding to any sub-time information flow model can be represented by text labels, for example, Tag1-B1 (characterizing adder, i.e., basic logic unit), so that after querying Tag1, the sub-time information flow model is determined according to Tag 1.
In the embodiment of the application, the input time tag is used for representing a time period when the test signal is input to the sub-time-flow output model, and the output time tag is used for representing an output time period after the test signal is input to the sub-time-flow output model. Specifically, the input timestamp and the input timestamp may be represented by integer data (e.g., a time period).
And S103, connecting the plurality of sub-time information flow models based on the connection relation among the plurality of basic logic units in the gate-level netlist to obtain a time information flow model designed for the integrated circuit.
In the embodiment of the present application, the integrated circuit design is used to represent a circuit design of a designed hardware device, and specifically, the hardware device is generally a circuit design of a device having an encryption processing function or storing key information, such as a circuit design of an encryption chip, a memory (Cache), and the like.
In the embodiment of the application, the gate-level netlist corresponding to the integrated circuit design to be tested is determined, the gate-level netlist is matched with the pre-stored model library, the plurality of sub-time information flow models are determined, so that the plurality of sub-time information flow models are connected based on the connection relation between the plurality of basic logic units corresponding to the gate-level netlist, the time information flow models for the integrated circuit design are obtained, the generation step of the time flow output model is simplified, meanwhile, the mode of determining the time information flow models for the integrated circuit design by connecting the plurality of sub-time information flow models including the time labels not only shortens the time for constructing the models for the integrated circuit design, but also provides a judgment standard for the subsequently judged integrated circuit design to process the safety of input signals, and realizes that whether the time attribute labels are the same or not by judging, whether a channel of implicit time information exists in the integrated circuit design to be tested is determined, so that the integrated circuit design is improved, the problem that an attacker steals user information by using an undetected information flow channel due to the fact that the integrated circuit design comprises an implicit time side channel in the prior art is solved, and the safety of hardware equipment is improved; meanwhile, the problem of high development cost of an integrated circuit in the prior art is solved, and the method has important practical application value for detecting and eliminating the time channel as early as possible.
In one implementation, as shown in fig. 2, step S102 matches the gate-level netlist with a pre-stored model library to determine a plurality of sub-time information flow models, including:
s1021, determining model labels of the sub-time information flow models respectively matched with the multiple basic logic units in the gate level netlist based on the lookup table;
step S1022, determining a plurality of sub-time information flow models according to the model labels of the sub-time information flow models respectively matched with the plurality of basic logic units in the and gate level netlist.
For example, assuming that the gate-level netlist comprises a counter and adders cascaded together, by matching with a model library, determining that a label of a sub-time flow output model corresponding to the counter is a, and a label of a sub-time flow output model corresponding to the adders is B, searching in the model library according to A, B to determine a corresponding sub-time information flow model, and connecting to obtain the time flow model consisting of the sub-time flow models corresponding to the gate-level netlist.
For example, assume that the gate-level netlist only includes one basic logic unit, i.e., an adder, and the corresponding Tag is determined to be Tag2 by matching with the lookup table, and then the corresponding sub-time information flow model is called in the model library according to Tag 2.
Specifically, the basic logic unit corresponding to any one of the sub-time information flow models includes at least one of the following:
and gate, not gate, or gate, flip-flop.
For example, an adder is a logic unit consisting of an and gate.
In another implementation, step S101 determines a gate-level netlist corresponding to an integrated circuit design to be tested, including at least one of:
determining a gate-level netlist corresponding to an integrated circuit design to be tested according to a current circuit design tool;
and according to a preset interface, acquiring a gate-level netlist file aiming at the integrated circuit design to be tested, and determining a gate-level netlist corresponding to the integrated circuit design to be tested.
In specific application, the gate-level netlist file can be called locally through a preset interface, and can also be manufactured by using a logic synthesis tool, such as a Synopsys Design Compiler tool, that is, the application provides two ways of obtaining the gate-level netlist file, and after the gate-level netlist file is obtained, a corresponding gate-level netlist can be obtained through analysis.
In yet another implementation, as shown in fig. 1, the method includes steps S201 to S204, where steps S201, S202, and S203 are the same as or similar to steps S101, S102, and S103, respectively, and are not repeated herein.
Step S204, analyzing the integrated circuit design according to the time information flow model aiming at the integrated circuit design and a plurality of input conditions, wherein any input condition comprises respective values of a plurality of test input signals and respective time attribute labels of the plurality of test input signals.
According to the embodiment of the application, whether the time information flow model has the time side channel or not is judged by inputting the signal to the time information flow model for many times and judging whether the output time attribute labels output by the time information flow model for many times are consistent or not, for example, if the output time attribute labels are inconsistent, it can be determined that the time periods occupied by the time information flow model for signal processing are different, namely the processing duration is different, and the time side channel exists, so that the effect of transplanting the judgment of the design safety of the integrated circuit to the research and development stage is achieved, and the hardware development cost is reduced.
Further, any sub-time information flow model includes an operation rule corresponding to the any sub-time information flow model, the operation rule is a corresponding relationship between a value of each of the plurality of input signals, an input time attribute label of each of the plurality of input signals, and an output time attribute label of the any sub-time information flow model output for the plurality of input signals.
In yet another implementation, as shown in fig. 1, before the step S102 matches the gate-level netlist with the pre-stored model library, the method further includes:
determining an input time attribute label for each of a plurality of input signals of any of the sub-temporal information flow models;
when determining the respective values of a plurality of input signals of the logic function of the basic logic unit corresponding to the sub-time information flow model, determining a first signal output value of the logic function for the plurality of input signals;
determining a second signal output value of the sub-time information flow model corresponding to the logic function for the plurality of input signals when a value of any one of the plurality of input signals input to the sub-time information flow model corresponding to the logic function is changed;
if the first signal output value is inconsistent with the second signal output value, determining the input signal with the changed value in the input signal as a key input signal corresponding to the sub-time information flow model corresponding to the logic function until a plurality of key input signals of the sub-time information flow model corresponding to the logic function are obtained;
and determining an operation rule corresponding to any sub-time information flow model according to the output time attribute labels output by the any sub-time information flow model aiming at the key input signals based on the respective values of the key input signals and the respective input time attribute labels of the key input signals.
For example, assume that the logic function TO ═ f (I1, I2, I3 … In, T (I1), T (I2), T (I3) … T (In)) is an operation function corresponding TO a certain basic logic unit, where In represents input information of the input signal n, and T (In) represents an input time attribute tag of the input signal. In a specific application, the data types of T (I1), T (I2), T (I3) … T (In) may be set according to actual needs, In this embodiment of the application, T (I1), T (I2), T (I3) … T (In) are all set as integer data (used for representing a clock period), for example, T (In) is used for representing a time attribute tag when the input signal In is input to the analog test circuit. Assuming that the key input signals of the function are determined to be Is and Im according to the steps shown in fig. 2, the key input signals Is and Im are input to the function, and the corresponding relationship between the input time tags of the key input signals Is and Im and the output time tags output by the function Is determined according to the input time tags of the key input signals Is and Im and the output time tags output by the function, so as to obtain the corresponding relationship between the input time tags of each of the plurality of key input signals included in the sub-time information stream model corresponding to the certain basic logic unit and the output time tags of the any one of the plurality of sub-time information stream models with respect to the plurality of input signals.
In specific application, the sub-time information flow models corresponding to different basic logic units can be constructed by referring to table 1.
TABLE 1
Thus, according to Table 1, if the input signal is IsAnd ItWhen the logical and operation is performed, the operation result and the corresponding output time attribute tag are shown in fig. 3; when performing a logical OR operation, the operation result and its corresponding output time attribute tag are as shown in FIG. 4Shown in the specification; when the logical not operation is performed, the operation result and the corresponding output time attribute tag thereof are as shown in fig. 5; for the flip-flop, each time a signal passes through a stage of flip-flop in any basic logic unit, the output time tag is added with 1 on the basis of the input time tag, so that when a logical not operation is performed, the operation result and its corresponding output time attribute tag are as shown in fig. 6.
Therefore, after the test input signal is input into the sub-time information model, the corresponding output is determined according to the gate logic through which the test input signal passes and the operation rules corresponding to different gate logics, for example, if the test signal includes Ia and Ib, the input time attribute of Ia is t (a), and the input time attribute of i (b) is t (b), then if the test signal passes through the and gate in the analog test circuit, the output result determines the corresponding output time attribute label, specifically t (a), t (b), or the upper bound or the lower bound of the output time attribute label and the t (a), t (b), according to the rule shown in fig. 3.
Compared with the operation rule of the existing basic logic unit, the embodiment of the application establishes the corresponding relation between the input time labels of the input signals and the corresponding output results through the operation rule, namely the corresponding relation between the input time labels of the multiple key input signals included in the sub-time information flow model and the output time labels of the multiple input signals of any sub-time information flow model, and realizes the purpose of determining the processing time length according to the time labels.
Example two
The embodiment of the present application provides a model determination apparatus for an integrated circuit design, as shown in fig. 7, the apparatus 30 includes: netlist determination module 301, model matching module 302, and model determination module 303, wherein,
a netlist determining module 301, configured to determine a gate-level netlist corresponding to an integrated circuit design to be tested;
a model matching module 302, configured to match the gate-level netlist with a pre-stored model library to determine a plurality of sub-time information flow models, where the model library includes the plurality of sub-time information flow models and a corresponding lookup table, and the lookup table includes a corresponding relationship between the plurality of sub-time information flow models and corresponding basic logic units;
and the model determining module 303 is configured to perform connection processing on the multiple sub-time information flow models based on a connection relationship between multiple basic logic units corresponding to the gate-level netlist, so as to obtain a time information flow model designed for the integrated circuit.
The model determining apparatus for an integrated circuit design provided in the embodiments of the present application determines a gate-level netlist corresponding to an integrated circuit design to be tested, matches the gate-level netlist with a pre-stored model library, and determines a plurality of sub-time information flow models, so as to perform a connection process on the plurality of sub-time information flow models based on a connection relationship between a plurality of basic logic units corresponding to the gate-level netlist to obtain a time information flow model for the integrated circuit design, thereby simplifying a generation step of the time flow output model, and meanwhile, by performing a connection process on the plurality of sub-time information flow models including time tags, determining a time information flow model for the integrated circuit design is performed, thereby not only shortening a time for constructing the model for the integrated circuit design, but also providing a judgment standard for subsequently judging safety of the integrated circuit design to be tested in processing an input signal, whether the hidden time information channel exists in the integrated circuit design to be tested is determined by judging whether the time attribute labels are the same or not, so that the integrated circuit design is improved, the problem that an attacker steals user information by using the undetected information flow channel due to the fact that the integrated circuit design comprises the hidden time side channel in the prior art is solved, and the safety of hardware equipment is improved; meanwhile, the problem of high development cost of an integrated circuit in the prior art is solved, and the method has important practical application value for detecting and eliminating the time channel as early as possible.
Further, the model matching module is configured to:
determining model labels of the sub-time information flow models respectively matched with a plurality of basic logic units in the gate-level netlist based on the lookup table;
and determining a plurality of sub-time information flow models according to the model labels of the sub-time information flow models respectively matched with the plurality of basic logic units in the gate-level netlist.
Further, before the model matching module matches the gate-level netlist with the pre-stored model library, the model matching module is further configured to:
constructing a sub-time information flow model corresponding to a logic function based on the logic function corresponding to any basic logic unit, and determining respective input time attribute labels of a plurality of input signals input to the sub-time information flow model corresponding to the logic function;
determining a first signal output value corresponding to the logic function, which the sub-time information flow model outputs for the plurality of input signals, when determining respective values of the plurality of input signals input to the sub-time information flow model corresponding to the logic function;
when the value of any input signal in a plurality of input signals input to the sub-time information flow model corresponding to the logic function is changed, determining the sub-time information flow model corresponding to the logic function, and outputting a second signal output value aiming at the plurality of input signals;
if the first signal output value is inconsistent with the second signal output value, determining the input signal with the changed value in the input signal as a key input signal corresponding to the sub-time information flow model corresponding to the logic function until a plurality of key input signals of the sub-time information flow model corresponding to the logic function are obtained;
and determining an operation rule corresponding to any sub-time information flow model according to the output time attribute labels output by any sub-time information flow model aiming at the key input signals based on the respective values of the key input signals and the corresponding input time attribute labels.
Further, the basic logic unit corresponding to any sub-time information flow model comprises at least one of the following items:
and gate, not gate, or gate, flip-flop.
Further, the netlist determination module includes at least one of:
determining a gate-level netlist corresponding to an integrated circuit design to be tested according to a current circuit design tool;
and according to a preset interface, acquiring a gate-level netlist file aiming at the integrated circuit design to be tested, and determining a gate-level netlist corresponding to the integrated circuit design to be tested.
Further, the model determination module is further configured to:
the integrated circuit design is analyzed according to a time information flow model for the integrated circuit design and a plurality of input conditions, any one of which includes respective values of a plurality of test input signals and respective time attribute tags of the plurality of test input signals.
The model determining apparatus for an integrated circuit design provided in the embodiment of the present application is used to execute the model determining method for an integrated circuit design provided in the foregoing embodiment, and the implementation principles are similar, and are not described herein again.
EXAMPLE III
An embodiment of the present application provides a terminal, including: the computer program may be executed by a processor, which implements the above-described model determination method for an integrated circuit design.
In particular, the processor may be a CPU, general purpose processor, DSP, ASIC, FPGA or other programmable logic device, transistor logic device, hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. A processor may also be a combination of computing functions, e.g., comprising one or more microprocessors, a DSP and a microprocessor, or the like.
In particular, the processor is coupled to the memory via a bus, which may include a path for communicating information. The bus may be a PCI bus or an EISA bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc.
The memory may be, but is not limited to, a ROM or other type of static storage device that can store static information and instructions, a RAM or other type of dynamic storage device that can store information and instructions, an EEPROM, a CD-ROM or other optical disk storage, optical disk storage (including compact disk, laser disk, optical disk, digital versatile disk, blu-ray disk, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.
Optionally, the memory is used for storing codes of computer programs for executing the scheme of the application, and the processor is used for controlling the execution. The processor is configured to execute application program code stored in the memory to perform the actions of the model determination apparatus for an integrated circuit design provided by the embodiment shown in FIG. 7.
The terminal provided by the embodiment of the application determines a gate-level netlist corresponding to an integrated circuit design to be tested, matches the gate-level netlist with a pre-stored model library, and determines a plurality of sub-time information flow models, so that the plurality of sub-time information flow models are connected based on the connection relationship among a plurality of basic logic units corresponding to the gate-level netlist, thereby obtaining the time information flow model for the integrated circuit design, simplifying the generation step of the time flow output model, meanwhile, the mode of determining the time information flow model for the integrated circuit design by connecting the plurality of sub-time information flow models including time labels not only shortens the time for constructing the model for the integrated circuit design, but also provides a judgment standard for judging the safety of the integrated circuit design to be tested for processing input signals, thereby realizing that whether the time attribute labels are the same or not by judging, whether a channel of implicit time information exists in the integrated circuit design to be tested is determined, so that the integrated circuit design is improved, the problem that an attacker steals user information by using an undetected information flow channel due to the fact that the integrated circuit design comprises an implicit time side channel in the prior art is solved, and the safety of hardware equipment is improved; meanwhile, the problem of high development cost of an integrated circuit in the prior art is solved, and the method has important practical application value for detecting and eliminating the time channel as early as possible.
Example four
The embodiment of the application provides a computer-readable storage medium, which stores computer-executable instructions for executing the model determination method for integrated circuit design provided by the above embodiment.
Compared with the prior art, the computer-readable storage medium provided by the embodiment of the application determines a gate-level netlist corresponding to an integrated circuit design to be tested, matches the gate-level netlist with a pre-stored model library, determines a plurality of sub-time information flow models, so as to perform connection processing on the plurality of sub-time information flow models based on the connection relationship among a plurality of basic logic units corresponding to the gate-level netlist to obtain a time information flow model for the integrated circuit design, simplifies the generation step of the time flow output model, and simultaneously, by performing connection processing on the plurality of sub-time information flow models including time labels, determines the time information flow model for the integrated circuit design, thereby not only shortening the time for constructing the model for the integrated circuit design, but also providing a judgment standard for the subsequently judged integrated circuit design to process the safety of input signals, whether the hidden time information channel exists in the integrated circuit design to be tested is determined by judging whether the time attribute labels are the same or not, so that the integrated circuit design is improved, the problem that an attacker steals user information by using the undetected information flow channel due to the fact that the integrated circuit design comprises the hidden time side channel in the prior art is solved, and the safety of hardware equipment is improved; meanwhile, the problem of high development cost of an integrated circuit in the prior art is solved, and the method has important practical application value for detecting and eliminating the time channel as early as possible.
The above-described embodiments of the apparatus are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may also be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
One of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
While the preferred embodiments of the present invention have been described, the present invention is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and such equivalent modifications or substitutions are included in the scope of the present invention defined by the claims.
Claims (10)
1. A method for model determination for an integrated circuit design, comprising:
determining a gate-level netlist corresponding to an integrated circuit design to be tested;
matching the gate-level netlist with a pre-stored model library to determine a plurality of sub-time information flow models, wherein the model library comprises a plurality of sub-time information flow models and corresponding query tables, and each query table comprises a corresponding relation between the plurality of sub-time information flow models and the corresponding basic logic unit;
and connecting the plurality of sub-time information flow models based on the connection relation among the plurality of basic logic units in the gate-level netlist to obtain the time information flow model designed for the integrated circuit.
2. The method of claim 1, wherein any of the sub-temporal information flow models comprises an operation rule corresponding to the any of the sub-temporal information flow models, the operation rule being a correspondence between a value of each of the plurality of input signals, an input time attribute label of each of the plurality of input signals, and an output time attribute label of the any of the sub-temporal information flow models output for the plurality of input signals.
3. The method of model determination for an integrated circuit design of claim 2, wherein prior to matching the gate level netlist to a pre-stored model library, the method further comprises:
determining an input time attribute label for each of a plurality of input signals of any of the sub-temporal information flow models;
when determining the respective values of a plurality of input signals of the logic function of the basic logic unit corresponding to any one of the sub-time information flow models, determining a first signal output value of the logic function for the plurality of input signals;
when the value of any input signal in a plurality of input signals input to the sub-time information flow model corresponding to the logic function is changed, determining the sub-time information flow model corresponding to the logic function, and outputting a second signal output value aiming at the input signals;
if the first signal output value is inconsistent with the second signal output value, determining the input signal with the changed value in the input signals as the key input signal corresponding to the sub-time information flow model corresponding to the logic function until a plurality of key input signals of the sub-time information flow model corresponding to the logic function are obtained;
and determining an operation rule corresponding to any sub-time information flow model according to the output time attribute labels output by the any sub-time information flow model aiming at the key input signals based on the respective values of the key input signals and the corresponding input time attribute labels.
4. The method of claims 1-3, wherein the basic logic unit corresponding to any sub-time information flow model comprises at least one of:
and gate, not gate, or gate, flip-flop.
5. The method of claim 1, wherein the matching the gate-level netlist to a pre-stored model library to determine a plurality of sub-time information flow models comprises:
determining model labels of sub-time information flow models respectively matched with a plurality of basic logic units in the gate-level netlist based on the lookup table;
and determining a plurality of sub-time information flow models according to the model labels of the sub-time information flow models respectively matched with the plurality of basic logic units in the gate-level netlist.
6. The method of model determination for an integrated circuit design of claim 1, wherein said determining a gate-level netlist corresponding to an integrated circuit design to be tested comprises at least one of:
determining a gate-level netlist corresponding to an integrated circuit design to be tested according to a current circuit design tool;
and according to a preset interface, acquiring a gate-level netlist file aiming at the integrated circuit design to be tested, and determining a gate-level netlist corresponding to the integrated circuit design to be tested.
7. The method of model determination for an integrated circuit design of claim 1, further comprising:
the integrated circuit design is analyzed in accordance with a time information flow model for the integrated circuit design and a plurality of input conditions, any one of which includes a value of each of the plurality of test input signals and a time attribute label of each of the plurality of test input signals.
8. A model determination apparatus for an integrated circuit design, comprising:
the netlist determining module is used for determining a gate-level netlist corresponding to the integrated circuit design to be tested;
the model matching module is used for matching the gate-level netlist with a pre-stored model library to determine a plurality of sub-time information flow models, the model library comprises a plurality of sub-time information flow models and corresponding query tables, and each query table comprises a corresponding relation between the plurality of sub-time information flow models and the corresponding basic logic units;
and the model determining module is used for connecting the plurality of sub-time information flow models based on the connection relation among the plurality of basic logic units corresponding to the gate-level netlist to obtain the time information flow model designed for the integrated circuit.
9. A terminal, comprising: memory, processor and computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of model determination for an integrated circuit design according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium storing computer-executable instructions for performing the method of model determination for an integrated circuit design of any of claims 1 to 7.
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