CN111221403A - SoC system and method capable of allocating sleep mode control - Google Patents
SoC system and method capable of allocating sleep mode control Download PDFInfo
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- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
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Abstract
The SoC system and the method capable of allocating sleep mode control provided by the embodiment of the invention comprise an execution module, a shallow sleep module, a task dispatching module and an instruction fetching module; when the execution module executes the dormancy instruction, sending a dormancy driving signal; the shallow dormancy module generates a shallow dormancy response signal according to the dormancy driving signal and the task clearing response signal; the instruction fetching module stops the instruction fetching action after receiving the shallow sleep response signal; after receiving the shallow sleep response signal, the execution module stops executing the action after executing the current instruction, so that the SoC system enters a shallow sleep mode. According to the SoC system and the SoC method provided by the embodiment of the invention, whether all current instructions of the processor are executed is ensured by adding the task dispatching module and the shallow sleep module in the processor kernel, so that the processor kernel can safely enter the shallow sleep mode, and the dynamic power consumption and the static power consumption are effectively reduced while the processor kernel is ensured to work correctly.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a system on a chip (SoC) system and a method capable of coordinating sleep mode control.
Background
Microprocessor chips are widely used in a variety of application scenarios, such as: the integrated chip is a core component for information acquisition and network communication of the Internet of things system, and is also an important device for realizing data encryption transmission in a block chain. The microprocessor chip plays a leading role in a specific unit regardless of the field of utilizing the characteristics of data services or the field of ensuring the safe transmission of data.
As one of core devices developed in the information-oriented society, with the progress of manufacturing processes and the improvement of structures, the performance of processor chips has advanced significantly, but the chips have been faced with a great challenge in terms of power consumption. For a number of reasons, the performance of single-core processors has slowed down after undergoing high-speed growth for about ten years, with power consumption becoming one of the major factors affecting and restricting processor development. Too high power consumption can cause multiple problems: high power consumption can result in high cost, affect portability of the device, affect reliability of the processor, etc., while low power consumption is also a requirement for environmental protection. In some specific application scenarios, in order to prolong the working time of the chip and ensure the safe, stable and efficient operation of the system, the power consumption must be reduced as much as possible.
At present, there are various methods for designing low power consumption of a chip, wherein the sleep mode is an effective method for reducing power consumption at the architecture level, that is, the processor enters the sleep mode when the processor is idle. However, this method has the following drawbacks: on one hand, when the instruction is not completely executed, the instruction may be forced to enter a sleep state, so that the processor may have a functional error; on the other hand, by adopting the method for reducing the power consumption, a large number of registers are needed to store information before entering the sleep mode, so that the area of a chip is increased; finally, in the above method, although the core enters the sleep mode to reduce the dynamic power consumption, there is still static power consumption, which in some designs is more than 42% of the whole circuit power consumption in the process below 90 nm.
In view of the above, it is desirable to provide a method for chip low power design, which only enables the processor to enter the sleep mode when the current instruction is determined to be completely executed, so as to prevent the processor from malfunction.
Disclosure of Invention
The embodiment of the invention provides an SoC system and a method capable of being matched with sleep mode control, which are used for solving the defects in the low-power-consumption design of a chip at present.
In a first aspect, an embodiment of the present invention provides an SoC system capable of coordinating sleep mode control, including: the system comprises an execution module, a shallow dormancy module, a task dispatching module and an instruction fetching module, wherein:
the execution module is used for sending a dormancy driving signal to the shallow dormancy module when the executed calling system operation instruction is a dormancy instruction; the shallow dormancy module is used for generating a shallow dormancy response signal according to the dormancy driving signal and a task clearing response signal sent by the task dispatching module, and sending the shallow dormancy response signal to the instruction fetching module and the execution module; the instruction fetching module is used for stopping the instruction fetching action after receiving the shallow sleep response signal; the execution module is further used for stopping executing the action after the current instruction is executed after the shallow sleep response signal is received, so that the SoC system enters a shallow sleep mode.
Further, the task dispatching module is further configured to generate a task clear response signal after the execution module stops executing the action after executing the current instruction.
Furthermore, the SoC system also comprises a programmable interrupt controller arranged in the high-frequency clock area; the programmable interrupt controller is used for generating a first trigger signal and controlling the SoC system to exit a shallow sleep mode.
Furthermore, the SoC system further includes a power management unit disposed in the low frequency clock region; the power management unit is used for receiving a shallow sleep response signal; and if the running state of the SoC system is idle, the power supply of the high-frequency clock area is cut off according to the shallow sleep response signal, so that the SoC system enters a deep sleep mode.
Further, the SoC system further includes a real-time timer disposed in the low-frequency clock region; the real-time timer is used for generating a second trigger signal and controlling the power management unit to operate so that the SoC system exits the deep sleep mode.
Further, the SoC system further includes a high-frequency clock generating module disposed in the high-frequency clock region, and the high-frequency clock generating module is configured to generate a first clock signal; and taking the first clock signal and the light dormancy response signal as the input of the first AND gate, and sending the output of the first AND gate to the instruction fetching module for controlling the instruction fetching module to stop the instruction fetching action after receiving the light dormancy response signal.
Further, the high-frequency clock generating module is further configured to generate a second clock signal; taking the second clock signal as a first input of a second AND gate; taking the shallow sleep response signal output by the shallow sleep module and the task clearing response signal output by the task dispatching module as the input of an OR gate, and taking the output of the OR gate as the second input of a second AND gate; and sending the output of the second AND gate to an execution module, and controlling the execution module to stop executing the action after the execution of the current instruction is finished, so that the SoC system enters a shallow sleep mode.
Further, the task dispatching module comprises a FIFO memory.
In a second aspect, an embodiment of the present invention provides a method for configurable sleep mode control, including: when the executed calling system operation instruction is a sleep instruction, the execution module sends a sleep driving signal to the shallow sleep module; the shallow dormancy module generates a shallow dormancy response signal according to the dormancy driving signal and a task clearing response signal sent by the task dispatching module, and sends the shallow dormancy response signal to the instruction fetching module and the execution module; the instruction fetching module stops the instruction fetching action after receiving the shallow sleep response signal; after receiving the shallow sleep response signal, the execution module stops executing the action after executing the current instruction, so that the SoC system enters a shallow sleep mode.
Further, if the SoC system is idle, the power management unit disposed in the low frequency clock region receives the shallow sleep response signal, and turns off the power of the high frequency clock region according to the shallow sleep response signal, so that the SoC system enters a deep sleep mode.
The SoC system and the method for controlling the configurable sleep mode ensure whether all current instructions of the processor are executed or not by adding the task dispatching module and the shallow sleep module in the processor kernel, so that the processor kernel can safely enter the shallow sleep mode, and the dynamic power consumption and the static power consumption are effectively reduced while the processor kernel is ensured to work correctly.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of an architecture of an SoC system capable of allocating sleep mode control according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a hardware structure of an SoC system capable of coordinating sleep mode control according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating an operation principle of a task dispatch module in an SoC system capable of allocating sleep mode control according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a method for controlling a configurable sleep mode according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a principle of entering a shallow sleep mode of an SoC system capable of being configured with sleep mode control according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides an SoC system capable of allocating sleep mode control, including but not limited to: the system comprises an execution module 1, a shallow dormancy module 2, a task dispatching module 3 and an instruction fetching module 4, wherein: the execution module 1 is used for sending a dormancy driving signal to the shallow dormancy module 2 when the system operation instruction executed by the execution module is a dormancy instruction; the shallow dormancy module 2 is configured to generate a shallow dormancy response signal according to the dormancy driving signal and the task clearing response signal sent by the task dispatching module 3, and send the shallow dormancy response signal to the instruction fetching module 4 and the execution module 1.
Further, the instruction fetching module 4 is configured to stop the instruction fetching after receiving the shallow sleep response signal; the execution module 1 is further configured to stop executing the action after the current instruction is executed after the shallow sleep response signal is received, so that the SoC system enters a shallow sleep mode.
Specifically, as shown in fig. 2, in the SoC system capable of allocating sleep mode control according to the embodiment of the present invention, the whole SoC system can be divided into a high frequency clock region (including a processor core in the high frequency clock region) and a low frequency clock region. The processor core part may include conventional units such as an internal data memory, an internal instruction memory, a decoding module, a write-back module, an IR register, a PC register, and a register set, and also includes an execution module 1, a shallow sleep module 2, a task dispatching module 3, and an instruction fetching module 4. And the peripheral part mainly includes: the system comprises a high-frequency clock generation module (HCLKGEN) located in a high-frequency clock area, a universal serial port controller (UART), a Programmable Interrupt Controller (PIC), Pulse Width Modulation (PWM), an analog-to-digital converter (ADC), a general purpose I/O (general purpose input/output) port (GPIO), a Serial Peripheral Interface (SPI), an external memory (ROM), a JTAG interface, external Flash, a low-frequency clock generation module (LCLKGEN) located in a low-frequency clock area, a Power Management Unit (PMU), a real-time timer (RTC), a Watchdog and the like.
The instruction fetching module 1 is mainly used for reading instructions from an internal instruction memory.
The decoding module is mainly used for translating the instruction sent by the instruction fetching module 1 and acquiring instruction information; and the corresponding data is called from the register group and sent to the task dispatching module 3 and the execution module 1.
The execution module 1 is mainly used for receiving the data transmitted from the decoding module to perform operation, sending the generated execution information to the shallow sleep module 2, and sending the corresponding operation result to the write-back module.
When the decoding module decodes one instruction, a task is dispatched once, namely, the task dispatching module 3 sequentially generates the task dispatching instructions, and when the execution module 1 finishes executing the corresponding instruction, the task delivery is successful. After the delivery of the task, the task is completed.
The shallow sleep module 2 is mainly used for transmitting a sleep driving signal to the shallow sleep module 2 when the execution module 1 finishes executing a sleep instruction. The shallow sleep module 2 feeds back the sleep response signal to the fetch module 4 and the execution module 1. Meanwhile, a task clear signal from the task dispatching module 3 is received, and finally a feedback signal (i.e., a sleep response signal) is output from the core. The write-back module is mainly used for writing back the data result to the register set.
Specifically, the main steps of implementing the configurable sleep mode control in the SoC system provided in the embodiment of the present invention include: task dispatch procedures and shallow sleep control procedures.
Wherein, the task dispatching process is described as follows: when the execution module 1 of the processor executes a sleep instruction in the process of invoking the system operation instruction, the execution module 1 sends a sleep driving signal to the shallow sleep module 2.
The shallow sleep control process is described as follows: when the shallow dormancy module 2 receives the dormancy driving signal, detecting and judging whether the task dispatching module sends a task clearing response signal or not; if the task clearing response signal is received, it can be determined that no instruction is not completed, and at this time, the shallow sleep module generates a sleep response signal.
On one hand, the instruction fetching module 4 is controlled to stop fetching new instructions through the dormancy response signal; on the other hand, the execution module 1 is controlled to stop working after all task instructions in the task dispatching module are executed through the task clearing response signal, and finally the whole SoC system enters a shallow sleep mode. Meanwhile, the light sleep module 2 also uses the generated sleep response signal as the output of the processor core, which indicates that the SoC system has entered the light sleep mode.
The SoC system capable of being controlled by the sleep mode is provided by the embodiment of the invention, whether all current instructions in the task dispatch module 3 of the processor are executed is ensured by adding the task dispatch module and the shallow sleep module in the processor core, so that the processor core can safely enter the shallow sleep mode, and the dynamic power consumption and the static power consumption are effectively reduced while the processor core is ensured to work correctly.
Based on the content of the foregoing embodiment, as an optional embodiment, the task dispatching module 3 is further configured to generate a task empty response signal after the execution module stops executing the action after the execution module finishes executing the current instruction.
Specifically, in the embodiment of the present invention, the task clearing corresponding signal is mainly used for representing that the execution module has executed the current instruction in the task dispatching module 3, and stopping the next execution action.
The SoC system provided by the embodiment of the invention monitors the running state of the current instruction by additionally arranging the task dispatching module, and timely feeds back the monitoring result to the shallow sleep module, so that the distributable sleep mode control of the SoC system is realized through the shallow sleep module.
Based on the content of the foregoing embodiments, as an alternative embodiment, as shown in fig. 2, the SoC system further includes a Programmable Interrupt Controller (PIC) disposed in the high-frequency clock region; the PIC is used for generating a first trigger signal and controlling the SoC system to exit from the shallow sleep mode. Namely: and after the processor core stops working, the shallow sleep module outputs a shallow sleep response signal. If the processor needs to be awakened to start working again, the processor core can be restored to the working state again by interrupting the shallow sleep mode by configuring a PIC (the trigger signal is named as the first trigger signal for distinguishing) which is arranged outside the high-frequency clock area to generate a trigger signal.
According to the SoC system capable of being controlled by the sleep mode in the configurable mode, the PIC is arranged, so that the shallow sleep mode of the SoC system can be stopped in real time according to the actual process requirement, and the adaptability and controllability of the system are effectively improved.
Based on the content of the foregoing embodiment, as an alternative embodiment, as shown in fig. 2, the SoC system further includes a power management unit (PMU for short) disposed in the low-frequency clock region; the PMU is used for receiving the light dormancy response signal; and if the running state of the SoC system is idle, the power supply of the high-frequency clock area is cut off according to the shallow sleep response signal, so that the SoC system enters a deep sleep mode.
The method for turning off the power supply of the high-frequency clock region may be that related software is used to write a value to a specific register of the PMU module to trigger the PMU module to cut off one of the operations of turning off the power supply of the high-frequency clock region when the PMU executes a sequence of sleep instructions, so that the SoC system enters a deep sleep mode. The operation state of the SoC system may be determined based on any means in the prior art, which is not described herein again.
The SoC system provided by the embodiment of the invention realizes the switching of the high-frequency clock region by controlling the PMU module, so as to achieve the purpose of controlling the SoC system to enter the deep sleep mode.
Based on the content of the foregoing embodiment, as an optional embodiment, the SoC system further includes a real time timer (RTC) disposed in the low frequency clock area; the RTC is used for generating a second trigger signal and controlling the PMU to operate so that the SoC system exits the deep sleep mode.
Specifically, in the embodiment of the present invention, the specific control process based on the allocable sleep mode is implemented by the following steps:
step 1, dividing an SoC system into a high-frequency clock area and a low-frequency clock area. The high-frequency clock area provides a clock frequency required by normal operation of the SoC system, and the low-frequency clock area provides a frequency for maintaining a low power consumption mode (namely a shallow sleep mode and a deep sleep mode);
and 4, if the SoC system is idle, configuring a PMU peripheral module of the low-frequency clock to turn off all modules in the whole high-frequency clock area, and entering a deep sleep mode at the moment. Not only can reduce dynamic power consumption, but also can prevent static power consumption from generating;
and 5, monitoring the whole SoC system through the RTC in the low-frequency clock area, and if the SoC system needs to enter the working state again, taking the interruption (namely the second trigger signal) of the RTC as the awakening condition of the deep sleep mode by configuring the PMU.
According to the SoC system provided by the embodiment of the invention, the PMU is regulated and controlled by utilizing the interruption of the RTC, the control of the whole SoC system exiting the deep sleep mode is realized, and the controllability and the adaptability of the whole system are enhanced.
Based on the content of the foregoing embodiment, as an optional embodiment, the SoC system further includes a high-frequency clock generation module (HCLKGEN for short) disposed in the high-frequency clock area, where the HCLKGEN is mainly used to generate the first clock signal; and the first clock signal and the light dormancy response signal are used as the input of the first and gate, and the output of the first and gate is sent to the instruction fetching module 4, so as to control the instruction fetching module 4 to stop the instruction fetching action after receiving the light dormancy response signal.
In the embodiment of the invention, a gating clock is constructed by additionally arranging the first AND gate, so that when a corresponding sleep signal arrives (is set to be 0), the clock cannot enter the instruction fetching module, and the instruction fetching operation is stopped at the moment.
Based on the above description of the embodiment, as an alternative embodiment, HCLKGEN is further configured to generate a second clock signal; and the second clock signal is used as the first input of the second AND gate; taking the shallow sleep response signal output by the shallow sleep module and the task clearing response signal output by the task dispatching module as the input of an OR gate, and taking the output of the OR gate as the second input of the second AND gate; and sending the output of the second AND gate to the execution module, and controlling the execution module to stop executing the action after the execution of the current instruction is finished, so that the SoC system enters a shallow sleep mode.
In the embodiment of the present invention, in order to prevent the processor from having an unexecuted instruction, when the processor needs to enter the shallow sleep state, the execution module 1 cannot be immediately stopped, and only when all tasks in the task dispatching module 3 are completed, that is, the tasks are empty, the execution module 1 can be closed.
Specifically, as shown in fig. 2, after all tasks in the task dispatching module 3 are cleared, a task clear response signal is generated, and meanwhile, the signal in the second formula is gated after passing through an or gate with the sleep response signal generated by the limit sleep module. The output of the or gate and the second clock signal are used as the input of the second and gate, and only when the sleep signal is set to 0 and the task clearing signal is set to 0, the execution module is also closed by the second gating clock (the second and gate), so that the processor enters the shallow sleep mode. And the shallow sleep module outputs a signal that the processor enters into shallow sleep after simultaneously receiving the sleep driving signal and the task clearing response signal.
Further, the task dispatch module 3 may comprise a FIFO memory in embodiments of the invention. As shown In fig. 3, the FIFO (First-In and First-Out) memory is a First-In First-Out memory, and is divided into a write-only area and a read-only area. The read operation and the write operation can be performed asynchronously, and the data written on the write area is read from the area at the read end in the order of writing, similar to a buffer that absorbs the speed difference between the write end and the read end.
Therefore, the specific execution process of the processor core can be realized by the following steps:
step 1, continuously fetching an instruction from an internal instruction memory by an instruction fetching module 4, storing a current instruction in an IR register, and storing a current address in a PC register;
step 4, the execution module 1 receives the operation tasks assigned by the task dispatching module 3, meanwhile, after each instruction is executed, the execution module regards as delivering a task once, and sends a task delivering signal to the task dispatching module 3;
step 5, the task dispatching module 3 removes the corresponding task information from the FIFO memory each time receiving a task delivery signal;
and 6, writing the executed result back to the register group by the write-back module.
The task dispatching mechanism adopted in the embodiment can ensure the correctness of the functions of the processor, and simultaneously can reduce registers for storing information, thereby greatly reducing the area.
An embodiment of the present invention provides a method for configurable sleep mode control, as shown in fig. 4, including but not limited to the following steps:
step S1, when the invoking system operation instruction executed by the execution module 1 is a hibernation instruction, the execution module sends a hibernation driving signal to the shallow hibernation module 2;
step S2, the shallow sleep module 2 generates a shallow sleep response signal according to the sleep driving signal and the task clearing response signal sent by the task dispatching module 3, and sends the shallow sleep response signal to the instruction fetching module 4 and the execution module 1;
step S3, the instruction fetching module 4 stops the instruction fetching operation after receiving the shallow sleep response signal;
in step S4, after receiving the shallow sleep response signal, the execution module 1 stops executing the current instruction, so that the SoC system enters the shallow sleep mode.
Further, if the running state of the SoC system is idle, the power management unit disposed in the low-frequency clock region receives the shallow sleep response signal, and turns off the power of the high-frequency clock region according to the shallow sleep response signal, so that the SoC system enters a deep sleep mode.
Specifically, as shown in fig. 5, on the basis of the foregoing embodiment, with the mechanism based on task scheduling provided in the embodiment of the present invention, a specific process of the processor core entering the shallow sleep mode may be implemented by the following steps:
step 1, after executing a sleep instruction, an execution module 1 sends a sleep driving signal (0 signal) to a shallow sleep module 2;
step 4, after the instruction fetching module 4 stops working, no instruction fetching operation is carried out, and then no task is dispatched;
and step 5, in order to prevent the processor from having an unexecuted instruction, the execution module 1 continues to execute, namely continues to deliver the task.
Step 6, the execution module 1 finishes executing all instructions in the task dispatching module 3, namely all tasks are delivered;
and 7, the task dispatching module 3 outputs a task clearing response signal (0 signal) to the shallow sleep module 2.
Step 8, outputting the task clearing response signal and the sleep response signal which are simultaneously output through an OR gate, wherein the output signal is 0 (when the sleep response signal is a 0 signal and the task clearing response signal is a 0 signal);
step 9, gating a second clock signal of the execution module 1 and a signal output by the or gate, and inputting the gated second clock signal to the second gating module, wherein the output signal of the second gating module is 0, and at this time, the clock cannot enter the execution module 1;
step 10, the execution module 1 stops working, and other modules of the processor core also stop working in sequence, so that the dynamic power consumption of the processor core is greatly reduced;
and 11, after the processor core stops working, the shallow sleep module outputs a shallow sleep response signal. Further, if the processor needs to be awakened to work again, the peripheral PIC can be configured to trigger the interrupt to enter the working state.
Further, an embodiment of the present invention further provides a method for controlling an SoC system to enter a deep sleep mode based on an allocable sleep mode, where a specific process of the method may be implemented by the following steps:
step 1, setting an SoC system into a high-frequency clock area and a low-frequency clock area, wherein the high-frequency clock area provides clock frequency required by normal work, and the low-frequency clock area provides frequency for maintaining a low power consumption mode;
and 4, if the SoC system is idle, configuring a PMU peripheral module of the low-frequency clock to turn off all modules of the whole high-frequency clock area, and entering a deep sleep mode at the moment. Not only can reduce dynamic power consumption, but also can prevent static power consumption from generating;
step 5, the whole SoC system is monitored by the RTC of the low-frequency clock area; if it is desired to re-enter the active state, the PMU may be configured to use the RTC interrupt as a wake-up condition.
According to the SoC method capable of being controlled by the sleep mode, the task dispatching module and the shallow sleep module are added in the processor core to ensure whether all current instructions of the processor are executed completely or not, so that the processor core can safely enter the shallow sleep mode, and dynamic power consumption and static power consumption are effectively reduced while the processor core is ensured to work correctly. Furthermore, the chip can be adjusted to enter a shallow sleep mode or a deep sleep mode according to the requirement, so that the safety of the processor is ensured, and the power consumption is further reduced.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A SoC system configurable for sleep mode control, comprising: the system comprises an execution module, a shallow dormancy module, a task dispatching module and an instruction fetching module;
the execution module is used for sending a dormancy driving signal to the shallow dormancy module when the system operation instruction executed by the execution module is a dormancy instruction;
the shallow sleep module is used for generating a shallow sleep response signal according to the sleep driving signal and a task clearing response signal sent by the task dispatching module, and sending the shallow sleep response signal to the instruction fetching module and the execution module;
the instruction fetching module is used for stopping instruction fetching after receiving the shallow sleep response signal;
the execution module is further configured to stop executing the action after the execution of the current instruction is completed after receiving the shallow sleep response signal, so that the SoC system enters a shallow sleep mode.
2. The SoC system with configurable sleep mode control as recited in claim 1, wherein the task dispatch module is further configured to generate the task clear response signal after the execution module stops executing the action after the execution module completes execution of the current instruction.
3. The system in a SoC of claim 1, further comprising a programmable interrupt controller disposed in a high frequency clock domain;
the programmable interrupt controller is used for generating a first trigger signal and controlling the SoC system to exit the shallow sleep mode.
4. The system on a chip (SoC) with configurable sleep mode control of claim 1, further comprising a power management unit disposed in a low frequency clock region;
the power management unit is used for receiving the shallow sleep response signal;
and if the running state of the SoC system is idle, the power supply of a high-frequency clock area is turned off according to the shallow sleep response signal, so that the SoC system enters a deep sleep mode.
5. The system on a chip (SoC) with configurable sleep mode control of claim 4, further comprising a real-time timer located in a low frequency clock zone;
the real-time timer is used for generating a second trigger signal and controlling the power management unit to operate so that the SoC system exits the deep sleep mode.
6. The system on a SoC of claim 1, further comprising a high frequency clock generation module disposed in the high frequency clock region, the high frequency clock generation module configured to generate a first clock signal;
and taking the first clock signal and the shallow sleep response signal as the input of a first AND gate, and sending the output of the first AND gate to the instruction fetching module for controlling the instruction fetching module to stop the instruction fetching action after receiving the shallow sleep response signal.
7. The system on a chip (SoC) of claim 6, wherein the high frequency clock generation module is further configured to generate a second clock signal;
taking the second clock signal as a first input of a second AND gate;
taking the shallow sleep response signal output by the shallow sleep module and the task clearing response signal output by the task dispatching module as the inputs of an OR gate, and taking the output of the OR gate as the second input of the second AND gate;
and sending the output of the second AND gate to the execution module, and controlling the execution module to stop executing the action after the execution of the current instruction is finished, so that the SoC system enters a shallow sleep mode.
8. The SoC system that can coordinate sleep mode control of claim 1, wherein the task dispatch module comprises a FIFO memory.
9. A method of configurable sleep mode control, comprising:
when the executed calling system operation instruction is a sleep instruction, the execution module sends a sleep driving signal to the shallow sleep module;
the shallow dormancy module generates a shallow dormancy response signal according to the dormancy driving signal and a task clearing response signal sent by the task dispatching module, and sends the shallow dormancy response signal to the instruction fetching module and the execution module;
the instruction fetching module stops instruction fetching after receiving the shallow sleep response signal;
and after receiving the shallow sleep response signal, the execution module stops executing the action after finishing executing the current instruction so as to enable the SoC system to enter a shallow sleep mode.
10. The method of tailorable sleep mode control according to claim 9,
and if the running state of the SoC system is idle, a power management unit arranged in a low-frequency clock area receives the shallow sleep response signal and turns off a power supply of a high-frequency clock area according to the shallow sleep response signal so as to enable the SoC system to enter a deep sleep mode.
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