CN111220906A - Apparatus and method for error detection and correction involving linear analog circuits - Google Patents

Apparatus and method for error detection and correction involving linear analog circuits Download PDF

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CN111220906A
CN111220906A CN201911189316.9A CN201911189316A CN111220906A CN 111220906 A CN111220906 A CN 111220906A CN 201911189316 A CN201911189316 A CN 201911189316A CN 111220906 A CN111220906 A CN 111220906A
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analog
circuit
linear
circuitry
signal
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简-彼得·斯考特
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NXP BV
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits
    • G01R31/3161—Marginal testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/316—Testing of analog circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1071—Measuring or testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test

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  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

An apparatus includes a linear analog circuit and a data checking circuit. The linear analog circuit receives an analog input signal and provides a processed analog output signal. The linear analog circuit includes: voltage change circuitry and voltage impedance circuitry that perform processing of the analog input signal by the linear analog circuit; and an analog test bus circuit (ATB) that selectively passes different ones of the plurality of input ports to at least one output port. A data checking circuit is communicatively coupled to the ATB and includes a data processing circuit that detects errors communicated by the linear analog circuit by: applying a control signal to cause the ATB to selectively pass the different ones of the plurality of input ports while the linear analog circuit and the data inspection circuit facilitate testing of the linear analog circuit.

Description

Apparatus and method for error detection and correction involving linear analog circuits
Technical Field
Aspects of the various embodiments relate to an apparatus and method for detecting and correcting errors of a linear analog circuit.
Background
Various tests may be used to detect and correct faults in analog and/or mixed signal circuits. Such testing may require the addition of hardware and may affect the operational and layout requirements of the circuitry.
These and other problems have presented challenges to the efficiency of error detection and correction in linear analog circuit implementations for various applications.
Disclosure of Invention
Various example embodiments are directed to the problems identified above and/or other problems that may become apparent from the following disclosure regarding detecting and correcting errors in linear analog circuits.
In certain example embodiments, aspects of the present disclosure relate to an analog test bus circuit (ATB) positioned on a linear analog circuit for detecting and correcting errors communicated by the linear analog circuit using control signals to cause the ATB to selectively pass different outputs of (internal) nodes of the linear analog circuit to a data inspection circuit. The data checking circuit facilitates testing of the linear analog circuit, including facilitating analog checksum testing, built-in self-test (BIST), and/or built-in fault injection testing (BIFI), without adding additional circuitry to the linear analog circuit.
In a more particular example embodiment, an apparatus includes a linear analog circuit and a data check circuit that may form part of a discrete circuit or an Integrated Circuit (IC). The linear analog circuit receives an analog input signal and provides a processed analog output signal. The linear analog circuit includes voltage change circuitry, voltage impedance circuitry, and an ATB. The voltage change circuitry and the voltage impedance circuitry collectively perform processing of the analog input signal by the linear analog circuit. As can be appreciated and as described further herein, the voltage change circuitry includes linear circuit elements (e.g., resistors and amplifiers) that do not carry state and therefore do not store energy, and the (linear) voltage impedance circuitry is a state-carrying circuit element that stores energy, such as capacitors, inductors, and/or other circuits that store energy. For example, (linear) voltage change circuitry modulates analog input signals provided at a plurality of voltage nodes and provides the modulated analog signals at the output of the voltage change circuitry. (linear) voltage impedance circuitry comprising capacitive circuitry blocks the modulated analog signal and provides a blocked modulated analog signal at an output of the voltage impedance circuitry. The ATB includes a plurality of input ports that selectively pass different ones of the plurality of input ports to at least one output port, wherein the input ports are connected to the voltage change circuitry and the voltage impedance circuitry. As described further herein, the ATB may selectively output processed analog output signals associated with one (internal) node of the voltage altering circuitry and the voltage resistive circuitry at a time.
The data checking circuit may facilitate at least two of the following tests: analog checksum test, BIST, and BIFI. In some embodiments, the data checking circuitry facilitates each of the analog checksum test, the BIST, and the BIFI. For example, the linear analog circuit and the data check circuit collectively facilitate performing testing on the linear analog circuit by testing for parametric faults and transient faults by means of each of the analog checksum test, the BIST, and the BIFI. In other embodiments, the linear analog circuit and the data checking circuit collectively facilitate testing of the linear analog circuit by processing signals using an analog-to-digital converter (ADC) and the data processing circuit through an algorithm that facilitates only one of the BIST and the analog checksum test or at least one of the BIST and the BIFI in response to the analog checksum test detecting an error.
In various embodiments, the data checking circuit additionally includes an ADC and/or a digital-to-analog converter (DAC). An ADC may be used to facilitate BIST and a DAC may be used to facilitate BIFI. Additionally, the apparatus may include BIST circuitry to perform BIST and/or BIFI circuitry to perform BIFI, where the data check circuitry performs analog checksum testing (which may optionally be concurrent with the application mode) and facilitates BIST and BIFI.
In various embodiments, when the linear analog circuit and the data check circuit perform a test on the linear analog circuit, such as performing an analog checksum test, the linear analog circuit may receive an analog input signal (e.g., a voltage signal) and provide a processed analog output signal. The linear analog circuit may provide a processed analog output signal during an application mode of the device and while the linear analog circuit and the data check circuit perform a test on the linear analog circuit.
The linear analog circuit and the data checking circuit may collectively perform a test on the linear analog circuit for low frequency signals received by the ATB with respect to a sampling frequency capacity of the ADC by: the method includes processing sequentially received signals using a data processing circuit through a quasi-parallel processing algorithm and estimating and canceling time delays associated with different internal nodes of a linear analog circuit, and simulating therein tests of probes to the different internal nodes concurrently or simultaneously. In other embodiments and/or additionally, the linear analog circuit and the data checking circuit collectively perform testing on the linear analog circuit by: the ADC and the data processing circuit are undersampled and wherein voltage differences between signals at the plurality of internal nodes are estimated. Additionally, the model of the linear analog circuit used in the analog processing algorithm of the data inspection circuit may include a selective time delay in the signal driving the ATB to offset the signal offset. For example, the linear analog circuit and the data inspection circuit may collectively perform a test on the linear analog circuit by processing the signals using the ADC and the data processing circuit through an algorithm configured to model a time delay for cancelling a signal offset in the respective signals directed toward the ATB.
The ATB may access the linear analog circuit by passing analog values (e.g., voltage or current) to and from the linear analog circuit. In various embodiments, the data checking circuit additionally includes a DAC communicatively positioned between the data processing circuit and the ATB. The DAC may send a correction signal to the linear analog circuit in response to the detected error communicated by the linear analog circuit.
In more particular embodiments, the apparatus includes a plurality of linear analog circuits. For example, the apparatus additionally comprises at least one further linear analog circuit providing a processed analog output signal. The at least one further linear analog circuit comprises: another voltage modification circuitry and another voltage impedance circuitry that collectively perform processing of the analog input signal by the other linear analog circuit; and another ATB, the ATB including a plurality of input ports, the ATB selectively passing different ones of the plurality of input ports to at least one output port. The apparatus additionally includes a central ATB that receives signals provided from each of the linear analog circuits and transmits signals toward the data checking circuit, the linear analog circuits including the first-recited linear analog circuit and the at least one additional linear analog circuit. The data checking circuit may perform testing on each of the linear analog circuit and the at least one further linear analog circuit by running a simulated checksum test on each of the linear analog circuit and the at least one further linear analog circuit, respectively.
Another particular example embodiment relates to a method of using the apparatus described above. The method may include: receiving an analog input signal at a linear analog circuit and providing a processed analog output signal, the linear analog circuit comprising: voltage change circuitry and voltage impedance circuitry that collectively perform processing of the analog input signal by the linear analog circuit; and an ATB, the ATB including a plurality of input ports. The method additionally comprises: modulating the analog input signals provided at a plurality of voltage nodes of the voltage change circuitry and providing modulated analog signals at an output of the voltage change circuitry; blocking the modulated analog signal by the voltage impedance circuitry including capacitive circuitry and providing a blocked modulated analog signal at an output of the voltage impedance circuitry. In addition, the method comprises: driving, by the output of the voltage change circuitry, an input of voltage impedance circuitry and one of the plurality of input ports of the ATB and driving, by the output of the voltage impedance circuitry, another one of the plurality of input ports of the ATB; and selectively passing a different input port of the plurality of input ports to at least one output port of the ATB in response to a control signal. And detecting errors communicated by the linear analog circuit by a data check circuit by: applying the control signal to cause the ATB to selectively pass the different ones of the plurality of input ports (and/or to pass an error correction signal to a respective state-carrying element such as a capacitor or resistor) while the linear analog circuit and the data checking circuit perform a test on the linear analog circuit, the data checking circuit including an ADC communicatively coupled to the at least one output port of the analog test bus circuit and including a data processing circuit.
In various embodiments, the method comprises: providing the processed analog output signal during an application mode of the device and while the linear analog circuit and the data checking circuit perform a test on the linear analog circuit. Detecting the error conveyed by the linear analog circuit may include comparing data indicative of the modulated analog signal and the impeded analog signal to one or more expected values. And, in a particular embodiment, the method additionally comprises: sending a correction signal to the linear analog circuit through a DAC in response to the detected error communicated by the linear analog circuit, the DAC communicatively positioned between the data processing circuit and the ATB.
The above discussion/summary is not intended to describe each embodiment or every implementation of the present disclosure. The figures and detailed description that follow also illustrate various embodiments.
Drawings
Various exemplary embodiments may be more completely understood when the following detailed description is considered in conjunction with the following drawings, in which:
FIG. 1 illustrates an example apparatus for detecting errors conveyed by a linear analog circuit in accordance with this disclosure;
FIG. 2 illustrates another example apparatus for detecting errors conveyed by a linear analog circuit in accordance with this disclosure;
FIG. 3 illustrates an example apparatus for detecting and correcting errors conveyed by a linear analog circuit in accordance with this disclosure;
FIG. 4 is a graph illustrating an analog signal in an example test facilitated by an apparatus according to the present disclosure;
FIG. 5 is a graph illustrating an analog signal in an example test facilitated by an apparatus according to the present disclosure;
FIG. 6 illustrates a model of an example apparatus for computing properties of a data inspection circuit for detecting and correcting errors conveyed by a linear analog circuit using modeled delays in accordance with this disclosure;
7A-7B are graphs illustrating analog signals in an example test facilitated by an apparatus according to the present disclosure; and is
FIG. 8 illustrates an example apparatus for detecting errors conveyed by more than one linear analog circuit in accordance with this disclosure.
While the various embodiments discussed herein may take modifications and alternative forms, various aspects of the various embodiments have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure, including aspects defined in the claims. Additionally, as used throughout this application, the term "example" is merely illustrative and not limiting.
Detailed Description
It is believed that aspects of the present disclosure are applicable to a variety of different types of devices, systems, and methods involving detecting and optionally correcting faults in linear analog circuits. In certain embodiments, it has been shown that aspects of the present disclosure are beneficial when used in the context of detecting errors conveyed by linear analog circuits using analog test bus circuits (ATBs) positioned on the linear analog circuits by using control signals to cause the ATBs to selectively pass different voltages or currents of internal nodes of the linear analog circuits. In some embodiments, the data check circuit may communicate with the linear analog circuit with the ATB to facilitate testing of the linear analog circuit without adding additional circuitry to the linear analog circuit, the testing including two or more of a built-in self-test, a simulated checksum test, and a built-in fault injection test. While not necessarily so limited, various aspects may be appreciated from the following discussion of non-limiting examples using an illustrative context.
Thus, in the following description, numerous specific details are set forth to describe specific examples presented herein. It should be apparent, however, to one skilled in the art that one or more other examples and/or variations of these examples may be practiced without all of the specific details set forth below. In other instances, well-known features have not been described in detail so as not to obscure the description of the examples herein. For purposes of illustration, the same reference numbers may be used in different drawings to identify the same element or additional instances of the same element. Also, while aspects and features may in some cases be described in separate drawings, it should be understood that features of one drawing or embodiment may be combined with features of another drawing or embodiment, even if the combinations are not explicitly shown or explicitly described as a combination.
A variety of different tests may be used to detect faults in analog and/or mixed signal circuits. A system using analog checksum testing may detect and correct faults in analog and/or mixed signal circuits. When the checksum mechanism runs concurrently with the application mode, it can detect both permanent faults and transient faults. Another way to detect faults in analog and/or mixed signal circuits is built-in self test (BIST). When operating intermittently with the application mode, it may test the circuit under various conditions (e.g., maximum supply voltage and minimum supply voltage). The BIST may detect some faults that the checksum mechanism may not be able to detect. However, in contrast to analog checksum testing, transient faults cannot be detected using BIST. The analog checksum test and BIST may complement each other in detecting hard defects (hard defects) that may be caused by aging and in detecting parameter deviations that may be caused by slow-activating latent defects. As a specific example, the analog checksum test may detect "how much the analog block deviates from its implemented function? ", and the BIST can detect" is the analog block still meeting the specification? "
To obtain more complete fault coverage, built-in fault injection testing (BIFI) may additionally or alternatively be used. In test mode, the BIFIs temporarily inject faults at different internal nodes of the linear analog circuit in order to verify that the analog checksum test and BIST are working properly. The analog checksum test, BIST, and BIFI may be complementary to each other. Embodiments in accordance with the present disclosure are directed to an apparatus comprising a linear analog circuit in communication with a data inspection circuit that performs analog checksum testing and facilitates combining the three test methods without requiring any modification to the linear analog circuit itself and with minimal hardware overhead. In particular embodiments, the apparatus may achieve and provide high diagnostic coverage (e.g., 99% coverage for ASIL D according to the Institute of Electrical and Electronics Engineers (IEEE) international organization for standardization (ISO)26262 standard) in a linear analog circuit, including transient faults and parametric faults that are difficult to detect.
According to various embodiments, a device using analog checksum testing may achieve nearly the same level of fault detection and correction as that of dual or triple redundancy, while using only a fraction of the area and power overhead of dual or triple redundancy. To calculate the analog checksum, in various embodiments, the linear analog circuit is not modified (e.g., no additional hardware is required) as long as some internal nodes of the analog/mixed-signal block can be detected. This is often the case for many applications, such as for safety-related ICs, since linear analog circuits may be equipped with analog test bus circuits (ATBs) used in production testing. The checksum calculation and comparison is performed by a simple linear analog circuit.
Particular embodiments relate to an apparatus that includes a linear analog circuit and a data checking circuit that may form part of a discrete circuit or an Integrated Circuit (IC). The linear analog circuit receives an analog input signal and provides a processed analog output signal. For example, the linear analog circuit includes voltage change circuitry, voltage impedance circuitry, and an ATB. The voltage change circuitry and the voltage impedance circuitry collectively perform processing of the analog input signal by the linear analog circuit. The ATB includes a plurality of input ports that selectively pass different ones of the plurality of input ports to at least one output port, wherein the input ports are connected to the voltage change circuitry and the voltage impedance circuitry. The voltage change circuitry modulates analog input signals provided at a plurality of voltage nodes and provides the modulated analog signals at an output of the voltage change circuitry. Voltage impedance circuitry including capacitive circuitry blocks the modulated analog signal and provides the blocked modulated analog signal at an output of the voltage impedance circuitry. As described further herein, the ATB may selectively output the processed analog output signal associated with one internal node of the voltage altering circuitry and the voltage impedance circuitry (which includes the voltage node) at a time.
The data checking circuit may facilitate one or more tests, including one, two, or all of an analog checksum test, a BIST, and a BIFI. In various embodiments, the data inspection circuit additionally includes an analog-to-digital converter (ADC) and/or a digital-to-analog converter (DAC). An ADC may be used to facilitate BIST and a DAC may be used to facilitate BIFI. For example, the DAC is communicatively positioned between the data processing circuit and the ATB and sends a correction signal to the linear analog circuit in response to a detected error communicated by the linear analog circuit. In various embodiments, when a linear analog circuit and a data check circuit perform a test on the linear analog circuit, the linear analog circuit receives an analog (e.g., voltage or current) signal and provides a processed analog output signal. For example, the linear analog circuit may provide a processed analog output signal during an application mode of the device and while the linear analog circuit and the data check circuit perform a test on the linear analog circuit.
In particular embodiments, the linear analog circuit and the data checking circuit collectively perform a test on the linear analog circuit for low frequency signals received by the analog test bus circuit relative to a sampling frequency capability of the ADC by: the method includes processing sequentially received signals using a data processing circuit through a quasi-parallel processing algorithm and estimating and canceling time delays associated with different internal nodes of a linear analog circuit, and simulating therein tests of probes to the different internal nodes concurrently or simultaneously. However, embodiments are not limited to low frequency signals. In other embodiments, the linear analog circuit and the data check collectively perform a test on the linear analog circuit for signals received by the ATB and having a cycle length approximately corresponding to the sampling frequency capacity of the ADC by: the ADC and the data processing circuit are undersampled and wherein voltage differences between signals at the plurality of internal nodes are estimated. Alternatively and/or additionally, the data checking circuit and the linear analog circuit collectively perform a test on the linear analog circuit by processing the signals using the ADC and the data processing circuit through an algorithm that models a time delay in the respective signals directed toward the ATB to cancel the signal offset.
In various embodiments, the apparatus may additionally include BIST circuitry and/or BIFI circuitry to perform BIST and BIFI, respectively. BIST may be facilitated by the ADC of the data inspection circuit and BIFI may be facilitated by the DAC of the data inspection circuit. The data checking circuit may facilitate all, two, or only one of these tests.
In various embodiments, the apparatus additionally includes at least one additional linear analog circuit that provides a processed analog output signal. The at least one further linear analog circuit comprises: another voltage modification circuitry and another voltage impedance circuitry that collectively perform processing of the analog input signal by the other linear analog circuit; and another ATB, the ATB including a plurality of input ports, the ATB selectively passing different ones of the plurality of input ports to at least one output port. The apparatus additionally includes a central ATB that receives signals provided from each of the linear analog circuits and transmits signals toward the data checking circuit, the linear analog circuits including the first-recited linear analog circuit and the at least one additional linear analog circuit. The data checking circuit may perform testing on each of the linear analog circuits by running a sequential analog checksum test on each of the linear analog circuit and the at least one additional linear analog circuit, respectively.
Various other embodiments are directed to methods of using the apparatus described above. The method may include: an analog input signal is received at a linear analog circuit and a processed analog output signal is provided. As described above, the linear analog circuit includes: voltage change circuitry and voltage impedance circuitry that collectively perform processing of the analog input signal by the linear analog circuit; and an ATB, the ATB including a plurality of input ports. The method additionally comprises: modulating the analog input signals provided at a plurality of voltage nodes of the voltage change circuitry and providing modulated analog signals at an output of the voltage change circuitry; blocking the modulated analog signal by the voltage impedance circuitry including capacitive circuitry and providing a blocked modulated analog signal at an output of the voltage impedance circuitry. In addition, the method comprises: driving, by the output of the voltage change circuitry, an input of voltage impedance circuitry and one of the plurality of input ports of the ATB and driving, by the output of the voltage impedance circuitry, another one of the plurality of input ports of the analog test bus circuit; and selectively passing a different input port of the plurality of input ports to at least one output port of the ATB in response to a control signal. And detecting errors communicated by the linear analog circuit by a data check circuit by: applying the control signal to cause the ATB to selectively pass the different ones of the plurality of input ports (and/or to pass an error correction signal to a respective state-carrying element such as a capacitor or resistor) while the linear analog circuit and the data checking circuit perform a test on the linear analog circuit, the data checking circuit including an ADC communicatively coupled to the at least one output port of the ATB and including a data processing circuit.
In various specific embodiments, the method further comprises: providing the processed analog output signal during an application mode of the device and while the linear analog circuit and the data checking circuit perform a test on the linear analog circuit. Detecting the error conveyed by the linear analog circuit may include comparing data indicative of the modulated analog signal and the impeded analog signal to one or more expected values. And, in a particular embodiment, the method additionally comprises: sending a correction signal to the linear analog circuit through a DAC in response to the detected error communicated by the linear analog circuit, the DAC communicatively positioned between the data processing circuit and the analog test bus circuit.
Turning now to the drawings, FIG. 1 illustrates an example apparatus for detecting errors conveyed by a linear analog circuit according to this disclosure. The apparatus 100 facilitates testing of the linear analog circuit 102 by performing analog checksum testing during the application mode and facilitating combination of analog checksum testing with BIST and/or BIFI (for ease of reference, the linear analog circuit 102 is referred to herein as "analog circuit 102").
As shown, the apparatus 100 includes an analog circuit 102 and a data checking circuit 104. As can be appreciated, the analog circuit 102 has voltage altering circuitry and voltage reactance circuitry 106 that collectively perform processing of the analog input signal by the analog circuit 102. The voltage change circuitry modulates analog input signals provided at a plurality of voltage nodes and provides the modulated analog signals at an output of the voltage change circuitry. For example, the voltage change circuitry comprises (linear) circuit elements which do not carry states and therefore do not store energy. Example voltage change circuitry includes a resistor and an amplifier. The voltage impedance circuitry includes capacitive circuitry that blocks the modulated analog signal and provides a blocked analog signal at an output of the voltage impedance circuitry. Voltage impedance circuitry is state-carrying (linear) circuit elements that store energy, such as capacitors, inductors, and other circuits that store energy. The circuitry of analog circuit 102 may include various linear analog circuitry with various components.
The apparatus 100 includes an analog circuit 102, the analog circuit 102 having an ATB108, the ATB108 for extracting (tapout) an internal voltage V from voltage change circuitry and voltage reactance circuitry 106 (e.g., amplifiers, resistors, and capacitors)CAnd VR. The ATB108 includes a plurality of input ports and is configured and arranged to selectively pass different ones of the plurality of input ports to at least one output port. For example, one or more outputs of the voltage change circuitry drive an input of the voltage impedance circuitry and one of the plurality of input ports of the ATB108, and one or more outputs of the voltage impedance circuitry drive another of the plurality of input ports of the analog test bus circuit. The ATB108 may access the analog circuit by passing an analog value (e.g., a voltage or current) to the analog circuit 102 and passing the analog value from the analog circuit 102.
More specifically, the ATB108 may be used for production testing and may allow one internal node to be selected at a time from a plurality of internal nodes of the voltage altering circuitry and voltage resistive circuitry 106. Since the calculation of the analog checksum test requires that all voltages V be appliedRAnd VCAvailable simultaneously, so some action can be taken to achieve this goal or to achieve the same checksum as if V could be obtained in parallelRAnd VCAs such, as otherwise described herein at least in connection with fig. 2.
The data checking circuit 104 provides testing of the analog circuit 102 during the application mode, wherein the diagnostic coverage of the testing is high for functional safety. In a particular embodiment, the analog circuit 102 receives an analog input signal (e.g., a voltage signal) and provides a processed analog output signal when the analog circuit and the data check circuit perform a test on the analog circuit. The data check circuit 104 is communicatively coupled to the at least one output port of the ATB 108. The data checking circuit 104 comprises a data processing circuit 103, said data processing circuit 103 being adapted to detect errors transmitted by the analog circuit 102 by: the control signals are applied when the analog circuit 102 and the data check circuit 104 perform testing on the analog circuit 102 to cause the ATB108 to selectively pass different ones of the plurality of input ports (e.g., pass different voltages or currents of internal nodes of the analog circuit 102).
The data inspection circuit 104 may facilitate at least two of the following tests to provide testing of the analog circuit: BIST, analog checksum test during application mode, and BIFI. In a particular embodiment, the data checking circuit facilitates each of the analog checksum test, the BIST, and the BIFI. As described further herein, the data check circuit 104 may perform analog checksum testing and may facilitate one or more tests of BIST and BIFI.
In particular embodiments, data inspection circuit 104 additionally includes an ADC and/or a DAC, as otherwise described herein. An ADC may be used to facilitate BIST and a DAC may be used to facilitate BIFI. In such embodiments, device 100 may additionally include BIST circuitry for performing BIST and BIFI circuitry for performing BIFI, where data check circuit 104 performs analog checksum testing (during application mode) and facilitates BIST and BIFI. Data checking circuitry 104 may be used to evaluate BIST circuitry and/or BIFI circuitry and/or results provided therefrom. In such embodiments, the analog circuitry 102 and the data inspection circuitry 104 collectively facilitate testing of the analog circuitry by testing for parametric faults and transient faults by means of each of the following tests: BIST, BIFI, and analog checksum testing. However, embodiments are not so limited and may include facilitating one of the tests, two of the tests, or all three of the tests. In some particular embodiments, and by way of example, the data processing circuit 103 may process the signals through an algorithm configured to facilitate at least one of BIST and BIFI testing and analog checksum testing.
In various embodiments, the analog circuit 102 and the data check circuit 104 collectively perform testing of the analog circuit 102 for low frequency signals received by the ATB108 with respect to the sampling frequency capability of the ADC by: the data processing circuit 103 is used to process the sequentially received signals through a quasi-parallel processing algorithm and to estimate and cancel time delays associated with different internal nodes of the analog circuit, and to simulate therein testing of probes to the different internal nodes concurrently or simultaneously. However, embodiments are not so limited, and the data inspection circuit 104 may not include or use an ADC and may perform analog checksum testing in analog form, such as for high frequency signals received by the test ATB 108. In other embodiments, the analog circuit 102 and the data check circuit 104 collectively perform testing of the analog circuit 102 by: the ADC and data processing circuit 103 is down-sampled and therein voltage differences between the signals at the plurality of internal nodes of the analog circuit 102 are estimated. In further embodiments, the analog circuitry 102 and the data check circuitry 104 collectively perform testing on the analog circuitry 102 by: the signals are processed using the ADC and data processing circuit 103 through algorithms that model the time delays in the respective signals directed toward the ATB108 to cancel the signal offset.
In various embodiments, the DAC is communicatively positioned between the data processing circuit 103 of the data inspection circuit 104 and the ATB 108. As described further herein, the DAC may be used to send a correction signal to the analog circuit 102 in response to a detected error communicated by the analog circuit 102.
For clarity, the checksum theory for field detection of faults is described, and for better understanding, the description starts with a digital checksum. The checksum of the digital linear circuit (e.g., filter) may be implemented as any linear circuit, which may be implemented as a Moore Machine. Such a mole machine consists of combinational logic and state memory (e.g., flip-flops, latches, or RAM cells). For more general and specific information on the checksum test, refer to "design of fault-tolerant linear digital state variable system" by Abhijit Chatterjee, manual A.d' Abreu: theories and Techniques (The Design of Fault-Tower Linear State variable systems: The Theory and Techniques) ", IEEE computer Integrated services (IEEE Transactions on computers), Vol.42, No. 7, p.1993, p.794-.
In each clock cycle N, the input data i (N) and the state data S (N) are processed in combinational logic, resulting in output data y (N) and a new state S (N +1) for the next cycle. Each of the values I, S and Y may be a single signal or a vector of multiple single signals. The state memory is clocked and captures its input S (N +1) in each clock cycle, outputting it in the form of S (N). In addition, two checksums c1(N) and c2(N) are calculated in each clock cycle N. The checksum c1(N) is calculated from the state S (N) and the input I (N). The checksum c2(N) is calculated based only on the state s (N).
As can be appreciated, the way to calculate c1 and c2 is: c1(N) is a prediction of c2(N +1) such that in a fault-free linear block (consisting of combinational logic and state memory), c1(N) ═ c2(N + 1). Delaying c1(N) by one cycle produces c1(N-1), which c1(N-1) equals c2(N) in a fault-free linear block. Further, any non-zero differences c1(N-1) -c2(N) indicate a fault in the linear block. The same degree of fault detection can be achieved by double redundancy, e.g. y (n) is calculated independently with a second instance of the same linear block fed with the same input signal i (n). This may double the area and power required, while computing the checksum may use a fraction of the area and power of the linear block. One difference is that: multiple concurrent failures can typically be detected in dual redundancy, whereas in the case of checksum-based systems, the number of concurrent failures is limited by the Hamming distance (Hamming distance) d, where d-1 failures can be detected and (d-1)/2 failures can be corrected. This hamming distance is also implicit in checksum-based systems; c1 and c2 consist of one or more single signals, depending on the desired hamming distance. In various applications, such as functional safety, where single failures may occur frequently and double or even triple failures may occur infrequently, the limitation of detecting, for example, only single and double failures (as would be produced by hamming distance d-3) may not be a problem.
The digital checksum test described above is similar to the analog checksum test applied to analog circuits. The device is not clocked, but rather time-continuous; the clocked register is replaced by a capacitor which performs an integration of the current, resulting in a voltage representing the result of the integration. The states are represented by the voltage of a capacitor, while the equivalent of combinational logic is the remaining circuitry other than a capacitor — the circuitry consisting of (or that can be modeled as) an amplifier and a resistor. Respectively extracting voltages V from the analog circuits 102RAnd VC. In the data-checking circuit 104, the linear analog network calculates c1 and c2 again by voltage representation. Again, c1 and c2 may consist of one or more single signals.
According to various specific embodiments, the detected error may be used, using the voltage to one or more capacitors VCError signal feedback corrects the fault. In the general case where there are n faults in the analog circuit 102, these singlesN of the difference signals are provided back to a single VCN of the signals. For one or more error signal component sums V to be provided backCThe selection of signal circuitry (e.g., one or more components) may depend on the location of the fault in the analog circuit 102. A number of different adaptive self-learning strategies may be used to determine which of the single error signals to feed into the single VCWhich of the components. Such a strategy may be implemented in a comparison circuit (as otherwise described herein). The use of a digital comparison circuit may allow to ensure that in all cases a sufficient phase margin is maintained so that any risk of oscillation is safely eliminated.
FIG. 2 illustrates another example apparatus for detecting errors conveyed by a linear analog circuit according to this disclosure. The device 210 may include a discrete circuit or IC having a linear analog circuit and a data check circuit, such as the circuit previously described above in connection with fig. 1.
As shown, the device 210 includes a linear analog circuit 212 (for ease of reference, the linear analog circuit 212 is referred to herein as "analog circuit 212"), the analog circuit 212 having voltage changing circuitry (e.g., amplifier, resistor 216) and voltage impedance circuitry (e.g., capacitor 218) coupled to an ATB 220. Although the embodiment of fig. 2 (and various additional figures) shows the voltage change circuitry and the voltage reactance circuitry as separate components or blocks, embodiments are not so limited and such components are not necessarily physically separate.
All analogue values (e.g. voltage V)RAnd VC) Obtained by the ATB 220, the ATB 220 may be part of the analog circuit 212, as described above. Data checking circuit 214 sequentially captures these analog values (optionally by computation circuit 224), optionally digitizes the analog values (e.g., voltage or current, via ADC 222) and provides the results to computation circuit 224, which computation circuit 224 computes and compares the two checksums. The computational circuitry 224 may provide control signals to the ATB 220 to control the selectivity of different ones of the plurality of input portsAnd (5) transferring.
As previously described, for more complete test coverage, such as for parametric faults and transient faults, the apparatus 210 may be used to facilitate analog checksum testing and BIST in combination with optionally BIFI. Analog checksum test and BIST may have large overlap-both cover most failures. The analog checksum test and BIST may thus provide a different Dual Redundancy (direct Dual Redundancy). This synergy allows to fully relax the detection limits of both methods, thus further reducing the risk of false alarms. Also, the synergistic effect results from the fact that: BIST, BIFI, and checksum testing may use ADCs and/or DACs, which may allow reuse and save area, power, and design effort.
Another synergistic effect was found by the following embodiment: BIST and BIFI run intermittently with the application mode, while the checksum proceeds concurrently. Thus, preferably, the BIST and the BIFI may be activated at and only when the checksum fails, and/or the BIST and the BIFI may be activated in addition to one checksum at startup.
FIG. 3 illustrates an example apparatus for detecting and correcting errors conveyed by a linear analog circuit according to this disclosure. Similar to fig. 1 and 2, device 330 includes a linear analog circuit 332 (for ease of reference, the linear analog circuit 332 is referred to herein as "analog circuit 332"), the analog circuit 332 having voltage altering circuitry (e.g., amplifier, resistor 316) and voltage impedance circuitry (e.g., capacitor 318) coupled to ATB 320. Data check circuit 334 sequentially captures the output analog value (e.g., voltage) from ATB 320 (selection is made by calculation circuit 342), digitizes the analog value (e.g., by ADC 340) and provides the result to calculation circuit 342, which calculation circuit 342 calculates and compares the two checksums. The computational circuitry 342 provides control signals to the ATB 320 to control the selective delivery of different ones of the plurality of input ports.
The data checking circuit 334 may additionally include a DAC 344, which DAC 344 detects the error and provides a correction signal back to the analog circuit 332. Due to the direction of voltageImpedance circuitry (e.g., capacitor 318) provides a correction signal (e.g., value), so ATB 320 can be used to implement error correction. The ATB 320 is arranged with different tree structures for forcing and sensing. The data check circuit 334 generates a digital error signal that is converted by the DAC 344. As previously described, analog checksum tests consisting of more than one signal produce the same number of signal differences. Due to the fact that V is paired by ATB 320RAnd VCCannot be performed in parallel, so a variety of approaches are depicted in different embodiments, as additionally shown and described in fig. 4-6 and 7A-7B.
Fig. 4 is a graph illustrating an analog signal in an example test facilitated by an apparatus according to the present disclosure. As illustrated by graph 450, quasi-synchronous sampling of the slow signal may be used in various embodiments. As previously described, the linear analog circuit and the data checking circuit collectively perform a test on the linear analog circuit for low frequency signals received by the analog test bus circuit with respect to the sampling frequency capacity of the ADC by: the method includes processing sequentially received signals using a data processing circuit through a quasi-parallel processing algorithm and estimating and canceling time delays associated with different internal nodes of a linear analog circuit, and simulating therein tests of probes to the different internal nodes concurrently or simultaneously.
In embodiments where the sampling frequency of the ADC in the data inspection circuit is much higher than the signal frequency, samples can be taken quasi-parallel so that the resulting error is sufficiently small. FIG. 4 shows a signal at V consisting of two single signalsCAnd V consisting of a single signalRThis is depicted at example (a). Samples labeled N-1 to N-4. The dashed line marks the time at which the sample is taken in an ideal manner and shows, for example, Δ V, e.g. the (small) difference between the actual point in time and the sampled analog value, e.g. voltage, at the ideal point in time.
Fig. 5 is a graph illustrating an analog signal in an example test facilitated by an apparatus according to the present disclosure. In other embodiments, undersampling may be performed on the fast quasi-stationary signal, as shown in graph 554. The linear analog circuit and the data checking circuit collectively perform a test on the linear analog circuit for signals received by the ATB and having a period length approximately corresponding to the sampling frequency capacity of the ADC by: the ADC and the data processing circuit are undersampled and wherein voltage differences between signals at the plurality of internal nodes are estimated.
At VRAnd VCIn embodiments where the period of the signal is about the maximum sampling frequency but the signal is sufficiently stationary, undersampling may be performed. FIG. 5 passes V consisting of two single signals at the same example as shown in FIG. 4CAnd V consisting of a single signalRThis is depicted. The arrow points to where the corresponding sample should actually be. Again, for example, Δ V is shown, e.g. (small) difference between the actual point in time and the sampled analog value (e.g. voltage) at the point in time.
FIG. 6 illustrates a model of an example apparatus for computing properties of a data inspection circuit for detecting and correcting errors conveyed by a linear analog circuit using modeled delays according to this disclosure. In particular embodiments, a model of a linear analog circuit used in an analog processing algorithm of a data inspection circuit includes selective time delays in a signal driving an analog test bus circuit to offset signal skew. This model may be used to calculate the properties of the data inspection circuit 662.
Similar to fig. 1-3, the apparatus includes a linear analog circuit 660 (for ease of reference, the linear analog circuit 660 is referred to herein as "analog circuit 660"), the analog circuit 660 having voltage altering circuitry (e.g., amplifiers, resistors) and voltage impedance circuitry (e.g., capacitors) coupled to the ATB. The data checking circuit sequentially captures the output analog value (e.g., voltage) from the ATB (selection is made by the computation circuit), digitizes the analog value (e.g., by an ADC) and provides the result to the computation circuit, which computes and compares the two checksums. The computational circuitry provides control signals to the ATB to control selective delivery of different ones of the plurality of input ports.
According to various embodiments, the sampling offset may be modeled by delays 664, 665. That is, different V's in the analog circuit 660RAnd VCDifferent sampling times of the signal yield the same fault detection capability, although fault correction may not be used in such embodiments, since the modeled circuit is not a true circuit. Fig. 2 shows an actual Analog Mixed Signal (AMS) block, and fig. 7A shows an actual sampling time. FIG. 6 illustrates modeling of an AMS block (e.g., analog circuit 660). Although FIG. 6 shows the delays 664, 665 as blocks, the actual delay circuitry is not included in the AMS block, but rather a data checking circuit 662 that models such delays. Fig. 7B shows the re-modeled sampling times using the modeled delays. Re-modeling here means that the checksum calculation is performed as if there were a physical delay circuit and the sampling did not have any offset. The result is the same as without the delay block, but there is an offset in the samples.
7A-7B are graphs illustrating example tests facilitated by an apparatus according to the present disclosure. More specifically, FIG. 7A shows an example graph 770 of a simulated checksum test without modeled delay (such as the simulated checksum test performed by the device shown in FIG. 2), and FIG. 7B shows an example graph 771 of a simulated checksum test using modeled delay that may be performed by the device shown in FIG. 6.
FIG. 8 illustrates an example apparatus for detecting errors conveyed by more than one linear analog circuit in accordance with this disclosure. As shown, each IC may include a plurality of linear analog circuits 881-1 … 881-N (for ease of reference, the linear analog circuits 881-1 … 881-N are referred to herein as "analog circuits 881-1, 881-N or each analog circuit 881-1, 881-N"). Each analog circuit has an ATB, which may be referred to as a "local ATB. The output of the local ATB is provided to central ATB 882. Like the local ATB, central ATB 882 is intended for production testing, so it can select one of the signals and provide the selected signal to an IC pin or a dedicated ADC for production testing. This structure can also be reused for calculating the analog checksum without additional hardware overhead.
Similar to fig. 1-3 and 6, each analog circuit 881-1, 881-N of device 880 has voltage changing circuitry (e.g., amplifiers, resistors) and voltage impedance circuitry (e.g., capacitors) coupled to local ATB. Local ATBs are coupled to central ATB 882. The central ATB 882 receives the signals provided from the analog circuits 881-1, 881-N through the local ATBs of the analog circuits 881-1, 881-N and sends the signals toward the ADCs of the data check circuit 883. Data check circuit 883 sequentially captures the output analog signal from each local ATB through central ATB 882 (optionally by computational circuitry), digitizes the analog value (e.g., through an ADC) and provides the result to computational circuitry, which computes and compares the two checksums. The computational circuitry provides control signals to the local ATB and central ATB 882 to control the selective delivery of different ones of the plurality of input ports. As can be appreciated, the data check circuit 883 performs a test on each of the analog circuits 881-1, 881-N by running a sequential analog checksum test on each of the analog circuits 881-1, 881-N, respectively.
The circuitry shown in fig. 1-3, 6 and 8 may be used in various combinations. For example, an IC having a plurality of linear analog circuits may include the data checking circuit shown in fig. 2, 3, and/or 6. In addition, various devices illustrated herein can be used to implement various methods.
An example method includes: receiving an analog input signal at a linear analog circuit and providing a processed analog output signal, the linear analog circuit comprising: voltage change circuitry and voltage impedance circuitry that collectively perform processing of the analog input signal by the linear analog circuit; and an ATB, the ATB including a plurality of input ports. The method additionally comprises: modulating the analog input signals provided at a plurality of voltage nodes of the voltage change circuitry and providing modulated analog signals at an output of the voltage change circuitry; and blocking the modulated analog signal by the voltage impedance circuitry including capacitive circuitry and providing a blocked analog signal at an output of the voltage impedance circuitry. The method may include: driving, by the output of the voltage change circuitry, an input of voltage impedance circuitry and one of the plurality of input ports of the ATB and driving, by the output of the voltage impedance circuitry, another one of the plurality of input ports of the ATB; and selectively passing a different input port of the plurality of input ports to at least one output port of the ATB in response to a control signal. In various embodiments, the method comprises: detecting errors communicated by the linear analog circuit by a data checking circuit by: applying the control signal to cause the ATB to selectively pass the different ones of the plurality of input ports while the linear analog circuit and the data check circuit perform a test on the linear analog circuit, the data check circuit including an ADC communicatively coupled to the at least one output port of the ATB and including a data processing circuit. The processed analog output signal may be provided during an application mode of the device and while the linear analog circuit and the data check circuit perform a test on the linear analog circuit.
As described above, detecting the error conveyed by the linear analog circuit may include comparing data indicative of the modulated analog signal and the impeded analog signal to one or more expected values. In various embodiments, facilitating the testing by the data checking circuitry includes facilitating at least two of the following tests to provide a test corresponding to a certain safety integrity level and to provide diagnostic coverage according to a certain safety integrity level: BIST, analog checksum test, and BIFI. Additionally, the method may additionally include: sending a correction signal to the linear analog circuit through a DAC in response to the detected error communicated by the linear analog circuit, the DAC communicatively positioned between the data processing circuit and the ATB.
As described above, embodiments in accordance with the present disclosure are directed to compensating for sample offsets using analog checksums in a functionally secure context, reusing existing test structures such as ATBs, ADCs, and/or DACs, using various synergies with BIST and BIFI, and/or using special-purpose means. In addition, although the devices shown in fig. 2-3, 6, and 8 illustrate a data checking circuit having an ADC, embodiments are not limited thereto. For example, the data checking circuit may perform analog checksum testing in a purely analog form without the use of an ADC (e.g., for high frequency signals).
Terms used to illustrate orientation, such as upper/lower, left/right, top/bottom, and above/below, may be used herein to refer to relative element positions as shown in the figures. It is to be understood that such terms are merely used for convenience and that in actual use, the disclosed structures may be oriented differently than shown in the figures. Accordingly, the terminology should not be interpreted in a limiting manner.
The skilled artisan will recognize that various terms, as used in this specification (including the claims), are intended to have their ordinary meaning in the art, unless otherwise indicated. By way of example, this specification describes and/or illustrates aspects of the claimed disclosure as may be implemented by various circuits or circuitry that may be described or illustrated using terms such as: blocks, modules, devices, systems, units, controllers, and/or other circuit-type depictions (e.g., reference numerals 102 and 212 of fig. 1-2 depict blocks/modules as described herein). Such circuitry or circuitry is used in conjunction with other elements to illustrate how certain embodiments may be implemented in the form of structures, steps, functions, operations, activities, and so forth. For example, in some of the embodiments discussed above, one or more modules are discrete logic circuits or programmable logic circuits configured and arranged to implement these operations/activities as may be performed with the methods shown in fig. 3, 6, and 8. In certain embodiments, such programmable circuitry is one or more computer circuits, including memory circuitry for storing and accessing programs to be executed as a set (or sets) of instructions (and/or to be used as configuration data for defining how the programmable circuitry is to be executed), and algorithms or processes as described herein are used by the programmable circuitry to perform associated steps, functions, operations, activities, or the like. Depending on the application, the instructions (and/or configuration data) may be configured to be implemented in logic circuitry, where the instructions (whether characterized in object code, firmware, or software) are stored in and accessible from a memory (circuitry). As another example, where the specification may refer to "a first linear analog circuit," "a second linear analog circuit," etc., where a circuit may be replaced with terms such as "circuitry," "circuitry," etc., the adjectives "first" and "second" are not intended to imply any description of the structure or to provide any material meaning; rather, such adjectives are used only in english antecedents to distinguish one such similarly-named structure from another.
Based on the foregoing discussion and description, one skilled in the art will readily recognize that various modifications and changes may be made to the various embodiments without strictly following the exemplary embodiments and applications illustrated and described herein. For example, the methods illustrated in the figures may involve steps that are performed in various orders (with one or more aspects of the embodiments herein being retained) or may involve fewer or more steps. For example, a plurality of linear analog circuits (e.g., the linear analog circuit shown in fig. 8) may be used in combination with a data inspection circuit such as the data inspection circuit shown in fig. 1-3. As another example, a modeled delay technique (as shown in FIG. 6) may be used in combination with the circuitry shown in FIGS. 1-2. Such modifications do not depart from the true spirit and scope of the various aspects of the present disclosure, including the aspects set forth in the claims.

Claims (10)

1. An apparatus, characterized in that it comprises:
a linear analog circuit configured and arranged to receive an analog input signal and to provide a processed analog output signal, the linear analog circuit comprising:
voltage change circuitry and voltage impedance circuitry collectively configured and arranged to perform processing of the analog input signal by the linear analog circuit;
an analog test bus circuit comprising a plurality of input ports and configured and arranged to selectively pass different ones of the plurality of input ports to at least one output port;
the voltage change circuitry is configured and arranged to modulate the analog input signals provided at a plurality of voltage nodes and to provide modulated analog signals at an output of the voltage change circuitry; and is
The voltage impedance circuitry comprising capacitive circuitry is configured and arranged to block the modulated analog signal and to provide a blocked analog signal at an output of the voltage impedance circuitry; and is
Wherein the output of the voltage change circuitry is configured and arranged to drive an input of voltage impedance circuitry and one of the plurality of input ports of the analog test bus circuit, and the output of the voltage impedance circuitry is configured and arranged to drive another of the plurality of input ports of the analog test bus circuit; and
a data checking circuit communicatively coupled to the at least one output port of the analog test bus circuit and including a data processing circuit configured and arranged to detect errors communicated by the linear analog circuit by: applying control signals to cause the analog test bus circuit to selectively pass the different ones of the plurality of input ports while the linear analog circuit and the data inspection circuit facilitate testing of the linear analog circuit.
2. The apparatus of claim 1, wherein the data inspection circuit is configured and arranged to facilitate at least two of the following tests to provide testing of the linear analog circuit during an application mode: analog checksum testing, built-in self-test, and built-in fault injection testing.
3. The apparatus of claim 1, wherein the data inspection circuit further comprises an analog-to-digital converter (ADC), and the data inspection circuit is configured and arranged to facilitate each of the following tests: analog checksum testing, built-in self-test, and built-in fault injection testing.
4. The apparatus of claim 1, wherein the linear analog circuit receives the analog input signal and provides the processed analog output signal when the linear analog circuit and the data inspection circuit perform a test on the linear analog circuit.
5. The device of claim 1, wherein the analog test bus circuit is configured and arranged to access the linear analog circuit by passing analog values to and from the linear analog circuit, and wherein the data checking circuit further comprises a digital-to-analog converter (DAC) communicatively positioned between the data processing circuit and the analog test bus circuit, the DAC configured and arranged to send a correction signal to the linear analog circuit in response to a detected error communicated by the linear analog circuit.
6. The apparatus of claim 1, wherein the model of the linear analog circuit used in the analog processing algorithm of the data inspection circuit comprises a selective time delay in the signal driving the analog test bus circuit to offset signal skew.
7. The apparatus of claim 1, further comprising built-in self-test circuitry configured and arranged to perform built-in self-tests and built-in fault injection circuitry configured and arranged to perform built-in fault injection tests, wherein the data checking circuit is configured and arranged to perform analog checksum tests and facilitate the built-in self-tests and the built-in fault injection tests.
8. The apparatus of claim 1, wherein the data inspection circuit further comprises an analog-to-digital converter (ADC), and the linear analog circuit and the data inspection circuit are collectively configured and arranged to perform the test on the linear analog circuit by processing signals using the ADC and the data processing circuit through an algorithm configured to model a time delay for cancelling a signal offset in respective signals directed toward the analog test bus circuit.
9. The apparatus of claim 1, further comprising:
at least one further linear analog circuit configured and arranged to provide a processed analog output signal, the at least one further linear analog circuit comprising:
another voltage modification circuitry and another voltage impedance circuitry collectively configured and arranged to perform processing of the analog input signal by the other linear analog circuitry; and
another analog test bus circuit comprising a plurality of input ports and configured and arranged to selectively pass a different input port of the plurality of input ports to at least one output port; and
a central analog test bus circuit configured and arranged to receive signals provided from each of the linear analog circuits and configured to transmit signals towards the data checking circuit, the linear analog circuits including the first recited linear analog circuit and the at least one further linear analog circuit.
10. A method, characterized in that it comprises:
receiving an analog input signal at a linear analog circuit and providing a processed analog output signal, the linear analog circuit comprising: voltage change circuitry and voltage impedance circuitry collectively configured and arranged to perform processing of the analog input signal by the linear analog circuit; and an analog test bus circuit comprising a plurality of input ports;
modulating the analog input signals provided at a plurality of voltage nodes of the voltage change circuitry and providing modulated analog signals at an output of the voltage change circuitry;
blocking the modulated analog signal by the voltage impedance circuitry including capacitive circuitry and providing a blocked analog signal at an output of the voltage impedance circuitry;
driving, by the output of the voltage change circuitry, an input of voltage impedance circuitry and one of the plurality of input ports of the analog test bus circuit and driving, by the output of the voltage impedance circuitry, another one of the plurality of input ports of the analog test bus circuit;
selectively passing different ones of the plurality of input ports to at least one output port of the analog test bus circuit in response to a control signal; and
detecting, by a data checking circuit, an error conveyed by the linear analog circuit by: applying the control signal to cause the analog test bus circuit to selectively pass the different ones of the plurality of input ports while the linear analog circuit and the data checking circuit perform a test on the linear analog circuit, the data checking circuit including an analog-to-digital converter (ADC) communicatively coupled to the at least one output port of the analog test bus circuit and including a data processing circuit.
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