CN111211782A - High-speed successive approximation type analog-to-digital converter with leakage current compensation function - Google Patents

High-speed successive approximation type analog-to-digital converter with leakage current compensation function Download PDF

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CN111211782A
CN111211782A CN202010068045.8A CN202010068045A CN111211782A CN 111211782 A CN111211782 A CN 111211782A CN 202010068045 A CN202010068045 A CN 202010068045A CN 111211782 A CN111211782 A CN 111211782A
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switch
leakage current
capacitor
sampling
weight
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CN111211782B (en
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徐代果
蒋和全
李儒章
王健安
陈光炳
王育新
付东兵
戴永红
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Chongqing Jixin Technology Co Ltd
CETC 24 Research Institute
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Chongqing Jixin Technology Co Ltd
CETC 24 Research Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors

Abstract

The invention discloses a high-speed successive approximation type analog-to-digital converter with a leakage current compensation function, which comprises a main ADC module, an auxiliary ADC module and two sampling switch leakage current compensation modules; the auxiliary ADC module generates auxiliary leakage current which is in a linear relation with the leakage current of the main ADC module and sends the auxiliary leakage current to the two sampling switch leakage current compensation modules, so that the two sampling switch leakage current compensation modules generate compensation current which is the same as the leakage current of the main ADC module and send the compensation current to the main ADC module. In the invention, because the device of the auxiliary ADC module is the device of the main ADC module, the area of the auxiliary ADC module can be made small; because the compensation current generated by the auxiliary ADC module and the sampling switch leakage current compensation module and the leakage current generated by the main ADC module are linearly and synchronously changed along with the temperature, the power supply voltage and the process, an additional compensation technology is not needed, the structure is simple, and the compensation precision is high.

Description

High-speed successive approximation type analog-to-digital converter with leakage current compensation function
Technical Field
The invention relates to the field of high-speed successive approximation type analog-to-digital converters, in particular to a high-speed successive approximation type analog-to-digital converter with a leakage current compensation function.
Background
In recent years, with the further improvement of performance indexes of analog-to-digital converters, especially with the continuous development of integrated circuit process technologies, research on high-speed successive approximation analog-to-digital converters (SAR ADCs) is also more and more intensive. With the continuous evolution of the integrated circuit manufacturing process, the design of a high-gain operational amplifier becomes more and more difficult, and because the operational amplifier is not needed, the SAR ADC has the advantage of natural low power consumption, and particularly under the nanometer-scale process node, the speed of the SAR ADC is greatly improved. Therefore, high-speed SAR ADCs are the focus of research in current analog-to-digital converters. Due to the parasitic diode between the source electrode and the drain electrode of the sampling switch and the ground, when the SAR ADC is in a successive approximation state, a leakage current exists between the sampling polar plate and the ground, and due to the existence of the leakage current, the charge conservation of the weight capacitor array is broken, so that the precision of the SAR ADC is reduced. With the continuous progress of the integrated circuit manufacturing process and the increase of the temperature, the leakage current is larger and larger, and the influence on the SAR ADC precision is increased.
The circuit diagram of a conventional SAR ADC is shown in fig. 1, and the successive approximation roadmap and timing diagram are shown in fig. 2. If the parasitic diodes between the sources and drains of the sampling switches Sp and Sn and the ground are not considered, when the SAR ADC of the structure is in a sampling state, the sampling signal Clkin is at a high level, the clock signal Clk is at a low level, and the switch Sp/Sn of the main ADC module samples the differential input signals Vip and Vin. When the SAR ADC is in a successive approximation state, a switch Sp/Sn of the main ADC module is disconnected, a sampling signal Clkin is at a low level, a clock signal Clk generates an enabling signal of the comparator, and the upper polar plate VSP and the lower polar plate VSN of the weight capacitor array start a successive approximation process.
If the parasitic diodes between the sources and drains of the sampling switches Sp and Sn and the ground are considered, the cross-sectional view of the sampling switch of the parasitic diode between the sources and drains of the sampling switches Sp and Sn and the ground is shown in fig. 3, the BOOST module is a sampling switch gate voltage bootstrap circuit, P-SUB is a chip substrate, DNW is a deep N-well, NW is an N-well, P + is a P diffusion region, N + is an N diffusion region, PW is a P-well, and G represents the gate of the sampling NMOS transistor. When the SAR ADC is In a successive approximation state, due to the parasitic diodes Dp and Dn between the source and drain of the sampling switches and the ground, there is a leakage current Ip and In from the sampling plates VSP and VSN to the ground, and the magnitude of this leakage current can be expressed as:
Figure BDA0002376550290000021
in the formula (1), ISRepresenting leakage current Ip or In, Is0The reverse saturation current of the diode is a constant positively correlated with the area of the diode, and I is shown by the formula (1)SWill increase with increasing temperature. In the design of the high-speed SAR ADC, in order to increase the sampling speed, the area of a sampling switch is made larger, and the design of a sampling capacitor is smaller, so that the area of a parasitic diode between a source electrode and a drain electrode of the sampling switch and the ground is increased, and when the SAR ADC is in a successive approximation state, the leakage current from a sampling polar plate VSP and a VSN to the ground is increased, so that the sampling polar plate has larger leakage current. As the ic manufacturing process continues to evolve, the leakage current increases, and thus, the above problem is more serious in advanced processes. Meanwhile, as can be seen from equation (1), the leakage current increases as the temperature increases. The SAR ADC successive approximation route diagram and the timing diagram in consideration of the influence of the leakage current are shown in FIG. 4. it can be seen from FIG. 4 that if the influence of the leakage current is considered, the sampling plates VSP and VSN are used in the successive approximation processThe voltage drop can occur, meanwhile, because the voltages of the two plates are different, the voltage drop amplitudes of the two plates are also different, the precision of the SAR ADC can be seriously influenced, and the leakage current is a problem to be solved in the design of the high-precision SAR ADC.
Disclosure of Invention
The invention provides a high-speed successive approximation type analog-to-digital converter with a leakage current compensation function.
The technical scheme of the invention is as follows:
a high-speed successive approximation type analog-to-digital converter with a leakage current compensation function comprises a main ADC module, an auxiliary ADC module, a first sampling switch leakage current compensation module, a second sampling switch leakage current compensation module and a switch control module; the main ADC module comprises a comparator, a first sampling switch Sp, a second sampling switch Sn, a first weight capacitor array, a second weight capacitor array, a first nominal capacitor and a second nominal capacitor, wherein the output end of the comparator is electrically connected with the switch control module, the non-inverting input end of the comparator is connected with a differential input signal Vip through the first sampling switch Sp, the non-inverting input end of the comparator is also electrically connected with the first end of the first nominal capacitor, and the second end of the first nominal capacitor is grounded; the first weighting capacitor array comprises a plurality of weighting capacitors and a plurality of first three-end control switches S1 corresponding to the weighting capacitors one by one, the first ends of the weighting capacitors in the first weighting capacitor array are all electrically connected with the non-inverting input end of the comparator, and the polar plate corresponding to the first end of the first nominal capacitor and the polar plate corresponding to the first end of the weighting capacitor in the first weighting capacitor array form a first sampling polar plate VSP together; second ends of a plurality of weight capacitors of the first weight capacitor array are respectively and electrically connected with input ends of corresponding first three-end control switches S1, a first output end of each first three-end control switch S1 is connected with a power supply voltage VREFN, a second output end of each first three-end control switch S1 is connected with a power supply voltage VREFP, and a control end of each first three-end control switch S1 is correspondingly and electrically connected with one output end of a switch control module;
the inverting input end of the comparator is connected with the differential input signal Vin through a second sampling switch Sn, the inverting input end of the comparator is also electrically connected with a first end of a second nominal capacitor, a second end of the second nominal capacitor is grounded, and the capacitance value and the polar plate area of the second nominal capacitor and the first nominal capacitor are equal; the second weighted capacitor array comprises a plurality of weighted capacitors and a plurality of second three-end control switches S2 corresponding to the weighted capacitors one by one, the number of the weighted capacitors in the second weighted capacitor array is equal to that of the weighted capacitors in the first weighted capacitor array, the capacitance value and the plate area of each weighted capacitor in the second weighted capacitor array are equal to that of one weighted capacitor in the first weighted capacitor array, the first ends of the weighted capacitors in the second weighted capacitor array are electrically connected with the inverting input end of the comparator, and the plate corresponding to the first end of the second nominal capacitor and the plates corresponding to the first ends of the weighted capacitors in the second weighted capacitor array form a second sampling plate VSN; second ends of a plurality of weight capacitors of the second weight capacitor array are respectively and electrically connected with input ends of corresponding second three-end control switches S2, a first output end of each second three-end control switch S2 is connected with a power supply voltage VREFN, a second output end of each second three-end control switch S2 is connected with a power supply voltage VREFP, and a control end of each second three-end control switch S2 is respectively and electrically connected with a control end of a corresponding first three-end control switch S1;
the auxiliary ADC module is used for generating an auxiliary leakage current Ip1 In a linear relation with the leakage current Ip of the first sampling polar plate VSP and transmitting the auxiliary leakage current Ip1 to the first end of the first sampling switch leakage current compensation module, generating an auxiliary leakage current In1 In a linear relation with the leakage current In of the second sampling polar plate VSN and transmitting the auxiliary leakage current In1 to the first end of the second sampling switch leakage current compensation module, the first sampling switch leakage current compensation module generates a compensation current KIn1 equal to the leakage current In according to the value of the auxiliary leakage current In1 and transmits the compensation current to the first sampling polar plate VSP from the second end of the first sampling switch leakage current compensation module, and the second sampling switch leakage current compensation module generates a compensation current KIp1 equal to the auxiliary leakage current Ip according to the value of the leakage current Ip1 and transmits the compensation current to the second sampling polar plate VSN from.
Furthermore, the capacitance values of the plurality of weight capacitors in the first weight capacitor array sequentially form a binary relation, and the weight capacitor with the smallest capacitance value in the first weight capacitor array is equal to the capacitance value of the first nominal capacitor.
Further, the auxiliary ADC module includes a third sampling switch Sp1, a fourth sampling switch Sn1, a third weighted capacitor array, a fourth weighted capacitor array, a third nominal capacitor, and a fourth nominal capacitor, where the capacitance and the plate area of the third nominal capacitor and the fourth nominal capacitor are equal to each other, and K times of the capacitance and K times of the plate area of the third nominal capacitor are equal to those of the first nominal capacitor, where K is an integer greater than 1; the third weight capacitor array comprises a plurality of weight capacitors and a plurality of third three-terminal control switches S3 corresponding to the weight capacitors one by one, the number of the weight capacitors in the third weight capacitor array is equal to that of the weight capacitors in the first weight capacitor array, and the capacitance value K times and the electrode plate area K times of each weight capacitor in the third weight capacitor array are equal to that of one weight capacitor in the first weight capacitor array; the first ends of a plurality of weight capacitors in the third weight capacitor array are electrically connected with the first end of a third nominal capacitor, and the second end of the third nominal capacitor is grounded; a polar plate corresponding to the first end of the third nominal capacitor and polar plates corresponding to the first ends of the multiple weighting capacitors in the third weighting capacitor array form a third sampling polar plate VSP 1; the second ends of a plurality of weight capacitors in the third weight capacitor array are respectively and electrically connected with the input end of a corresponding third three-terminal control switch S3, the first output end of each third three-terminal control switch S3 is connected with a power supply voltage VREFN, the second output end of each third three-terminal control switch S3 is connected with a power supply voltage VREFP, and the control end of each third three-terminal control switch S3 is respectively and electrically connected with the control end of a corresponding first three-terminal control switch S1;
the fourth weight capacitor array comprises a plurality of weight capacitors and a plurality of fourth three-terminal control switches S4 corresponding to the weight capacitors one by one, the number of the weight capacitors in the fourth weight capacitor array is equal to that of the weight capacitors in the second weight capacitor array, and the capacitance value K times and the electrode plate area K times of each weight capacitor in the fourth weight capacitor array are equal to that of one weight capacitor in the second weight capacitor array; the first ends of a plurality of weight capacitors in the fourth weight capacitor array are electrically connected with the first end of a fourth nominal capacitor, and the second end of the fourth nominal capacitor is grounded; a polar plate corresponding to the first end of the fourth nominal capacitor and polar plates corresponding to the first ends of the multiple weighting capacitors in the fourth weighting capacitor array form a fourth sampling polar plate VSN 1; the second ends of the multiple weight capacitors in the fourth weight capacitor array are respectively electrically connected with the input end of the corresponding fourth three-terminal control switch S4, the first output end of each fourth three-terminal control switch S4 is connected with the supply voltage VREFN, the second output end of each fourth three-terminal control switch S4 is connected with the supply voltage VREFP, and the control end of each fourth three-terminal control switch S4 is respectively electrically connected with the control end of the corresponding second three-terminal control switch S2.
Further, the first sampling switch Sp, the second sampling switch Sn, the third sampling switch Sp1, and the fourth sampling switch Sn1 are all PMOS transistors, the length-to-width ratio and the channel area of the first sampling switch Sp and the second sampling switch Sn are equal, the length-to-width ratio and the channel area of the third sampling switch Sp1 and the fourth sampling switch Sn1 are equal, and the channel area of the first sampling switch Sp is K times the channel area of the third sampling switch Sp 1.
Furthermore, each three-terminal control switch comprises a PMOS tube and an NMOS tube, the length-width ratio and the channel area of the PMOS tubes in the first three-terminal control switch S1 and the second three-terminal control switch S2 are equal, the length-width ratio and the channel area of the NMOS transistor in the first three-terminal control switch S1 and the second three-terminal control switch S2 are equal, the length-width ratio and the channel area of the PMOS tubes in the third three-terminal control switch S3 and the fourth three-terminal control switch S4 are equal, the length-width ratio and the channel area of the NMOS transistor in the third three-terminal control switch S3 and the fourth three-terminal control switch S4 are equal, the channel area of the PMOS tube in the first three-terminal control switch S1 is K times of the channel area of the PMOS tube in the third three-terminal control switch S3, the channel area of the NMOS tube in the first three-terminal control switch S1 is K times of the channel area of the NMOS tube in the third three-terminal control switch S3.
Further, the first sampling switch leakage current compensation module comprises a standard field effect transistor M0 and a plurality of first mirror field effect transistors M1, the sources of the first mirror field effect transistors M1 are electrically connected with each other and then are used as the second end of the first sampling switch leakage current compensation module to be electrically connected with the first sampling polar plate VSP, the gates of the first mirror field effect transistors M1 are electrically connected with the gate of the standard field effect transistor M0, and the drains are connected with the power supply VDD; the source electrode of the standard field effect transistor M0 is used as the first end of the first sampling switch leakage current compensation module and is electrically connected with the third sampling polar plate VSP1, the grid electrode of the standard field effect transistor M0 is electrically connected with the source electrode thereof, and the drain electrode is connected with the power supply VDD; the sum of the channel areas of a plurality of the first mirror field effect transistors M1 is equal to K times the channel area of the standard field effect transistor M0.
Further, the number of the first mirror image fets M1 is K, and the width-to-length ratio and the channel area of each first mirror image fet M1 are equal to those of the standard fet M0.
Furthermore, the first sampling switch leakage current compensation module further includes K mirror switches S5, a drain of each first mirror fet M1 is connected to a power supply VDD through one mirror switch S5, and a control terminal of each mirror switch S5 is connected to a corresponding trimming code control signal.
Further, the first sampling switch leakage current compensation module further includes J second mirror field effect transistors M2 and (K + J) mirror switches S5, a channel area of each second mirror field effect transistor M2 is smaller than a channel area of a standard field effect transistor M0, a source of each J second mirror field effect transistor M2 and a source of each K first mirror field effect transistor M1 are electrically connected to each other and then serve as a second end of the first sampling switch leakage current compensation module to be electrically connected to the first sampling electrode plate VSP, a gate of each J second mirror field effect transistor M2 is electrically connected to a gate of the standard field effect transistor M0, a drain of each second mirror field effect transistor M5 is connected to a power supply VDD, a drain of each first mirror field effect transistor M1 is connected to the power supply VDD through a mirror switch S5, and a control end of each mirror switch S5 is connected to a corresponding trimming code control signal.
Furthermore, the structure of the second sampling switch leakage current compensation module is the same as that of the first sampling switch leakage current compensation module.
The invention has the following beneficial effects:
1. the device of the auxiliary ADC module is reduced to 1/k of the device of the main ADC module in proportion, and the sampling switch leakage current compensation module is of a current mirror structure, so that the area of the module is small, and the area of the ADC cannot be obviously increased.
2. Because the compensation current generated by the auxiliary ADC module and the sampling switch leakage current compensation module and the leakage current generated by the main ADC module are linearly and synchronously changed along with the temperature, the power supply voltage and the process, an additional compensation technology is not needed, the structure is simple, and the compensation precision is high.
3. The on-off of the mirror switch S5 is controlled through the trimming code, the mismatch of the sampling switch leakage current compensation module is trimmed, and the compensation precision can be further improved.
Drawings
FIG. 1 is a block diagram of a conventional SAR ADC;
FIG. 2 is a successive approximation roadmap and a timing diagram of a conventional SAR ADC during high-speed sampling;
FIG. 3 is a cross-sectional view of the sampling switch considering parasitic diodes between the source and drain of the sampling switch and ground;
FIG. 4 is a SAR ADC successive approximation roadmap and a timing diagram of a conventional structure considering the influence of leakage current;
FIG. 5 is a block diagram of the present invention;
FIG. 6 is a circuit diagram of a first sampling switch leakage current compensation module;
FIG. 7 is a graph comparing SAR ADC accuracy with sampling frequency variation for the present invention and conventional architecture;
fig. 8 is a graph comparing SAR ADC accuracy with temperature for the present invention and conventional configurations.
Detailed Description
The invention will be further explained with reference to the drawings.
In the description of the present invention, unless otherwise specified and limited, it is to be noted that the term "connected" is to be interpreted broadly, and may be, for example, a mechanical connection or an electrical connection, or a communication between two elements, or may be a direct connection or an indirect connection through an intermediate medium, and a specific meaning of the term may be understood by those skilled in the art according to specific situations.
As shown in fig. 5, the embodiment of the present invention includes a main ADC module 1, an auxiliary ADC module 2, a first sampling switch leakage current compensation module 3, a second sampling switch leakage current compensation module 4, and a switch control module 5; the main ADC module 1 includes a comparator 11, a first sampling switch Sp, a second sampling switch Sn, a first weight capacitor array 12, a second weight capacitor array 13, a first nominal capacitor 14, and a second nominal capacitor 15, an output end of the comparator 11 is electrically connected to the switch control module 5, an in-phase input end is connected to a differential input signal Vip through the first sampling switch Sp, an in-phase input end of the comparator 11 is also electrically connected to a first end of the first nominal capacitor 14, and a second end of the first nominal capacitor 14 is grounded.
The first weighted capacitor array 12 includes a plurality of weighted capacitors and a plurality of first three-terminal control switches S1 corresponding to the weighted capacitors one to one, and the following description will be given by taking the example that the first weighted capacitor array 12 includes n weighted capacitors, the capacitance values of the n weighted capacitors in the first weighted capacitor array 12 sequentially form a binary relationship, and the weighted capacitor with the smallest capacitance value in the first weighted capacitor array 12 is equal to the capacitance value of the first nominal capacitor 14, and taking the example that the capacitance value of the first nominal capacitor 14 is equal to C, the capacitance values of the n weighted capacitors in the first weighted capacitor array 12 sequentially form C, 2C, 4C, … …, 2C, etc. from small to large(n-2)C，2(n-1)C。
First ends of the n weight capacitors in the first weight capacitor array 12 are all electrically connected with a non-inverting input end of the comparator 11, and a polar plate corresponding to the first end of the first nominal capacitor 14 and a polar plate corresponding to the first ends of the n weight capacitors in the first weight capacitor array 12 form a first sampling polar plate VSP together; the second ends of the n weight capacitors of the first weight capacitor array 12 are electrically connected to the input end of the corresponding first three-terminal control switch S1, the first output end of each first three-terminal control switch S1 is connected to the supply voltage VREFN, the second output end is connected to the supply voltage VREFP, and the control end of each first three-terminal control switch S1 is electrically connected to an output end of the switch control module 5.
The inverting input end of the comparator 11 is connected with the differential input signal Vin through a second sampling switch Sn, the inverting input end of the comparator 11 is further electrically connected with a first end of a second nominal capacitor 15, a second end of the second nominal capacitor 15 is grounded, and the capacitance values and the plate areas of the second nominal capacitor 15 and the first nominal capacitor 14 are equal; the second weighted capacitor array 13 includes n weighted capacitors and n second three-terminal control switches S2 corresponding to the weighted capacitors one by one, and the capacitance values of the n weighted capacitors in the second weighted capacitor array 13 are C, 2C, 4C, … …, 2C from small to large(n-2)C，2(n-1)C, the plate areas of the two weighting capacitors with the same capacitance values in the first weighting capacitor array 12 and the second weighting capacitor array 13 are also equal.
First ends of n weight capacitors in the second weight capacitor array 13 are all electrically connected with an inverted input end of the comparator 11, and a polar plate corresponding to the first end of the second nominal capacitor 15 and a polar plate corresponding to the first ends of the n weight capacitors in the second weight capacitor array 13 form a second sampling polar plate VSN together; the second ends of the n weight capacitors of the second weight capacitor array 13 are respectively electrically connected with the input end of the corresponding second three-terminal control switch S2, the first output end of each second three-terminal control switch S2 is connected with the supply voltage VREFN, the second output end is connected with the supply voltage VREFP, and the control end of each second three-terminal control switch S2 is respectively electrically connected with the control end of the corresponding first three-terminal control switch S1;
the auxiliary ADC module 2 comprises a third sampling switch Sp1, a fourth sampling switch Sn1, a third weight capacitor array 21, a fourth weight capacitor array 22 and a third nominal capacitor23 and a fourth nominal capacitor 24, wherein the capacitance and the plate area of the third nominal capacitor 23 are both equal to those of the fourth nominal capacitor 24, and K times of the capacitance and K times of the plate area of the third nominal capacitor 23 are equal to those of the first nominal capacitor 12, where K is an integer greater than 1, and if the capacitance of the third nominal capacitor 23 is C1, then C1 is equal to C/K; the third weighted capacitor array 21 comprises n weighted capacitors and n third three-terminal control switches S3 corresponding to the weighted capacitors one by one, wherein K times of the capacitance value and K times of the plate area of each weighted capacitor in the third weighted capacitor array 21 are equal to those of a weighted capacitor in the first weighted capacitor array, that is, the capacitance values of the n weighted capacitors in the third weighted capacitor array 21 are C/K, 2C/K, 4C/K, … …, 2C/K, and the like in sequence from small to large(n-2)C/K，2(n-1)C/K; first ends of n weight capacitors in the third weight capacitor array 21 are all electrically connected with a first end of a third nominal capacitor 23, and a second end of the third nominal capacitor 23 is grounded; a plate corresponding to the first end of the third nominal capacitor 23 and plates corresponding to the first ends of the n weight capacitors in the third weight capacitor array 21 form a third sampling plate VSP 1; the second ends of the n weight capacitors in the third weight capacitor array 21 are respectively electrically connected with the input end of a corresponding third three-terminal control switch S3, the first output end of each third three-terminal control switch S3 is connected with the supply voltage VREFN, the second output end is connected with the supply voltage VREFP, and the control end of each third three-terminal control switch S3 is respectively electrically connected with the control end of a corresponding first three-terminal control switch S1;
the fourth weight capacitor array 22 includes n weight capacitors and n fourth three-terminal control switches S4 corresponding to the weight capacitors one to one, where K times of a capacitance value and K times of an electrode plate area of each weight capacitor in the fourth weight capacitor array 22 are equal to those of a weight capacitor in the second weight capacitor array 13, that is, the capacitance values of the n weight capacitors in the fourth weight capacitor array 22 are C/K, 2C/K, 4C/K, … …, 2C/K, and the like in sequence from small to large(n-2)C/K，2(n-1)C/K; n capacitors of the fourth weight capacitor array 22The first ends of the weighted capacitors are all electrically connected with the first end of a fourth nominal capacitor 24, and the second end of the fourth nominal capacitor 24 is grounded; a plate corresponding to the first end of the fourth nominal capacitor 24 and plates corresponding to the first ends of the n weight capacitors in the fourth weight capacitor array 22 form a fourth sampling plate VSN 1; the second ends of the n weight capacitors in the fourth weight capacitor array 22 are electrically connected to the input end of the corresponding fourth three-terminal control switch S4, the first output end of each fourth three-terminal control switch S4 is connected to the supply voltage VREFN, the second output end is connected to the supply voltage VREFP, and the control end of each fourth three-terminal control switch S4 is electrically connected to the control end of the corresponding second three-terminal control switch S2.
The first sampling switch Sp, the second sampling switch Sn, the third sampling switch Sp1 and the fourth sampling switch Sn1 are all PMOS transistors, the length-to-width ratio and the channel area of the first sampling switch Sp and the second sampling switch Sn are equal, the length-to-width ratio and the channel area of the third sampling switch Sp1 and the fourth sampling switch Sn1 are equal, and the channel area of the first sampling switch Sp is K times of the channel area of the third sampling switch Sp 1. The first three-terminal control switch S1, the second three-terminal control switch S2, the third three-terminal control switch S3 and the fourth three-terminal control switch S4 all comprise a PMOS tube and an NMOS tube, the length-width ratio and the channel area of the PMOS tubes in the first three-terminal control switch S1 and the second three-terminal control switch S2 are equal, the length-width ratio and the channel area of the NMOS transistor in the first three-terminal control switch S1 and the second three-terminal control switch S2 are equal, the length-width ratio and the channel area of the PMOS tubes in the third three-terminal control switch S3 and the fourth three-terminal control switch S4 are equal, the length-width ratio and the channel area of the NMOS transistor in the third three-terminal control switch S3 and the fourth three-terminal control switch S4 are equal, the channel area of the PMOS tube in the first three-terminal control switch S1 is K times of the channel area of the PMOS tube in the third three-terminal control switch S3, the channel area of the NMOS tube in the first three-terminal control switch S1 is K times of the channel area of the NMOS tube in the third three-terminal control switch S3.
As shown in fig. 6, the first sampling switch leakage current compensation module 3 includes a standard fet M0, K first mirror fets M1, J second mirror fets M2 and (K + J) mirror switches S5, the width-to-length ratio and the channel area of each first mirror fet M1 are equal to those of the standard fet M0, and the channel area of each second mirror fet M2 is smaller than that of the standard fet M0; after being mutually and electrically connected, the sources of the K first mirror image field-effect transistors M1 and the sources of the J second mirror image field-effect transistors M2 are electrically connected as the second end of a first sampling switch leakage current compensation module and are electrically connected with a first sampling polar plate VSP, the gates of the K first mirror image field-effect transistors M1 and the gates of the J second mirror image field-effect transistors M2 are electrically connected with the gate of a standard field-effect transistor M0, the drains of the K first mirror image field-effect transistors M1 and the drains of the J second mirror image field-effect transistors M2 are respectively connected with a power supply VDD through a mirror image switch S5, and the control end of each mirror image switch S5 is respectively connected with a corresponding trimming code control signal; the drain of the standard field effect transistor M0 is connected to a power supply VDD, the gate is electrically connected to the source thereof, and the source is electrically connected to the third sampling plate VSP1 as the first end of the first sampling switch leakage current compensation module 3.
The structure of the second sampling switch leakage current compensation module 4 is the same as that of the first sampling switch leakage current compensation module 3; the source electrodes of the first mirror field effect transistor M1 in the second sampling switch leakage current compensation module 4 are electrically connected with each other and then are used as the second end of the second sampling switch leakage current compensation module 4 to be electrically connected with the second sampling polar plate VSN; the source electrode of the standard field effect transistor M0 in the second sampling switch leakage current compensation module 4 is electrically connected with the fourth sampling polar plate VSN1 as the first end of the second sampling switch leakage current compensation module, and the control ends of the mirror switches S5 in the second sampling switch leakage current compensation module 4 are respectively connected with the corresponding trimming code control signals.
The working principle of the embodiment is as follows:
as shown In fig. 5, Dp and Dn respectively represent parasitic diodes between the source and the drain of the first sampling switch Sp and the second sampling switch Sn, Dp1 and Dn1 respectively represent parasitic diodes between the source and the drain of the third sampling switch Sp1 and the fourth sampling switch Sn4, and when the main ADC module 1 operates, a leakage current Ip is generated between the first sampling pad VSP and the ground due to the presence of the parasitic diodes Dp and Dn, and a leakage current In is generated between the second sampling pad VSN and the ground; since the third sampling switch Sp1, the fourth sampling switch Sn1, the third nominal capacitor 23, the fourth nominal capacitor 24, the third weighted capacitor array 21 and the fourth weighted capacitor array 22 of the auxiliary ADC module 2 are respectively reduced by K times by the first sampling switch Sp, the second sampling switch Sn, the first nominal capacitor 14, the second nominal capacitor 15, the first weighted capacitor array 12 and the second weighted capacitor array 13 of the main ADC module 1, the auxiliary leakage current Ip1 generated between the third sampling plate VSP1 and the ground is 1/K of the leakage current Ip, and the auxiliary leakage current In1 generated between the fourth sampling plate VSN1 and the ground is 1/K of the leakage current In.
As shown in fig. 6, the first sampling switch leakage current compensation module 3 is a mirror current source circuit which amplifies K times, after the auxiliary leakage current Ip1 flows into the source of the standard fet M0 in the first sampling switch leakage current compensation module 3, since the K first mirror fets M1 all form a mirror relationship with the standard fet M0, the sources of the K first mirror fets M1 all generate currents with the same size as the auxiliary leakage current Ip1, and the currents generated by the K first mirror fets M1 are superposed to form a compensation current Klp1 with the same size as the leakage current Ip and sent to the first sampling plate to compensate the leakage current Ip lost by the first sampling plate VSP, thereby improving the accuracy of the SAR ADC.
Because parameters of components are unlikely to be absolutely the same and errors always exist, errors exist between currents generated by the sources of the first mirror image field effect transistors M1 and the leakage current Ip1, the errors are likely to be amplified after the currents generated by the sources of the K first mirror image field effect transistors M1 are superposed, and therefore mismatch between the formed compensation current Klp1 and the leakage current Ip is likely to exist, at the moment, the adjustment codes can be set according to the difference value between the compensation current Klp1 and the leakage current Ip to control the on and off of each mirror image switch S5, so that the first mirror image field effect transistors M1 and the second mirror image field effect transistors M2 in proper number are selected to be connected into the mirror image circuits, and because the channel area of the second mirror image field effect transistors M2 is smaller than that of the first mirror image field effect transistors M1, the compensation currents Klp1 can be adjusted finely, and the compensation accuracy is further improved.
After the auxiliary leakage current In1 flows into the second sampling switch leakage current compensation module 4, the compensation current Kln1 generated according to the above process is sent to the second sampling electrode plate VSN, so as to compensate the leakage current In lost by the second sampling electrode plate VSN, and the working process and the control mode of the auxiliary leakage current In1 are completely the same as those of the first sampling switch leakage current compensation module 3.
The invention adopts 65nm CMOS technology, binary weighted capacitor structure, first nominal capacitor 14 value 10fF, make a 12-bit SAR ADC with 1.1MHz sampling rate compare with SAR ADC of traditional structure, when sampling time and temperature are not changed, along with the change of sampling frequency, the signal distortion noise ratio SNDR and no-stray dynamic range SFDR of SAR ADC of traditional structure change as shown in figure 6, as can be known from figure 6, along with the process that the sampling frequency is reduced from 1.1MHz to 100KHz, because the SAR ADC of traditional structure is in the time increase of successive approximation state, because of the existence of sampling leakage current, its precision is reduced (SNDR is reduced by 2dB, SFDR is reduced by 3 dB); the SAR ADC provided by the invention adopts a leakage current compensation technology, so that the precision is not obviously changed. When the sampling frequency and the input frequency are not changed, the change of the SNDR and the SFDR of the SAR ADC of the present invention and the conventional structure is compared with the change of the temperature, for example, as shown in fig. 7, as can be seen from fig. 7, as the temperature increases, since the conventional structure does not have the sampling switch leakage current compensation technology, the leakage current of the SAR ADC increases with the increase of the temperature, so that the accuracy of the SAR ADC decreases with the increase of the temperature (the SNDR decreases by 1.5dB, and the SFDR decreases by 4 dB). With the increase of the temperature, the precision of the SAR ADC is only slightly reduced (the SNDR is reduced by 0.2dB, and the SFDR is reduced by 0.5 dB); therefore, the SNDR and the SFDR of the SAR ADC have small change along with the sampling frequency, and can better overcome the influence of temperature change, thereby having higher precision.
The undescribed parts of the present invention are consistent with the prior art, and are not described herein.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures made by using the contents of the present specification and the drawings can be directly or indirectly applied to other related technical fields, and are within the scope of the present invention.

Claims (10)

1. A high-speed successive approximation type analog-to-digital converter with a leakage current compensation function is characterized in that: the device comprises a main ADC module, an auxiliary ADC module, a first sampling switch leakage current compensation module, a second sampling switch leakage current compensation module and a switch control module; the main ADC module comprises a comparator, a first sampling switch Sp, a second sampling switch Sn, a first weight capacitor array, a second weight capacitor array, a first nominal capacitor and a second nominal capacitor, wherein the output end of the comparator is electrically connected with the switch control module, the non-inverting input end of the comparator is connected with a differential input signal Vip through the first sampling switch Sp, the non-inverting input end of the comparator is also electrically connected with the first end of the first nominal capacitor, and the second end of the first nominal capacitor is grounded; the first weighting capacitor array comprises a plurality of weighting capacitors and a plurality of first three-end control switches S1 corresponding to the weighting capacitors one by one, the first ends of the weighting capacitors in the first weighting capacitor array are all electrically connected with the non-inverting input end of the comparator, and the polar plate corresponding to the first end of the first nominal capacitor and the polar plate corresponding to the first end of the weighting capacitor in the first weighting capacitor array form a first sampling polar plate VSP together; second ends of a plurality of weight capacitors of the first weight capacitor array are respectively and electrically connected with input ends of corresponding first three-end control switches S1, a first output end of each first three-end control switch S1 is connected with a power supply voltage VREFN, a second output end of each first three-end control switch S1 is connected with a power supply voltage VREFP, and a control end of each first three-end control switch S1 is correspondingly and electrically connected with one output end of a switch control module;
the inverting input end of the comparator is connected with the differential input signal Vin through a second sampling switch Sn, the inverting input end of the comparator is also electrically connected with a first end of a second nominal capacitor, a second end of the second nominal capacitor is grounded, and the capacitance value and the polar plate area of the second nominal capacitor and the first nominal capacitor are equal; the second weighted capacitor array comprises a plurality of weighted capacitors and a plurality of second three-end control switches S2 corresponding to the weighted capacitors one by one, the number of the weighted capacitors in the second weighted capacitor array is equal to that of the weighted capacitors in the first weighted capacitor array, the capacitance value and the plate area of each weighted capacitor in the second weighted capacitor array are equal to that of one weighted capacitor in the first weighted capacitor array, the first ends of the weighted capacitors in the second weighted capacitor array are electrically connected with the inverting input end of the comparator, and the plate corresponding to the first end of the second nominal capacitor and the plates corresponding to the first ends of the weighted capacitors in the second weighted capacitor array form a second sampling plate VSN; second ends of a plurality of weight capacitors of the second weight capacitor array are respectively and electrically connected with input ends of corresponding second three-end control switches S2, a first output end of each second three-end control switch S2 is connected with a power supply voltage VREFN, a second output end of each second three-end control switch S2 is connected with a power supply voltage VREFP, and a control end of each second three-end control switch S2 is respectively and electrically connected with a control end of a corresponding first three-end control switch S1;
the auxiliary ADC module is used for generating an auxiliary leakage current Ip1 In a linear relation with the leakage current Ip of the first sampling polar plate VSP and transmitting the auxiliary leakage current Ip1 to the first end of the first sampling switch leakage current compensation module, generating an auxiliary leakage current In1 In a linear relation with the leakage current In of the second sampling polar plate VSN and transmitting the auxiliary leakage current In1 to the first end of the second sampling switch leakage current compensation module, the first sampling switch leakage current compensation module generates a compensation current KIn1 equal to the leakage current In according to the value of the auxiliary leakage current In1 and transmits the compensation current to the first sampling polar plate VSP from the second end of the first sampling switch leakage current compensation module, and the second sampling switch leakage current compensation module generates a compensation current KIp1 equal to the auxiliary leakage current Ip according to the value of the leakage current Ip1 and transmits the compensation current to the second sampling polar plate VSN from.
2. The adc of claim 1, wherein: the capacitance values of the weighting capacitors in the first weighting capacitor array are in a binary relation in sequence, and the weighting capacitor with the minimum capacitance value in the first weighting capacitor array is equal to the capacitance value of the first nominal capacitor.
3. The adc of claim 1, wherein: the auxiliary ADC module comprises a third sampling switch Sp1, a fourth sampling switch Sn1, a third weighted capacitor array, a fourth weighted capacitor array, a third nominal capacitor and a fourth nominal capacitor, wherein the capacitance value and the plate area of the third nominal capacitor and the fourth nominal capacitor are equal, the capacitance value K times of the third nominal capacitor and the plate area K times of the third nominal capacitor are equal to the capacitance value and the plate area of the first nominal capacitor, and K is an integer greater than 1; the third weight capacitor array comprises a plurality of weight capacitors and a plurality of third three-terminal control switches S3 corresponding to the weight capacitors one by one, the number of the weight capacitors in the third weight capacitor array is equal to that of the weight capacitors in the first weight capacitor array, and the capacitance value K times and the electrode plate area K times of each weight capacitor in the third weight capacitor array are equal to that of one weight capacitor in the first weight capacitor array; the first ends of a plurality of weight capacitors in the third weight capacitor array are electrically connected with the first end of a third nominal capacitor, and the second end of the third nominal capacitor is grounded; a polar plate corresponding to the first end of the third nominal capacitor and polar plates corresponding to the first ends of the multiple weighting capacitors in the third weighting capacitor array form a third sampling polar plate VSP 1; the second ends of a plurality of weight capacitors in the third weight capacitor array are respectively and electrically connected with the input end of a corresponding third three-terminal control switch S3, the first output end of each third three-terminal control switch S3 is connected with a power supply voltage VREFN, the second output end of each third three-terminal control switch S3 is connected with a power supply voltage VREFP, and the control end of each third three-terminal control switch S3 is respectively and electrically connected with the control end of a corresponding first three-terminal control switch S1;
the fourth weight capacitor array comprises a plurality of weight capacitors and a plurality of fourth three-terminal control switches S4 corresponding to the weight capacitors one by one, the number of the weight capacitors in the fourth weight capacitor array is equal to that of the weight capacitors in the second weight capacitor array, and the capacitance value K times and the electrode plate area K times of each weight capacitor in the fourth weight capacitor array are equal to that of one weight capacitor in the second weight capacitor array; the first ends of a plurality of weight capacitors in the fourth weight capacitor array are electrically connected with the first end of a fourth nominal capacitor, and the second end of the fourth nominal capacitor is grounded; a polar plate corresponding to the first end of the fourth nominal capacitor and polar plates corresponding to the first ends of the multiple weighting capacitors in the fourth weighting capacitor array form a fourth sampling polar plate VSN 1; the second ends of the multiple weight capacitors in the fourth weight capacitor array are respectively electrically connected with the input end of the corresponding fourth three-terminal control switch S4, the first output end of each fourth three-terminal control switch S4 is connected with the supply voltage VREFN, the second output end of each fourth three-terminal control switch S4 is connected with the supply voltage VREFP, and the control end of each fourth three-terminal control switch S4 is respectively electrically connected with the control end of the corresponding second three-terminal control switch S2.
4. The adc of claim 3, wherein: the first sampling switch Sp, the second sampling switch Sn, the third sampling switch Sp1 and the fourth sampling switch Sn1 are all PMOS transistors, the length-to-width ratio and the channel area of the first sampling switch Sp and the second sampling switch Sn are equal, the length-to-width ratio and the channel area of the third sampling switch Sp1 and the fourth sampling switch Sn1 are equal, and the channel area of the first sampling switch Sp is K times of the channel area of the third sampling switch Sp 1.
5. The adc of claim 3, wherein: each of the three-terminal control switches comprises a PMOS transistor and an NMOS transistor, the length-width ratio and the channel area of the PMOS transistor in the first three-terminal control switch S1 and the second three-terminal control switch S2 are equal, the length-width ratio and the channel area of the NMOS transistor in the first three-terminal control switch S1 and the second three-terminal control switch S2 are equal, the length-width ratio and the channel area of the PMOS transistor in the third three-terminal control switch S3 and the fourth three-terminal control switch S4 are equal, the length-width ratio and the channel area of the NMOS transistor in the third three-terminal control switch S3 and the fourth three-terminal control switch S4 are equal, the channel area of the PMOS transistor in the first three-terminal control switch S1 is K times the channel area of the PMOS transistor in the third three-terminal control switch S3, and the channel area of the NMOS transistor in the first three-terminal control switch S1 is K times the channel area of the NMOS transistor in the third three-terminal control switch S3.
6. The adc of claim 3, wherein: the first sampling switch leakage current compensation module comprises a standard field effect transistor M0 and a plurality of first mirror image field effect transistors M1, the sources of the first mirror image field effect transistors M1 are electrically connected with each other and then are used as the second end of the first sampling switch leakage current compensation module to be electrically connected with a first sampling polar plate VSP, the grids of the first mirror image field effect transistors M1 are electrically connected with the grid of the standard field effect transistor M0, and the drains are connected with a power supply VDD; the source electrode of the standard field effect transistor M0 is used as the first end of the first sampling switch leakage current compensation module and is electrically connected with the third sampling polar plate VSP1, the grid electrode of the standard field effect transistor M0 is electrically connected with the source electrode thereof, and the drain electrode is connected with the power supply VDD; the sum of the channel areas of a plurality of the first mirror field effect transistors M1 is equal to K times the channel area of the standard field effect transistor M0.
7. The adc of claim 6, wherein: the number of the first mirror image field effect transistors M1 is K, and the width-length ratio and the channel area of each first mirror image field effect transistor M1 are equal to those of the standard field effect transistor M0.
8. The adc of claim 7, wherein: the first sampling switch leakage current compensation module further comprises K mirror image switches S5, the drain of each first mirror image field effect transistor M1 is connected with a power supply VDD through a mirror image switch S5, and the control end of each mirror image switch S5 is connected with a corresponding trimming code control signal.
9. The adc of claim 7, wherein: the first sampling switch leakage current compensation module further comprises J second mirror image field effect transistors M2 and (K + J) mirror image switches S5, the channel area of each second mirror image field effect transistor M2 is smaller than that of a standard field effect transistor M0, the source of J second mirror image field effect transistors M2 and the source of K first mirror image field effect transistors M1 are electrically connected with each other and then serve as the second end of the first sampling switch leakage current compensation module to be electrically connected with the first sampling electrode plate VSP, the gates of J second mirror image field effect transistors M2 are electrically connected with the gate of the standard field effect transistor M0, the drains are respectively connected with a power supply VDD through one mirror image switch S5, the drain of each first mirror image field effect transistor M1 is respectively connected with the power supply VDD through one mirror image switch S5, and the control end of each mirror image switch S5 is respectively connected with a corresponding trimming code control signal.
10. The adc as claimed in any one of claims 6 to 9, wherein: and the structure of the second sampling switch leakage current compensation module is the same as that of the first sampling switch leakage current compensation module.
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