CN111180384A

CN111180384A - Interconnect structure and method of forming the same

Info

Publication number: CN111180384A
Application number: CN201911093292.7A
Authority: CN
Inventors: 王菘豊; 梁顺鑫; 张容浩; 朱家宏; 林耕竹
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-11-09
Filing date: 2019-11-11
Publication date: 2020-05-19
Anticipated expiration: 2039-11-11
Also published as: CN111180384B; TWI801631B; TW202018808A

Abstract

Embodiments described herein relate generally to one or more methods for forming interconnect structures, such as dual damascene interconnect structures including conductive lines and conductive vias, and structures formed thereby. In some embodiments, interconnect openings are formed through one or more dielectric layers above the semiconductor substrate. The interconnect opening has a via opening and a trench located above the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is applied to one or more exposed dielectric surfaces of the trench. Conductive lines are formed in the trenches on the one or more exposed dielectric surfaces of the trenches and on the conductive vias. Embodiments of the present invention also relate to interconnect structures.

Description

Interconnect structure and method of forming the same

Technical Field

Embodiments of the invention relate to interconnect structures and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have resulted in multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In IC evolution processes, the functional density (e.g., the number of interconnected devices per chip area) has generally increased, while the geometry (e.g., the smallest component or line that can be produced using the fabrication process) has decreased. Such a scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. However, scaling down also results in challenges that may not have been presented by previous generations at larger geometries.

Disclosure of Invention

Embodiments of the present invention provide a method for forming an interconnect structure, comprising: etching an interconnect opening through one or more dielectric layers over a semiconductor substrate, the interconnect opening having a via opening and a trench over the via opening, the via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a first layer of a first conductive material; treating the via opening with a plasma to physically remove etch residues from sidewalls and bottom of the via opening; soaking the conductive member with a halide of the first conductive material, the residual halide of the first conductive material remaining in the via opening after soaking; reducing the residual halide of the first conductive material to form a second layer of the first conductive material on the first layer; depositing a conductive via in the via opening on the second layer of the first conductive material; and forming a conductive line on one or more exposed dielectric surfaces of the trench and in the trench over the conductive via.

Another embodiment of the present invention provides a method for forming an interconnect structure, comprising: etching an interconnect opening through one or more dielectric layers over a semiconductor substrate, the interconnect opening having a via opening and a trench over the via opening, the via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a conductive material; cleaning the through hole opening; depositing a conductive via in the cleaned via; subjecting one or more exposed dielectric surfaces of the trench to a nucleation enhancement treatment; and forming a conductive line on one or more exposed dielectric surfaces of the trench and in the trench over the conductive via.

Yet another embodiment of the present invention provides a method for forming an interconnect structure, comprising: depositing a conductive component over a substrate, the depositing comprising providing a plurality of precursors for a first conductive material; depositing one or more dielectric layers over the conductive features; etching an interconnect opening through the one or more dielectric layers, the interconnect opening having a via portion and a line portion above the via portion; cleaning the sidewalls and bottom surfaces of the interconnect opening with a halide of the first conductive material, which is a precursor for the first conductive material; depositing a conductive via in the via portion of the cleaned interconnect opening, the conductive via contacting the conductive feature; and depositing a conductive line in the line portion of the cleaned interconnect opening.

Yet another embodiment of the present invention provides an interconnect structure, comprising: a semiconductor substrate; one or more dielectric layers over the semiconductor substrate; and an interconnect structure disposed in the one or more dielectric layers, the interconnect structure comprising: a conductive via; and a conductive line over the conductive via, the conductive line disposed over a horizontal surface of the one or more dielectric layers, the same substance disposed at the horizontal surface of the one or more dielectric layers and at an upper surface of the conductive via at an interface between the conductive via and a conductive fill material of the conductive line.

Yet another embodiment of the present invention provides an interconnect structure, comprising: a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive via extending through the first dielectric layer, the conductive via comprising a first conductive material; a second dielectric layer over the first dielectric layer; and a conductive line extending through the second dielectric layer, the conductive line including a second conductive material, the conductive line sharing a first interface with the conductive via, the conductive line sharing a second interface with a horizontal surface of the first dielectric layer, the conductive line sharing a third interface with a vertical surface of the second dielectric layer, the same substance being disposed at the first interface, the second interface, and the third interface, the first interface and the second interface having more substance than the third interface, the substance being different from the first conductive material and the second conductive material.

Yet another embodiment of the present invention provides an interconnect structure, comprising: a semiconductor substrate; a first conductive feature over the semiconductor substrate; one or more dielectric layers over the first conductive features; a first interconnect structure disposed in the one or more dielectric layers, the first interconnect structure comprising a conductive via and a conductive line, the conductive via and the conductive line contacting horizontal surfaces of the one or more dielectric layers and vertical surfaces of the one or more dielectric layers, the same species being disposed at the horizontal surfaces of the one or more dielectric layers and the vertical surfaces of the one or more dielectric layers; and a second conductive component over the first interconnect structure, wherein the conductive via includes a first conductive material that extends continuously between the first conductive component and the conductive line, and wherein the conductive line includes a second conductive material that extends continuously between the conductive via and the second conductive component.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1-10 are cross-sectional views of respective intermediate structures during an exemplary method for forming an interconnect structure according to some embodiments.

Figure 11 is a flow diagram of an exemplary method for forming an interconnect structure according to some embodiments.

Fig. 12 is a flow diagram of an exemplary Atomic Layer Etch (ALE) process, in accordance with some embodiments.

Fig. 13-18 are cross-sectional views of various details and/or modifications of portions of the intermediate structure of fig. 6, according to some embodiments.

Fig. 19-20 are cross-sectional views of respective intermediate structures during an exemplary method for forming an interconnect structure according to some other embodiments.

Figure 21 is a flow diagram of an exemplary cleaning process, according to some embodiments.

Figure 22 is a cross-sectional view of a resulting interconnect structure according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Embodiments described herein relate generally to one or more methods for forming an interconnect structure in a semiconductor process, such as a dual damascene interconnect structure including conductive lines and conductive vias. In general, a conductive via may be selectively deposited in a via opening for an interconnect structure, after which a nucleation enhancement process may be performed, and subsequently a conductive fill material may be deposited in a trench for the interconnect structure. The nucleation enhancement treatment may cause the deposition of the conductive fill material to be bottom-up and/or conformal, such as by nucleation and deposition on the dielectric surface. Some embodiments may avoid the use of a seed layer to deposit the conductive fill material, and may further avoid the use of a high resistance metal-containing barrier layer in the interconnect structure. Accordingly, some process windows for forming the interconnect structure may be increased, and the resistance of the interconnect structure may be reduced. In some embodiments, a cleaning process is performed prior to the nucleation enhancement treatment to clean exposed surfaces of the via openings for the interconnect structures. The cleaning process may include a number of processes, such as physical and chemical removal processes. Some embodiments may also help remove native oxide that may form in the via opening and may reduce the chance of void formation during deposition of the conductive via. Therefore, the resistance of the interconnect structure can be further reduced. Other advantages or benefits may also be realized.

Some embodiments described herein are in the context of back end of line (BEOL) processes. Other processes and structures within the scope of other embodiments may be implemented in other contexts, such as in a middle of line (MEOL) process and in other contexts. Various modifications are discussed with reference to the disclosed embodiments; however, other modifications may be made to the disclosed embodiments while remaining within the scope of the subject matter. Those of ordinary skill in the art will readily appreciate other modifications that may be contemplated within the scope of other embodiments. Although method embodiments may be described in a particular order, various other method embodiments may be implemented in any logical order and may include fewer or more steps than those described herein.

Fig. 1-10 illustrate cross-sectional views of respective intermediate structures during exemplary methods for forming interconnect structures according to some embodiments. Fig. 11 is a flow diagram of an exemplary method 200 for forming an interconnect structure according to some embodiments.

Fig. 1 and operation 202 of method 200 illustrate forming a dielectric layer over a semiconductor substrate 20. Fig. 1 shows a first dielectric layer 22 over a semiconductor substrate 20. The semiconductor substrate 20 may be or include a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include elemental semiconductors such as silicon (Si) and germanium (Ge); a compound semiconductor; an alloy semiconductor; or a combination thereof.

Various devices may be located on the semiconductor substrate 20. For example, the semiconductor substrate 20 may include a Field Effect Transistor (FET), such as a Fin FET (FinFET), a planar FET, a vertical gate all around FET (VGAA FET), or the like; a diode; a capacitor; an inductor; and other devices. For example, the devices may be formed entirely within the semiconductor substrate 20, entirely within portions of the semiconductor substrate 20 and portions of one or more overlying layers, and/or entirely within one or more overlying layers. The processes described herein may be used to form and/or interconnect devices to form integrated circuits. The integrated circuit may be any circuit, such as for an Application Specific Integrated Circuit (ASIC), a processor, a memory, or other circuitry.

First of allA dielectric layer 22 is located over the semiconductor substrate 20. The first dielectric layer 22 may be located directly on the semiconductor substrate 20, or any number of other layers may be disposed between the first dielectric layer 22 and the semiconductor substrate 20. For example, the first dielectric layer 22 may be or include an inter-metal dielectric (IMD) or an inter-layer dielectric (ILD). The first dielectric layer 22 may be or include, for example, a low-k dielectric having a k value of less than about 4.0, such as about 2.0 or even lower. In some examples, first dielectric layer 22 includes silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO_xC_yA silicon carbon material, a compound thereof, a composite thereof, or a combination thereof.

The conductive features 24 are located in the first dielectric layer 22 and/or pass through the first dielectric layer 22. The conductive features 24 may be or include conductive lines and/or vias, gate structures of transistors, or contact plugs to gate structures of transistors and/or source/drain regions of transistors. In some examples, the first dielectric layer 22 is an IMD, and the conductive features 24 may include conductive lines and/or conductive vias (collectively or individually referred to as "interconnect structures"). The interconnect structure may be formed by, for example, using a damascene process to form openings and/or recesses through and/or in the IMD. Some examples of forming interconnect structures are described further below, but other processes and interconnect structures may be implemented. In other examples, the first dielectric layer 22 may comprise an ILD and the conductive feature 24 may comprise a gate electrode (e.g., tungsten, cobalt, etc.) in the ILD formed, for example, using a replacement gate process. In another example, the first dielectric layer 22 may be an ILD and the conductive features 24 may include contact plugs. Contact plugs may be formed by forming openings through the ILD to, for example, gate electrodes and/or source/drain regions of transistors formed on the semiconductor substrate 20. The contact plug may include an adhesion layer (e.g., Ti, etc.), a barrier layer (e.g., TiN, etc.) on the adhesion layer, and a conductive fill material (e.g., tungsten, cobalt, etc.) on the barrier layer. The contact plug can also be made of a less diffusive metal, such as tungsten, Mo or Ru, without a barrier layer.

A first Etch Stop Layer (ESL)26 is located over the first dielectric layer 22 and the conductive feature 24. In general, ESLs may provide a mechanism to stop the etching process when forming, for example, contacts or conductive vias. The ESL may be formed of a dielectric material having a different etch selectivity than adjacent layers or components. A first ESL26 is deposited on the top surfaces of the first dielectric layer 22 and the conductive features 24. The first ESL26 may comprise or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or combinations thereof, and may be deposited by Chemical Vapor Deposition (CVD), Plasma Enhanced CVD (PECVD), Atomic Layer Deposition (ALD), or other deposition techniques. In some examples, the thickness of the first ESL26 is in a range from about 3nm to about 10 nm.

A second dielectric layer 28 is located over the first ESL 26. For example, the second dielectric layer 28 may be or include an IMD. A second dielectric layer 28 is deposited on the top surface of the first ESL 26. The second dielectric layer 28 may be or include, for example, a low-k dielectric having a k value of less than about 4.0, such as about 2.0 or even less. In some examples, second dielectric layer 28 includes silicon oxide, PSG, BPSG, FSG, SiO_xC_yA silicon carbon material, a compound thereof, a composite thereof, or a combination thereof. The second dielectric layer 28 may be deposited using CVD, such as PECVD or Flowable CVD (FCVD); spin coating; or other deposition techniques. In some examples, a Chemical Mechanical Planarization (CMP) or other planarization process may be performed to planarize the top surface of the second dielectric layer 28. In some examples, the thickness of the second dielectric layer 28 is in a range from about 4nm to about 30 nm.

A second ESL30 is located over the second dielectric layer 28. A second ESL30 is deposited on the top surface of the second dielectric layer 28. The second ESL30 may comprise or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or combinations thereof, and may be deposited by CVD, PECVD, ALD, or other deposition techniques. In some examples, the thickness of the second ESL30 is in a range from about 3nm to about 10 nm.

A third dielectric layer 32 is located over the second ESL 30. For example, the third dielectric layer 32 may be or include an IMD. A third dielectric layer 32 is deposited on the top surface of the second ESL 30. The third dielectric layer 32 may be or include, for example, a k value of less than about 4.0 (such as about 2.0 orEven smaller) low-k dielectrics. In some examples, the third dielectric layer 32 includes silicon oxide, PSG, BPSG, FSG, SiO_xCy, silicon carbon material, compound thereof, or combination thereof. The third dielectric layer 32 may be deposited using CVD, such as PECVD or FCVD; spin coating; or other deposition techniques. In some examples, a CMP or other planarization process may be performed to planarize the top surface of the third dielectric layer 32. In some examples, the thickness of the third dielectric layer 32 is in a range from about 20nm to about 50nm, such as about 45 nm.

The configuration of the second dielectric layer 28, the second ESL30, and the third dielectric layer 32 of fig. 1 is an example. In other examples, the second ESL30 may be omitted between the second dielectric layer 28 and the third dielectric layer 32. Further, in some examples, a single dielectric layer may be formed in place of the second dielectric layer 28, the second ESL30, and the third dielectric layer 32. These and other modifications that can be made will be readily apparent to those of ordinary skill in the art.

Fig. 2 and operation 204 of the method 200 illustrate the formation of via openings 42 and trenches 40 in and/or through the first ESL26, the second ESL 28, the second ESL30, and the third dielectric layer 32 in the first ESL26, the second dielectric layer 28, the second ESL30, and the third dielectric layer 32. The via opening 42 and the trench 40 may be formed using a photolithography and etching process, such as in a dual damascene process. For example, a photoresist may be formed on the third dielectric layer 32, such as by using spin coating, and patterned to have a pattern corresponding to the trenches 40 by exposing the photoresist to light using an appropriate photomask. The exposed or unexposed portions of the photoresist may then be removed depending on whether a positive or negative photoresist is used. The pattern of photoresist may then be transferred to the third dielectric layer 32, such as by using a suitable etching process that forms a trench 40 in the third dielectric layer 32. The etching process may include Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), Inductively Coupled Plasma (ICP) etching, or the like, or a combination thereof. The etching process may be anisotropic. The second ESL30 may serve as an etch stop layer for the etching process. The photoresist is then removed, for example, in an ashing or wet strip process. Thereafter, another photoresist may be formed in the third dielectric layer 32 and the trench 40, such as by using spin coating, and patterned to have a pattern corresponding to the via opening 42 by exposing the photoresist to light using an appropriate photomask. The pattern of photoresist may then be transferred through the second ESL30, the second dielectric layer 28, and the first ESL26, such as by using one or more suitable etching processes that form a via opening 42 through the second ESL30, the second dielectric layer 28, and the first ESL 26. The etching process may include RIE, NBE, ICP etching, etc., or a combination thereof. The etching process may be anisotropic. The photoresist is then removed, for example, in an ashing or wet strip process.

The sidewalls of the trench 40 and via opening 42 are shown as being substantially vertical and having rounded corners. For example, the linear portion of the sidewall forms an angle measured within the respective second or third

dielectric layer

28, 32 in a range from about 85 to about 90, such as about 85 to about 89, and more specifically about 87. In other examples, the sidewalls of one or both of the trench 40 and the via opening 42 may be vertical, or may taper together in a direction toward or away from the bottom of the via opening 42. For example, the via opening 42 may have a positive tapered profile or a concave profile. Various examples of configurations for the via openings 42 and details thereof are shown and described in fig. 13-18.

In the exemplary configuration of fig. 2, the trench 40 has a first width W1 in the plane of the top surface of the third dielectric layer 32 and a second width W2 along the bottom surface of the trench 40. In some examples, the first width W1 is in a range from about 20nm to about 40nm, and in some examples, the second width W2 is in a range from about 18nm to about 36 nm. In this example, the depth of the trench is equal to the first thickness T1 of the third dielectric layer 32. As previously described, in some examples, the first thickness T1 is in a range from about 20nm to about 50 nm. A first aspect ratio of the first thickness T1 to the first width W1 may be in a range from about 0.5 to about 2.5, and a second aspect ratio of the first thickness T1 to the second width W2 may be in a range from about 0.56 to about 2.78.

At the side wall of the trenchIn an exemplary configuration that is vertical, the widths corresponding to the first width W1 and the second width W2 in fig. 2 are equal, and each width may range from about 20nm to about 40 nm. In this example, the aspect ratio of the first thickness T1 to the width of the trench 40 may be in the range from about 0.5 to about 2.5. In an exemplary configuration where the sidewalls of the trench taper (e.g., a positive tapered profile), the width corresponding to the first width W1 in fig. 2 may be a width (W) corresponding to the second width W2 in fig. 2_lower) And a function of the angle (θ) of the sidewall (e.g., W) measured inside the third dielectric layer 32_upper＝W_lower+[2T₁(tanθ)^-1]). Corresponding to the second width W in fig. 2₂May range from about 18nm to about 36nm, and the angle may range from about 85 to about 89, or may be less than 85. An aspect ratio of the first thickness T1 to a width corresponding to the second width W2 of fig. 2 may be in a range from about 0.56 to about 2.78.

One of ordinary skill in the art will readily appreciate that the dimensions, ratios, and angles described herein are merely examples. The dimensions, ratios, and angles may vary based on the technology in which the various aspects are implemented to generate the nodes and/or based on the various processes used. Such variations are within the scope of the invention.

Operation 206 of fig. 3 and method 200 shows conformally forming the liner layer 50 along the sidewalls of the via opening 42 and trench 40, along the respective bottom surfaces of the via opening 42 and trench 40, and along the top surface of the dielectric layer 32. The liner layer 50 may be formed by conformal deposition. The liner layer 50 may be or include silicon nitride (SiN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon-containing low-k dielectrics, carbon-containing low-k dielectrics, or the like, or combinations thereof, and may be deposited by CVD, ALD, or other deposition techniques. In some examples, the thickness of the spacer layer 50 is in a range from about 1nm to about 4nm, and more specifically, in a range from about 2nm to about 3 nm.

Fig. 4 and operation 208 of method 200 illustrate forming a respective liner 52 from liner layer 50 along sidewalls of via opening 42 and along sidewalls of trench 40. The liner 52 may be formed by anisotropically etching the liner layer 50. The etching process for anisotropically etching the liner layer 50 may include RIE, NBE, ICP etching, etc., or a combination thereof. The liner 52 and the second ESL30 (if implemented) may be diffusion barriers that may reduce or prevent out-diffusion of conductive fill material subsequently deposited in the trench 40 and via opening 42, for example, to the second dielectric layer 28 and the third dielectric layer 32. The liner 52 and the second ESL30 may form a dielectric diffusion barrier.

The profile of the liner 52 may vary depending on the profile of the sidewalls of the trench 40 and the via opening 42, and the like. In the example of fig. 4, the second thickness T is at a corner rounding at the side wall where the slope of the corner is about 45 degrees₂May be substantially equal to the thickness T of the liner layer 50 minus the thickness (T) removed by the anisotropic etch in the vertical direction_{Etching of}) Squaring by 2, dividing by 2 (e.g., T- [ T)_{Etching of}x 2^-(1/2)]). Further, the third thickness T3 along the substantially vertical portion of the respective sidewall at the bottom of the trench 40 or via opening 42 may be equal to the thickness T of the liner layer 50. In some examples, the second thickness T2 is in a range from about 0.3nm to about 1.2nm, and the third thickness T3 is in a range from about 1nm to about 4 nm. One of ordinary skill in the art will readily appreciate the relationship between the thickness of the liner 52 and the angle of inclination of the underlying sidewall.

In an exemplary configuration where the sidewalls of the trench are vertical, corresponding to the second thickness T in FIG. 4₂And a third thickness T₃May be equal (which may further be substantially equal to the thickness T of the spacer layer 50), each may be in the range from about 1nm to about 4 nm. In an exemplary configuration where the sidewalls of the trench taper at a constant angle of inclination (e.g., a positive tapered profile), corresponding to the second thickness T in fig. 4₂And a third thickness T₃Are equal in thickness. As understood by one of ordinary skill in the art, the thickness may be a function of the thickness T of the liner layer 50 and the angle of the sidewalls, similar to that described above. The width corresponding to the second width W2 in fig. 2 may be in the range from about 1nm to about 4 nm.

The profile of liner 52 may further vary depending on the step coverage of the deposition process used to deposit liner layer 50. For example, the thickness of liner 52 along the sidewalls of via opening 42 may be different than the thickness of liner 52 along the sidewalls of trench 40 due to the step coverage variation.

In operation 210 of the method 200, after forming the liner 52, optionally, a cleaning process may be performed to clean exposed surfaces of, for example, the trench 40 and the via opening 42. The cleaning process may include a plasma treatment, an etching process, another cleaning process, or a combination thereof. In an example, the cleaning process includes a plasma treatment (operation 212) followed by an Atomic Layer Etch (ALE) (operation 214). The plasma treatment in operation 212 may include using hydrogen gas (H)₂) With a carrier gas such as argon (Ar). In some cases, the plasma treatment may reduce oxides that may form on the surfaces of the conductive features 24 exposed through the via openings 42 and may remove organic materials that may form on the respective surfaces. The flow rate of the hydrogen gas in the plasma treatment may be in a range of about 5sccm to about 1,000sccm, and the flow rate of the carrier gas in the plasma treatment may be in a range of about 0sccm to about 1,000 sccm. The pressure of the plasma treatment may be in the range of about 10mTorr to about 200 mTorr. The temperature of the plasma treatment may range from about-20 ℃ to about 100 ℃. The power of the plasma generator of the plasma treatment may be in the range of about 20W to about 400W, and the frequency of the plasma generator may be about 13.56MHz or greater. The substrate during plasma processing may be biased in a range of about 20V to about 100V. The duration of the plasma treatment may be in the range of about 5 seconds to about 120 seconds.

The ALE in operation 214 is illustrated in further detail in fig. 12. The ALE in operation 214 may include implementing a plurality of cycles, such as in a range of 2 cycles to 25 cycles. Cycling of the ALE may include sequentially passing a reactant gas (operation 250), such as boron trichloride (BCl)₃) Flowing a gas with a carrier gas (e.g., argon (Ar)), purging (operation 252) a reactant gas, flowing an etchant gas (operation 254), such as hydrogen (H)₂) Flow with a carrier gas (e.g., argon (Ar)) and possible plasma enhancement; and purging (operation 256) the etchantA gas. In some examples, a reactive gas (e.g., boron trichloride (BCl)₃) Gas is adsorbed on the dielectric surface to form a monolayer and does not adsorb significantly on the metal surface, and the monolayer is passed through, for example, hydrogen (H)₂) Is etched by the flow of the etchant gas. An example provided herein is boron trichloride (BCl) as the reactant gas₃) Gas and hydrogen (H) as etchant gas₂) A gas; other gases may be used. In boron trichloride (BCl)₃) During the flow of the gas, boron trichloride (BCl)₃) The flow rate of the gas can be in a range of about 20sccm to about 180sccm, and the flow rate of the carrier gas can be in a range of about 200sccm to about 800 sccm. Furthermore, in boron trichloride (BCl)₃) During the flow of the gas, the ALE may have a pressure in a range of about 15mTorr to about 100mTorr, and the ALE may have a temperature in a range of about-20 ℃ to about 60 ℃. After purging boron trichloride, hydrogen (H)₂) Flow is initiated and the plasma is ignited. In the presence of hydrogen (H)₂) During the flow, hydrogen (H)₂) The flow rate of (a) may be in a range of about 5sccm to about 1,000sccm, and the flow rate of the carrier gas may be in a range of about 50sccm to about 400 sccm. In addition, in hydrogen (H)₂) During flow, the pressure of the ALE may be in the range of about 10mTorr to about 200mTorr, and the temperature of the ALE may be in the range of about-20 ℃ to about 20 ℃. The power of the plasma generator of the ALE may be in the range of about 10W to about 800W, and the frequency of the plasma generator may be about 13.56MHz or greater. The substrate during the plasma of the ALE may be biased in the range of about 50V to about 300V.

The above process is one example of a cleaning process (operation 210). In some embodiments (described further below with reference to fig. 19-22), the cleaning process includes a plasma treatment followed by a halide soak, followed by a reduction treatment.

In operation 216 of the method 200, a selective enhancement treatment may optionally be applied to exposed dielectric surfaces, such as the trenches 40 and via openings 42, after optionally performing the cleaning process in operation 210. The selectivity enhancing treatment may, for example, treat and/or passivate the dielectric surface such that subsequent metal deposition has a higher selectivity than without such treatment, such that metal is deposited at a greater rate on the metal surface than on the dielectric surface. For example, the selectivity enhancing treatment may render the dielectric surface hydrophobic, which may improve selectivity during subsequent metal deposition. The selective enhancement treatment may include flowing a silicon-containing hydrocarbon gas over the dielectric surface. The selective enhancing treatment may be a Trimethylsiloxy (TMS) treatment, a Dimethylsiloxy (DMS) treatment, or the like, or a combination thereof. Examples of silicon-containing hydrocarbon gases include 1,1,1,3,3, 3-Hexamethyldisilazane (HDMS), chlorotrimethylsilane (TMCS), N, O-bis (trimethylsilyl) acetamide (BSA), N- (trimethylsilyl) dimethylamine (TMS-DMA), TMS-imidazole (SIM, N-trimethylsilylimidazole), 1,1,3, 3-Tetramethyldisilazane (TMDS), chlorodimethylsilane (DMCS), the like, or combinations thereof. The selectivity enhancing treatment may cause a silylation process in which atoms or groups of atoms terminating at the dielectric surface may be substituted with species silicon-containing hydrocarbons, which may render the dielectric surface hydrophobic. The flow rate of the silicon-containing hydrocarbon can be in a range of about 5sccm to about 100sccm and the flow rate of the carrier gas flowing with the silicon-containing hydrocarbon can be in a range of about 0sccm to about 400 sccm. The pressure during the silicon-containing hydrocarbon flow may be in the range of about 1mTorr to about 100mTorr, and the temperature may be in the range of about 20 ℃ to about 300 ℃. The selectivity enhancement process may treat or passivate the exposed dielectric surfaces of the liner 52, the second ESL30, and the third dielectric layer 32 to improve selectivity of subsequent selective deposition on the conductive features 24.

Fig. 5 and operation 218 of method 200 illustrate forming conductive via 60 in via opening 42. The formation of the conductive via 60 may include selective deposition. For example, the selective deposition may use the conductive features 24 exposed through the via openings 42 as seeds. Selective deposition may include electroless deposition or plating, selective CVD, or other techniques. The conductive via 60 may be or include a metal, such as cobalt (Co), ruthenium (Ru), or the like, or combinations thereof. In an example, the conductive vias 60 are cobalt deposited using electroless plating or plating. The electroless deposition or plating of cobalt (Co) may be in a temperature range equal to or less than about 200 ℃, such as inRoom temperature (e.g., about 23 ℃) to about 200 ℃. Selective CVD may include using a material comprising Ru₃(CO)₁₂、C₁₀H₁₀Ru、C₇H₉RuC₇H₉、Ru(_C5(CH₃)₅)₂Etc., or a combination thereof, and a carrier gas, such as argon (Ar). The flow rate of the precursor gas may be in a range of about 5sccm to about 100sccm, and the flow rate of the carrier gas may be in a range of about 10sccm to about 400 sccm. The pressure of selective CVD may be in the range of about 0.2mTorr to about 20 mTorr. The temperature of selective CVD may be less than or equal to about 200 ℃, such as in the range of room temperature (e.g., about 23 ℃) to about 200 ℃.

As shown in fig. 5, the upper surface of the conductive via 60 is convex. In other examples, the upper surface of the conductive via 60 may be concave or flat. Various examples of configurations of the conductive vias 60 formed in the via openings 42 and details thereof are shown and described in fig. 13-18.

As shown in fig. 5, some residual deposition sites 62 may be formed during the selective deposition for forming the conductive vias 60. The residual deposition sites 62 may be formed on various surfaces, such as the surfaces of the second ESL30 and the liner 52 in the trench 40.

Operation 220 of fig. 6 and method 200 illustrates the implementation of a selective etch back to remove the remaining deposition sites 62. The etch-back may be a dry (e.g., plasma) etch process, a wet etch process, or a combination thereof. The plasma etch process may include using fluorinated carbon (C)_xF_y) Gas, chlorofluorocarbons (C)_xCl_yF_z) Gas, carbon chloride (C)_xCl_y) Gases, and the like or combinations thereof. The wet etch process may include using one or more of standard clean-1 (SC1), standard clean-2 (SC2), sulfuric acid-hydrogen peroxide mixture (SPM), dilute hydrofluoric acid (dHF) acid, hydrogen peroxide (H)₂O₂) Buffered Oxide Etch (BOE) solutions, hydrochloric acid (HCl), the like, or combinations thereof. The temperature of the solution may range from about 20 ℃ to about 90 ℃, and the duration of immersion of the substrate in the solution may range from about 10 seconds to about 120 secondsAnd (4) the following steps.

Fig. 7 and operation 222 of method 200 illustrate the implementation of a nucleation enhancing treatment along exposed surfaces in trench 40, e.g., including the upper surface of conductive via 60, to form treated surface 70. Typically, the nucleation enhancing treatment breaks bonds along exposed surfaces, such as in trenches 40, to enhance the ability to adsorb materials in a subsequent deposition process. In some examples, the nucleation enhancement process includes sputtering (operation 224), implantation (operation 226), plasma treatment (operation 228), Ultraviolet (UV) treatment (operation 230), plasma doping (operation 232), or the like, or combinations thereof. The nucleation enhancement treatment may be directional (e.g., anisotropic) or conformal (e.g., isotropic). In some examples, the nucleation enhancement treatment may treat, for example, vertical surfaces, although to a lesser extent than, for example, horizontal surfaces. The extent to which the nucleation enhancing treatment is performed (e.g., the extent to which bonds are broken along the surface) may affect the plurality of nucleation sites and, thus, at least the initial deposition rate for the later deposited conductive fill material 80, as will be described later. Generally, the more bonds that are broken and the more dangling bonds that are created, the nucleation sites may be used for adsorption and nucleation of the conductive fill material 80 to increase the deposition rate, at least the initial rate of deposition. In some instances, the nucleation enhancement process may be directional to process substantially only horizontal surfaces (e.g., the top surface of the second ESL30 exposed by the trench 40 and the upper surface of the conductive via 60), which enables bottom-up deposition of the conductive fill material in the trench 40 and reduces cracks and voids formed in the conductive fill material in the trench 40.

In an example, the nucleation enhancing treatment is sputtering using argon (Ar) gas (operation 224). The flow rate of argon can be in the range of about 10sccm to about 2,000 sccm. The pressure of sputtering can be in the range of about 0.5mTorr to about 50mTorr, and the temperature of sputtering can be in the range of about-20 ℃ to about 120 ℃. The power of the sputtering plasma generator may be in the range of about 100W to about 2,000W, and the frequency of the plasma generator may be about 13.56MHz or higher. The substrate may be biased in the range of about 50V to about 300V during sputtering. Sputtering may be directional (e.g., point)Horizontal surfaces), but in some instances sputtering may be conformal. Sputtering can cause argon to be deposited on the treatment surface 70 and/or to embed into the respective material to a depth below the treatment surface 70. For example, a species for sputtering (e.g., argon) may be embedded into the material forming the processing surface 70 (e.g., the conductive via 60, the second ESL30, the liner 52 in the trench 40, and the third dielectric layer 32) to a depth from the corresponding material of the processing surface 70 of equal to or less than about 2nm and at a concentration of about 1x10¹⁸cm^-3To about 1x10¹⁹cm^-3Within the range of (1). The concentration of the substance may decrease from a peak near the corresponding treatment surface 70 to a certain depth in the material. Sputtering can break bonds by atomic collisions of species with exposed material (e.g., the processing surface 70).

In another example, the nucleation enhancement process is a beam-line implant (operation 226). The species used for the beam-line implant may include silicon (Si), germanium (Ge), carbon (C), nitrogen (N), argon (Ar), etc., or combinations thereof. The implantation energy may range from about 2keV to about 10 keV. The implant dose may be about 10¹³cm^-2To about 2x10¹⁵cm^-2Within the range of (1). The implant may be from the corresponding exposed surface to a depth in the range of about 1nm to about 4nm, and the concentration of the implanted species is about 5x10¹⁸cm^-3To about 5x10²¹cm^-3Within the range of (1). The concentration of the substance may decrease from a peak near the corresponding treatment surface 70 to a certain depth in the material. The beam line implant may be directional, but in some instances multiple implants may be performed to achieve more conformal processing. The beam line implant may break bonds by atomic collisions of the implanted species with the implanted material (e.g., the processing surface 70).

In other examples, the nucleation enhancing treatment is a plasma treatment (operation 228). The plasma treatment may include using a gas containing xenon (Xe), argon (Ar), hydrogen (H)₂) Nitrogen (N)₂) Etc. or combinations thereof. The flow rate of the gas can be in a range of about 10sccm to about 2,000 sccm. The pressure of the plasma treatment may be in the range of about 10mTorr to about 100mTorr, and the temperature of the plasma treatment may beTo be in the range of about-20 c to about 60 c. The power of the plasma generator of the plasma treatment may be in the range of about 20W to about 200W, and the frequency of the plasma generator may be about 13.56MHz or greater. The substrate during plasma processing may be biased in a range of about 50V to about 300V. The species of the plasma may damage the exposed surface and may diffuse into the exposed surface. The plasma treatment may be conformal or directional. The plasma treatment may cause species of the plasma to embed in the treatment surface 70 and/or diffuse in the corresponding material to a depth below the treatment surface 70. For example, species for the plasma (e.g., xenon, argon, hydrogen, etc.) may diffuse into the material forming the processing surface 70 (e.g., the conductive via 60, the second ESL30, the liner 52 in the trench 40, and the third dielectric layer 32) to a depth from the corresponding material of the processing surface 70 that is equal to or less than about 5nm and is at about 1x10¹⁸cm^-3To about 1x10²⁰cm^-3At a concentration within the range of (a). The concentration of the substance may decrease from a peak near the corresponding treatment surface 70 to a certain depth in the material.

In yet another example, the nucleation enhancement treatment is a UV treatment (operation 230). The UV treatment may include exposing the substrate to UV light in the environment. The environment may include a gas containing argon (Ar), neon (Ne), xenon (Xe), etc., or combinations thereof. The energy of the UV light exposure may be in the range of about 3.4eV to about 10 eV. The duration of the UV light exposure may be equal to or less than about 300 seconds, such as in the range of about 15 seconds to about 300 seconds. UV treatment can cause bonds on the exposed surface to break, thereby damaging the exposed surface. Environmental species during UV treatment can diffuse into the exposed surface. For example, species of the environment (e.g., xenon, argon, neon, etc.) may diffuse into the material forming the processing surface 70 (e.g., the conductive via 60, the second ESL30, the liner 52 in the trench 40, and the third dielectric layer 32) to a depth from the corresponding material of the processing surface 70 that is equal to or less than about 5 nm. The concentration of the substance may decrease from a peak near each of the treatment surfaces 70 to a depth in the material. The UV treatment may be directional, but in some instances, multiple UV treatments may be implemented to achieve a more conformal treatment.

In a further example, the nucleation enhancing treatment is plasma doping (operation 232). The species used for plasma doping may include boron (B), argon (Ar), or the like, or combinations thereof. The doping can be to a depth of the corresponding exposed surface in the range of about 1nm to about 5nm and at a concentration of about 1x10¹⁹cm^-3To about 1x10²⁰cm^-3Within the range of (1). The concentration of the substance may decrease from a peak near the corresponding treatment surface 70 to a certain depth in the material. Plasma doping can break bonds by atomic collisions of the implanted species with the implanted material (e.g., the processing surface 70).

Fig. 8 and operation 234 of method 200 illustrate forming a conductive fill material 80 on the processing surface 70, e.g., filling the trench 40. Formation of the conductive fill material 80 can be deposited on the dielectric surface as well as the metal surface by a deposition process. The nucleation enhancement process described with respect to fig. 7 may create nucleation sites on the dielectric surface (e.g., on the process surface 70) on which the conductive fill material 80 may be adsorbed during deposition. Thus, the deposition of the conductive fill material 80 may be a bottom-up deposition and/or a conformal deposition, such as depending on the directionality of the nucleation enhancement process. In bottom-up deposition, cracks may be avoided by causing a single growth front of the conductive fill material 80 to propagate vertically in the trench 40.

Due to the conformal deposition, cracks 82 may form in the conductive fill material 80 in the trenches 40. The crack 82 may result from the merging or coalescence of different growth fronts of the conductive fill material 80 during conformal deposition. For example, a growth front originating from the sidewall surface of the liner 52 along the sidewalls of the third dielectric layer 32 may coalesce or merge with a growth front originating from the top surface of the second ESL30 to form at least a portion of the crack 82. Each of the cracks 82 includes, for example, one or more voids, grain boundaries of the conductive fill material 80, and/or other indications of coalescence or merging of growth fronts. The slit 82 may have an angle 86 with respect to vertical (e.g., perpendicular to the top surface of the second ESL 30). The angle 86 may be in the range of about 25 to about 75, more specifically about 30 to about 60. The angle 86 may be affected by the proximity of the sidewall surface of the liner 52 to the conductive via 60. In some examples, the conductive fill material 80 grows from the conductive via 60 at a rate greater than the rate of growth from the dielectric surface (e.g., the sidewall of the liner 52), such as about two to about three times. Thus, in such an example, the closer the sidewall of the liner 52 is to the conductive via 60, the smaller the angle 86 may be.

In some examples, the deposition of the conductive fill material 80 includes using CVD, electroless plating or deposition, or other deposition processes. The conductive fill material 80 may be or include a metal such as ruthenium (Ru), nickel (Ni), molybdenum (Mo), cobalt (Co), tungsten (W), copper (Cu), or the like, or combinations thereof. In some examples, the conductive fill material 80 is or includes ruthenium (Ru), molybdenum (Mo), cobalt (Co), or tungsten (W) deposited by CVD. Exemplary precursors for ruthenium include triruthenium dodecacarbonyl (Ru)₃(CO)₁₂) CHORUS, etc., or combinations thereof. Exemplary precursors for molybdenum include molybdenum (V) chloride (MoCl)₅)、Mo(CO)₅Etc., or combinations thereof. Exemplary precursors for cobalt include dicarbonyl hexacarbonyl tert-butyl acetylene (CCTBA), or the like, or combinations thereof. Exemplary precursors for tungsten include tungsten hexafluoride (WF)₆) Tungsten (V) chloride (WCl)₅) Etc., or combinations thereof. The flow rate of the precursor gas during CVD may be in a range of about 10 seem to about 200 seem, and the flow rate of the carrier gas (e.g., argon (Ar)) may be in a range of about 100 seem to about 800 seem. The pressure of the CVD may be in the range of about 0.2mTorr to about 20 mTorr. The temperature of CVD may be less than or equal to about 175 ℃, such as in the range of 120 ℃ to 170 ℃ (e.g., particularly for ruthenium deposition). In other examples, electroless plating or deposition may be used to deposit nickel. Annealing or reflow may be performed after depositing the conductive fill material 80.

In some examples, silicide and/or carbide may be formed along the processing surface 70 of the dielectric material including silicon and/or carbon. For example, assuming that the liner 52 and the second ESL30 comprise silicon, the nucleation enhancement treatment may cause the silicon to have dangling bonds at the processing surface 70, and the metal of the conductive fill material 80 may attach to the dangling bonds and/or react with the silicon of the processing surface 70 to form a silicide at the interface between the conductive fill material 80 and the liner 52 or the second ESL 30. The metal of the conductive fill material 80 may attach to dangling bonds and/or react with the silicon of the processing surface 70 during deposition of the conductive fill material 80 (e.g., when a precursor flows over the processing surface 70) and/or after deposition of the conductive fill material 80. Similarly, for example, assuming that the liner 52 and the second ESL30 include carbon, the nucleation enhancement treatment may cause the carbon to have dangling bonds at the treatment surface 70, and the metal of the conductive filler material 80 may attach to the dangling bonds and/or react with the carbon of the treatment surface 70 to form carbides (e.g., metal carbides) at the interface between the conductive filler material 80 and the liner 52 or the second ESL 30. The metal of the conductive fill material 80 may attach to dangling bonds and/or react with carbon of the processing surface 70 during deposition of the conductive fill material 80 (e.g., when a precursor flows over the processing surface 70) and/or after deposition of the conductive fill material 80. With dangling and/or broken bonds of silicon and/or carbon of the processing surface 70, silicide and/or carbide may be formed at the processing surface 70 to enhance nucleation of the conductive fill material 80 and promote adhesion of the conductive fill material 80 to dielectric layers, such as the liner 52 and the second ESL 30.

In some examples, the metal of the conductive via 60 may form a metal alloy or compound with the metal of the conductive fill material 80 at the treated surface 70 of the conductive via 60. The nucleation enhancing treatment may break bonds at the treated surface 70 of the conductive via 60 to allow the metal of the conductive via 60 and the conductive filler material 80 to mix and/or react at the treated surface 70 of the conductive via 60. The metal of the conductive fill material 80 can mix and/or react with the metal of the conductive via 60 at the processing surface 70 during deposition of the conductive fill material 80 (e.g., as the precursor flows over the processing surface 70) and/or after deposition of the conductive fill material 80. The conductive vias 60 and conductive fill material 80 can be electrically connected without significant resistance caused by the substances used in the nucleation enhancing process used to form the processing surface 70.

Still further, in some examples, a substance for nucleation enhancement treatment may be embedded in or on the treatment surface 70, such as by adsorption, diffusion, and/or injection, and the substance may react with the conductive filler material 80. For example, silicon or germanium implanted in the processing surface 70 may react with the metal of the conductive fill material 80 to form a metal-semiconductor compound (e.g., a silicide or germanide, respectively). As another example, the carbon implanted in the processing surface 70 may react with the metal of the conductive filler material 80 to form a metal carbide, or the nitrogen implanted in the processing surface 70 may react with the metal of the conductive filler material 80 to form a metal nitride. In other examples, other compounds may be formed.

In some examples, the substances used for nucleation enhancement treatments may be embedded in or on the treatment surface 70 and may remain unreacted with other materials. For example, an inert species (such as argon) may remain unreacted at or near the treatment surface 70. Unreacted species may diffuse into the respective dielectric layer. Depending on the nucleation enhancing treatment, the highest concentration of unreacted species may decrease at the treatment surface 70 (e.g., of the dielectric layer or conductive via 60) and in a direction from the treatment surface 70 to the respective dielectric layer or conductive via 60, or may increase in a direction from the treatment surface 70 to the respective dielectric layer or conductive via 60 to a peak prior to decreasing in that direction, such as when the species are implanted by beam-line implantation, plasma doping, or similar techniques.

The extent to which the substance used for the nucleation enhancing treatment may be embedded in or on the different treatment surfaces 70 may depend on the directionality of the nucleation enhancing treatment. For example, highly directional nucleation enhancement processes, such as beam-line implantation, may cause some surfaces to have more species embedded therein or thereon than others. In particular, in some instances, a horizontal surface (e.g., the top surface of the second ESL 30) may have more material embedded therein or thereon than a vertical surface (e.g., the sidewall of the liner 52). In some examples, the multidirectional nucleation enhancement treatment may be implemented in different directions to achieve a more uniform treatment between different surfaces, such as a multi-beam implant at different implant angles.

Fig. 9 illustrates the removal of excess conductive fill material 80 to form conductive lines 84 in third dielectric layer 32. The excess conductive fill material 80 and the treated surface 70 of the third dielectric layer 32 may be removed using a planarization process such as CMP. The third dielectric layer 32 may be further thinned by a planarization process, and in some examples, the third dielectric layer 32 may remove rounded corners of the trench 40. In some examples, the third dielectric layer 32 is thinned to a thickness of about 10nm to about 30 nm. The removal of the excess conductive fill material 80 and the treated surface 70 of the third dielectric layer 32 may form the top surfaces of the conductive fill material 80 and the third dielectric layer 32 to be coplanar. As described above, the crack 82 may remain in the wire 84. In some examples, the cracks 82 may be cured or removed by annealing or other thermal processes used during processing. As shown in fig. 9, an interconnect structure, such as a dual damascene interconnect structure, may be formed including conductive vias 60 and conductive lines 84.

Fig. 10 illustrates the formation of a third ESL90 and a fourth dielectric layer 92 over the third dielectric layer 32, the conductive line 84, and the liner 52 along the sidewalls of the trench 40, and wherein the conductive features 94 contact the conductive line 84 through the third ESL90 and the fourth dielectric layer 92. A third ESL90 may be deposited over the third dielectric layer 32, the conductive line 84, and the liner 52. The third ESL90 may comprise or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, the like, or combinations thereof, and may be deposited by CVD, PECVD, ALD, or deposition techniques thereof. A fourth dielectric layer 92 is deposited over the third ESL 90. For example, the fourth dielectric layer 92 may be or include an IMD. The fourth dielectric layer 92 may be or include, for example, a low-k dielectric having a k value less than about 4.0, such as about 2.0 or even less. In some examples, the fourth dielectric layer 92 includes silicon oxide, PSG, BPSG, FSG, SiO_xC_yA silicon carbon material, a compound thereof, a composite thereof, or a combination thereof. CVD such as PECVD or FCVD can be used; spin coating; or other deposition technique to deposit the fourth dielectric layer 92. In some examples, CMP or another planarization process may be performed to planarize the top surface of the fourth dielectric layer 92.

The conductive member 94 of the contact wire 84 may be or include, for example, a conductive via or another conductive member. Conductive features 94 may be formed using a damascene process, such as a dual damascene process. For example, the conductive features 94 may be formed using the process illustrated above with reference to fig. 2-9 or using a similar process.

As is apparent from the foregoing, no seed layer and metal-containing barrier layer are deposited in the described examples for forming conductive via 60 and conductive line 84. In the example shown and described, no seed layer and no metal-containing barrier layer is deposited between (i) the conductive line 84 and any dielectric layer (e.g., third dielectric layer 32 or second ESL 30) on or in which the conductive line 84 is deposited, (ii) the conductive via 60 and any dielectric layer (e.g., second ESL30, second dielectric layer 28, or first ESL 26) in which the conductive via 60 is disposed; or (iii) between the conductive via 60 and the wire 84. Some embodiments may implement a seed layer and/or a metal-containing barrier layer. Furthermore, although the species of the nucleation enhancing treatment may react with the metal of the conductive line 84 (e.g., conductive fill material 80) and/or conductive via 60, such as at the treated surface 70 of the conductive via 60 (e.g., the interface between the conductive via 60 and the conductive line 84), the resulting material may be thinner and/or have a lower concentration of the species than the deposited barrier layer, and thus, in some cases, may not be a diffusion barrier layer. For example, in some examples of performing the nucleation enhancing treatment, the substance may have a concentration of less than or equal to about 5% atoms (at.%), such as in the range of about 0.1 at.% to about 5 at.%, at the respective treated surfaces in the conductive lines 84 (e.g., conductive fill material 80) and/or conductive vias 60. The concentration of the substance in the conductive line 84 (e.g., conductive fill material 80) and/or conductive via 60 may be discontinuous because of the low concentration of the substance therein. Furthermore, the substance and conductive material of the conductive line 84 and/or the conductive via 60 may not be in a stable phase of the respective material compound (e.g., metal compound).

Fig. 13-18 illustrate various details and/or modifications to portions of the cross-sectional view of the intermediate structure of fig. 6, in accordance with some embodiments. Fig. 13-18 illustrate additional details and/or modifications to the via opening 42 formed in fig. 2 and the corresponding conductive via 60 formed in the via opening 42 in fig. 5 and 6. Fig. 13-18 all show a first ESL26 over the conductive feature 24, a second dielectric layer 28 over the first ESL26, and a second ESL30 over the second dielectric layer 28. Although the via opening 42 is not specifically identified in fig. 13-18, one of ordinary skill in the art will readily understand that the sidewalls of the first ESL26, the second dielectric layer 28, and the second ESL30 (with the conductive via 60 disposed therebetween) are the sidewalls of the via opening 42 formed in fig. 2 when viewing the figures. The via opening 42 in fig. 13-18 has a first dimension D1 (e.g., depth) from the top surface of the conductive feature 24 exposed through the via opening 42 to the top surface of the second ESL 30. The first dimension D1 may correspond to a combined thickness of the first ESL26, the second dielectric layer 28, and the second ESL 30. The first dimension D1 may be in the range of about 8nm to about 40nm, more specifically, in the range of about 10nm to about 30nm, such as about 25 nm.

In fig. 13 and 14, the via opening 42 has substantially vertical sidewalls with rounded corners at upper corners (e.g., sidewalls of the first ESL26, the second dielectric layer 28, and the second ESL30 on which the liner 52 is formed). The via opening 42 has a second dimension D2 (e.g., a width) at the bottom of the via opening 42 in fig. 13 and 14 (e.g., at the top surface of the conductive feature 24) and a third dimension D3 (e.g., a width) in the plane of the top surface of the second ESL 30. In some examples, the second dimension D2 is in a range from about 8nm to about 14nm, and in some examples, the third dimension D3 is in a range from about 13nm to about 19 nm. A first aspect ratio of the first dimension D1 and the second dimension D2 may be in a range of about 0.7 to about 3.75, and a second aspect ratio of the first dimension D1 and the third dimension D3 may be in a range of about 0.53 to about 2.31.

In fig. 15 and 16, the via opening 42 has vertical sidewalls (e.g., the sidewalls of the first ESL26, the second dielectric layer 28, and the second ESL30 on which the liner 52 is formed are vertical). Thus, the cross-section of the through-hole opening 42 is rectangular. The via opening 42 has a sixth dimension D6 (e.g., width) at the bottom of the via opening 42 in fig. 15 and 16 (e.g., at the top surface of the conductive feature 24). Since the sidewalls are vertical, the dimension (e.g., width) of the via opening 42 in the plane of the top surface of the second ESL30 is equal to the sixth dimension D6. In some examples, the sixth dimension D6 is in a range from about 8nm to about 14 nm. An aspect ratio of the first dimension D1 to the sixth dimension D6 may be in a range of about 0.7 to about 3.75.

In fig. 17 and 18, the via opening 42 has non-vertical or sloped sidewalls (e.g., the sidewalls of the first ESL26, the second dielectric layer 28, and the second ESL30 on which the liner 52 is formed are non-vertical or sloped). Thus, the cross-section of the via opening 42 may have a positive tapered profile, as shown, and in other examples, the cross-section of the via opening 42 may be a reentrant profile. The via opening 42 has a ninth dimension D9 (e.g., width) at the bottom of the via opening 42 in fig. 17 and 18 (e.g., at the top surface of the conductive feature 24) and a tenth dimension D10 (e.g., width) in the plane of the top surface of the second ESL 30. In some examples, the ninth dimension D9 is in the range of about 8nm to about 14nm, and in some examples, the tenth dimension D10 is in the range of about 13nm to about 19 nm. A first aspect ratio of the first dimension D1 and the ninth dimension D9 may be in a range of about 0.7 to about 3.75, and a second aspect ratio of the first dimension D1 and the tenth dimension D10 may be in a range of about 0.53 to about 2.31.

In fig. 13, 15 and 17, the conductive via 60 has convex

upper surfaces

100, 104 and 108 (e.g., convex curved surfaces) that protrude above the top surface of the second ESL 30. The convex

upper surfaces

100, 104, and 108 may be partially circular (e.g., semi-circular), partially elliptical (e.g., semi-elliptical), or other shape in cross-section. For example, the convex

upper surfaces

100, 104, and 108 can have an uppermost point at a horizontal surface above the top surface of the second ESL30, and the bottom of the convex top surface can be at a horizontal surface above the top surface of the second ESL30, at a horizontal surface at the top surface of the second ESL30, or at a horizontal surface below the top surface of the second ESL 30. As shown, uppermost points of the convex

upper surfaces

100, 104 and 108 protrude above the top surface of the second ESL30 by a fourth dimension D4, a seventh dimension D7 and an eleventh dimension D11, respectively. The fourth, seventh, and eleventh dimensions D4, D7, and D11 may range from about 0nm to about the respective second, sixth, and ninth dimensions D2, D6, and D9. In other examples, the uppermost points of the convex

upper surfaces

100, 104, and 108 may be at a horizontal surface below the top surface of the second ESL30 or at a horizontal surface of the top surface of the second ESL 30.

In fig. 14, 16 and 18, the conductive via 60 has convex

upper surfaces

102, 106 and 110 (e.g., concave curved surfaces) that are located below the top surface of the second ESL 30. The cross-section of the concave

upper surfaces

102, 106, and 110 may be part circular (e.g., semi-circular), part elliptical (e.g., semi-elliptical), or other shape. The concave

upper surfaces

102, 106, and 110 may have a lowest point at a horizontal surface below the top surface of the second ESL 30. The upper portions of the concave

upper surfaces

102, 106, and 110 can be at a horizontal surface above the top surface of the second ESL30 or at a horizontal surface of the top surface of the second ESL 30. As shown, the lowest points of the concave

upper surfaces

102, 106, and 110 are below the top surface of the second ESL30 by a fifth dimension D5, an eighth dimension D8, and a twelfth dimension D12, respectively. The fifth dimension D5, the eighth dimension D8, and the twelfth dimension D12 may each be in the range of about 0nm to about two-thirds of the first dimension D1 (e.g., (2/3) × D1). In other examples, the top surface may have other shapes, such as being planar, and may be at any horizontal surface relative to the top surface of the second ESL30 and/or another dielectric layer.

Fig. 19-21 illustrate cross-sectional views of respective intermediate structures during an exemplary method for forming an interconnect structure according to some other embodiments. Fig. 19 and 20 illustrate an implementation of a cleaning process (operation 210 of the method 200) on the intermediate interconnect structure of fig. 4 (e.g., after operations 202-208 are completed). The cleaning process according to this embodiment is illustrated in more detail in fig. 21. In this embodiment, the cleaning process includes a plasma treatment (operation 260), a subsequent halide soak (operation 262), and a subsequent reduction treatment (operation 264).

In the illustrated embodiment, the conductive feature 24 is a multi-layer feature that includes a body 24A formed of a first material (e.g., cobalt) and a cap 24B formed of a second material (e.g., tungsten). The cleaning process cleans the cap layer 24B of the conductive feature 24. In some embodiments, such as those described above, the conductive feature 24 is a single continuous metal layer (e.g., tungsten).

Fig. 19 illustrates the implementation of plasma treatment (operation 260) and halide soaking (operation 262). The plasma treatment serves to physically clean the residue from the trench 40 and/or through the opening 42. The halide dip serves to remove native oxides that may form on the metal components (e.g., the conductive component 24) during processing.

The plasma treatment may include using hydrogen (H)₂) Argon (Ar), helium (He), neon (Ne), O₂、O₃、N₂Or NH₃The gas is mixed with a carrier gas, such as argon (Ar). A plasma sheath is generated and hydrogen is accelerated through the plasma sheath to bombard the via openings 42. In some cases, the plasma treatment may reduce residual oxides, nitrides, and/or carbides that may form on the sidewalls and/or floor of the trench 40 and/or via opening 42 during the etching process used to pattern the first ESL26, second dielectric layer 28, second ESL30, third dielectric layer 32, and/or liner layer 50. The flow rate of the hydrogen gas in the plasma process may be in a range of about 5sccm to about 1,000sccm, and the flow rate of the carrier gas in the plasma process may be in a range of about 0sccm to about 1,000 sccm. The pressure of the plasma treatment may be in the range of about 10mTorr to about 200 mTorr. The temperature of the plasma treatment may range from about-20 ℃ to about 100 ℃. The power of the plasma generator of the plasma treatment may be in the range of about 20W to about 400W, and the frequency of the plasma generator may be about 13.56MHz or greater. The substrate during plasma processing may be biased in a range of about 20V to about 200V. The plasma treatment may be performed for a shorter duration. In particular, the plasma treatment may be performed for a duration sufficient to physically clean the residue from the trenches 40 and/or through the openings 42, but may not be performed for a time sufficient to remove native oxide that may have formed on the conductive features 24. For example, in some embodiments, the duration of the plasma treatment may be in the range of about 5 seconds to about 300 seconds. Performing the plasma treatment in a short time reduces the risk of damaging the via opening 42 or the profile of the conductive feature 24 during the plasma treatment.

The halide soaking comprises rendering conductiveThe component 24 is exposed to one or more soak agents. The soaking agent is a halide of the material of the conductive member 24. In some embodiments, the soaking agent is a chloride or fluoride of the material of the conductive member 24. For example, in embodiments where the conductive feature 24 is formed of tungsten (W), the halide is tungsten hexafluoride (WF)₆). Also, in embodiments where a silicide (e.g., TiSi) is formed on the conductive member 24, the halide may be titanium tetrachloride (TiCl)₄) Titanium Tetrafluoride (TiF)₄) Or a combination thereof. In some embodiments, one or more precursors used to form the conductive feature 24 may also be used as a soaking agent. Continuing with the example where the conductive feature 24 is formed of tungsten, the same precursor (e.g., WF)₆) May be used for deposition of the conductive features 24 and soaking of the conductive features 24. The halide immersion is performed in a process chamber, which in some embodiments is the same process chamber used to deposit the material of the conductive feature 24. The pressure of the halide soak may be in the range of about 1Torr to about 10 Torr. The halide soak temperature may be in the range of about 300 ℃ to about 450 ℃. The duration of the halide soak may be in the range of about 5 seconds to about 120 seconds.

The halide dip removes native oxide that may have formed on the conductive feature 24. Specifically, the halide soak converts the solid phase native oxide to a vapor phase oxide, which is then evacuated from the via openings 42 and trenches 40. Continuing with the example where the conductive feature 24 is formed of tungsten, tungsten oxide may be formed on the exposed surface of the conductive feature 24 during processing according to the following equation:

W+1.5O₂→WO₃.(1)

tungsten oxide is converted to tungsten oxyfluoride by exposure to a halide soak in accordance with the following conditions:

2WO₃+WF₆→3WO₂F₂.(2)

the resulting tungsten oxyfluoride gas may then be evacuated from the process chamber. Evacuation may be accomplished, for example, by flowing an inert gas (e.g., Ar) through the process chamber to entrain tungsten oxyfluoride. Removing native oxide from the exposed surfaces of the conductive features 24 with a halide soak may reduce damage to the conductive features 24 during the removal of the native oxide. In addition, the halide soak may etch the conductive feature 24 without substantially etching the first ESL26, the second dielectric layer 28, the second ESL30, the third dielectric layer 32, or the liner layer 50. Thus, the halide soak may allow the exposed surface of the conductive feature 24 to be cleaned without substantially damaging the profile of the via opening 42. The process window of the cleaning process may be improved, particularly when the width of the via opening 42 is less than about 10 nm. Furthermore, avoiding damage to the profile of the via opening 42 may reduce the chance of voids forming in the via opening 42 during the formation of the conductive via 60 (see fig. 5).

Some residue 112 may remain in the via opening 42 after the halide soak. Residue 112 may be the residue of the soaking agent itself, or may be a residual byproduct of the soaking. Continuing with the example where the conductive feature 24 is formed of tungsten, the residue 112 may be WF₆W, F or WO₂F₂. The residue 112 may be along the sidewalls and/or bottom of the via opening 42.

FIG. 20 illustrates an implementation of a restore process (operation 264). The reduction process includes exposing the conductive features 24 to one or more reducing agents, such as H₂. Exposure to the reducing agent allows additional material of the conductive feature 24 (e.g., the material of the capping layer 24B) to be selectively redeposited in the via opening 42. The reducing agent reacts with the residue 112, such as with the residual halide soak, to form additional material for the conductive feature 24. The amount of residue 112 in the via opening 42 may be reduced. Continuing with the example where the conductive feature 24 is formed of tungsten, the halide soak and residue 112 may include WF₆And the additional material of the conductive member 24 may be formed according to the following equation:

WF₆+3H₂→W+6HF.(3)

the reduction treatment can be carried out at low pressure and temperature. The pressure of the reduction treatment may be in the range of about 100mTorr to about 300 mTorr. The temperature of the reduction treatment may be in the range of about 300 ℃ to about 400 ℃. The duration of the reduction treatment may be in the range of about 5 seconds to about 60 seconds.

The redeposited portions of the conductive features 24 (e.g., the capping layer 24B) extend at least partially up into the via openings 42. The redeposited portion of the conductive member 24 has a thirteenth dimension D13 from the bottom surface of the first ESL26 to the top surface of the conductive member 24. In some examples, the thirteenth dimension D13 is in a range from about 2nm to about 15nm, such as less than about 5 nm. In some embodiments, the conductive features 24 have an original height fourteenth dimension D14, which in some examples is in the range of about 10nm to about 50 nm. The thirteenth dimension D13 may be in the range of about 5% to about 40% of the fourteenth dimension D14.

After the reduction process, subsequent processing as described above may be performed to produce the interconnect structure. The details of further processing will not be repeated here. Fig. 22 shows the resulting interconnect structure after subsequent processing (e.g., after operations 216-234 are completed). The interconnect structure of fig. 22 is similar to that of fig. 10 and includes some of the soak residue 112 surrounding the conductive via 60. Further, the redeposited portions of the conductive members 24 contact portions of the sidewalls of the pads 52, and the bottom surfaces of the pads 52 are located below the bottom surfaces of the conductive vias 60. The interface of the conductive feature 24 and the conductive via 60 may be located below the top surface of the first ESL26, flush with the top surface of the first ESL26, or above the top surface of the first ESL 26. Although some residue 112 is shown at the interface of the conductive feature 24 and the conductive via 60, it should be understood that some or all of the residue 112 at the interface may be consumed by the restore process (operation 264). The sidewalls of conductive via 60 may have more residue 112 than the interface of conductive feature 24 and conductive via 60. In some embodiments, no residue 112 remains at the interface of the conductive feature 24 and the conductive via 60.

Although the resulting interconnect structure of fig. 22 is similar to that of fig. 10, it should be understood that the cleaning process shown in fig. 21 may be applied to other embodiments. For example, the resulting interconnect structure may optionally be similar to the embodiments of fig. 13-18.

Some embodiments may achieve a number of advantages. Implementing the halide soak as part of the cleaning process of the via opening 42 allows the duration of the plasma treatment to be reduced, which may reduce damage to the profile of the via opening 42 by the cleaning process. The chance of forming voids in the conductive vias 60 can be reduced. Removing native oxide from the conductive features 24 with a halide soak and redepositing additional material of the conductive features 24 through a reduction process may result in a clean (e.g., oxide-free) surface on which the conductive vias 60 may be formed, thereby reducing the resistance of the interconnect structure. As previously described, some embodiments may avoid seed layers and/or barrier layers. Without the seed layer and/or barrier layer, the resistance of the interconnect structure may be reduced, thereby reducing the resistance-capacitance (RC) delay and increasing the device speed. Furthermore, the deposition of the conductive fill material in forming the interconnect structure may be by bottom-up deposition and/or conformal deposition due to a nucleation enhancement process. Bottom-up deposition and/or conformal deposition may reduce the amount of time to fill the trench, which may increase throughput during processing and reduce cost. The exemplary embodiments may be applied to any technology node, and may be particularly applicable to improved technology nodes, such as 20nm and smaller.

In an embodiment, a method comprises: etching an interconnect opening through one or more dielectric layers over a semiconductor substrate, the interconnect opening having a via opening and a trench over the via opening, the via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a first layer of a first conductive material; treating the via opening with a plasma to physically remove etch residues from sidewalls and a bottom of the via opening; soaking the conductive part with halide of the first conductive material, wherein residual halide of the first conductive material remains in the through hole opening after soaking; reducing the residual halide of the first conductive material to form a second layer of the first conductive material on the first layer; depositing a conductive via in the via opening on the second layer of the first conductive material; and forming a conductive line on one or more exposed dielectric surfaces of the trench and in the trench over the conductive via.

In some embodiments of the method, the first conductive material is tungsten and the halide of the first conductive material is tungsten hexafluoride. In some embodiments of the method, reducing the residual halide of the first conductive material comprises exposing the residual halide to hydrogen. In some embodiments of the method, forming the conductive line includes conformally depositing a material of the conductive line in a trench on the one or more exposed dielectric surfaces. In some embodiments of the method, depositing the material of the conductive line does not include depositing a seed layer of the material for depositing the conductive line. In some embodiments of the method, no metal-containing barrier layer is deposited in the interconnect opening prior to depositing the material of the conductive line. In some embodiments, the method further comprises: a nucleation enhancement treatment is applied to one or more exposed dielectric surfaces of the trench prior to depositing the material of the conductive line. In some embodiments of the method, the nucleation enhancement treatment increases the number of nucleation sites on the surface of the dielectric layer exposed in the trench by breaking chemical bonds of the surface of the dielectric layer exposed in the trench.

In an embodiment, a method comprises: etching an interconnect opening through one or more dielectric layers over a semiconductor substrate, the interconnect opening having a via opening and a trench over the via opening, the via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a conductive material; cleaning the through hole opening; depositing a conductive via in the cleaned via opening; subjecting one or more exposed dielectric surfaces of the trench to a nucleation enhancement treatment; and forming a conductive line on one or more exposed dielectric surfaces of the trench and in the trench over the conductive via.

In some embodiments of the method, cleaning the via opening comprises: the via opening is cleaned with a halide of the conductive material. In some embodiments of the method, etching the interconnect opening forms an etch residue in the via opening and a native oxide on a surface of the conductive feature, and cleaning the via opening comprises: removing the etching residues by treating the via opening with plasma; and removing the native oxide by exposing the surface of the conductive feature to a halide of the conductive material. In some embodiments of the method, treating the via opening with plasma comprises: the via openings are bombarded with hydrogen gas for a duration of about 5 seconds to about 300 seconds. In some embodiments of the method, exposing the surface of the conductive feature comprises: the surface of the conductive member is soaked with a halide of the conductive material, and a residual halide remains in the through-hole opening after the soaking. In some embodiments, the method further comprises: additional conductive material is redeposited on the conductive feature by exposing the surface of the conductive feature to a reducing agent. In some embodiments of the method, exposing the surface of the conductive component to the reducing agent comprises: the residual halide is reduced with hydrogen, and the reduced residual halide forms additional conductive material. In some embodiments, the method further comprises: a conductive feature is deposited over a semiconductor substrate using a plurality of precursors for a conductive material, a halide of which is one of the precursors for the conductive material. In some embodiments of the method, the nucleation enhancement treatment increases the number of nucleation sites on the exposed dielectric surface of the trench by breaking chemical bonds of the exposed dielectric surface of the trench. In some embodiments of the method, forming the conductive line includes conformally depositing a material of the conductive line on the exposed dielectric surface of the trench without depositing a seed layer of the material for the conductive line.

In an embodiment, a method comprises: depositing a conductive feature over a substrate, the depositing comprising providing a plurality of precursors to a first conductive material; depositing one or more dielectric layers over the conductive features; etching an interconnect opening through the one or more dielectric layers, the interconnect opening having a via portion and a line portion located above the via portion; cleaning the sidewalls and bottom surface of the interconnect opening with a halide of the first conductive material, the halide of the first conductive material being a precursor for the first conductive material; depositing a conductive via in the via portion of the cleaned interconnect opening, the conductive via contacting the conductive feature; and depositing a wire in the line portion of the cleaned interconnect opening.

In some embodiments, the method further comprises: after cleaning the interconnect openings, a first layer of conductive material is deposited on the conductive features in the cleaned interconnect openings.

An embodiment is a method. An interconnect opening is formed through one or more dielectric layers above a semiconductor substrate. The interconnect opening has a via opening and a trench located above the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is applied to one or more exposed dielectric surfaces of the trench. Conductive lines are formed on one or more exposed dielectric surfaces of the trenches and in the trenches over the conductive vias.

Another embodiment is a structure. The structure includes a semiconductor substrate, one or more dielectric layers over the semiconductor substrate, and an interconnect structure disposed in the one or more dielectric layers. The interconnect structure includes a conductive via and a conductive line over the conductive via. The conductive lines are disposed on horizontal surfaces of the one or more dielectric layers. The same substance is disposed at a horizontal surface of the one or more dielectric layers and at a surface of the conductive via at an interface between the conductive via and the conductive fill material of the conductive line. In some embodiments, an upper surface of the conductive via at an interface between the conductive via and the conductive fill material of the wire is convex. In some embodiments, an upper surface of the conductive via at an interface between the conductive via and the conductive fill material of the wire is concave. In some embodiments, there is a crack in the conductive filler material of the wire. In some embodiments, the structure further comprises a metal semiconductor compound located at an interface between the conductive fill material of the conductive line and the surface of the one or more dielectric layers, wherein the metal of the metal semiconductor compound is the same metal as the metal of the conductive fill material. In some embodiments, the structure further comprises a metal carbide at an interface between the conductive fill material of the conductive line and the surface of the one or more dielectric layers, wherein the metal of the metal carbide is the same metal as the metal of the conductive fill material. In some embodiments, the structure further comprises a metal alloy or metal compound at an interface between the conductive fill material of the conductive line and the conductive via. In some embodiments, the dielectric surface of the one or more dielectric layers abuts the conductive line; and the respective concentrations of the species decrease in respective directions from the dielectric surface to the one or more dielectric layers. In some embodiments, the structure further comprises: a first dielectric diffusion barrier liner along sidewalls of the conductive line; and a second dielectric diffusion barrier liner along sidewalls of the conductive via. In some embodiments, no seed layer and no barrier layer are disposed between the conductive via and the conductive line.

Another embodiment is a structure comprising: a semiconductor substrate; a first dielectric layer over the semiconductor substrate; a conductive via extending through the first dielectric layer, the conductive via comprising a first conductive material; a second dielectric layer over the first dielectric layer; and a conductive line extending through the second dielectric layer, the conductive line including a second conductive material, the conductive line sharing a first interface with the conductive via, the conductive line sharing a second interface with a horizontal surface of the first dielectric layer, the conductive line sharing a third interface with a vertical surface of the second dielectric layer, the same substance being disposed at the first interface, the second interface, and the third interface, the first interface and the second interface having more substance than the third interface, the substance being different from the first conductive material and the second conductive material. In some embodiments, the species is argon. In some embodiments, the species is a combination of silicon, germanium, carbon, nitrogen, and argon. In some embodiments, the species is a combination of xenon, argon, hydrogen, and nitrogen. In some embodiments, the substance is a combination of argon, neon, and xenon. In some embodiments, the species is a combination of boron and argon.

Another embodiment is a structure comprising: a semiconductor substrate; a first conductive member located over the semiconductor substrate; one or more dielectric layers over the first conductive features; a first interconnect structure disposed in the one or more dielectric layers, the first interconnect structure including a conductive via and a conductive line, the conductive via and the conductive line contacting a horizontal surface of the one or more dielectric layers and a vertical surface of the one or more dielectric layers, the same species being disposed at the horizontal surface of the one or more dielectric layers and the vertical surface of the one or more dielectric layers; and a second conductive feature over the first interconnect structure, wherein the conductive via includes a first conductive material that extends continuously between the first conductive feature and the conductive line, and wherein the conductive line includes a second conductive material that extends continuously between the conductive via and the second conductive feature. In some embodiments, more of the substance is disposed at a horizontal surface of the one or more dielectric layers than at a vertical surface of the one or more dielectric layers. In some embodiments, the wire is free of cracks. In some embodiments, the conductive line includes a crack that forms an acute angle with respect to a vertical surface of the one or more dielectric layers, the acute angle being in a range from 30 ° to 60 °.

Another embodiment is a method. A dual damascene opening is formed through one or more dielectric layers above a semiconductor substrate. The dual damascene opening includes a trench and a via opening. A conductive via is formed in the via opening. The number of nucleation sites on the dielectric surface exposed in the trench is increased by breaking the chemical bonds of the dielectric surface exposed in the trench. The conductive fill material is deposited in the trench by adsorbing the conductive fill material onto the increased number of nucleation sites. Depositing the conductive fill material does not include using a seed layer.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming an interconnect structure, comprising:

etching an interconnect opening through one or more dielectric layers over a semiconductor substrate, the interconnect opening having a via opening and a trench over the via opening, the via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a first layer of a first conductive material;

treating the via opening with a plasma to physically remove etch residues from sidewalls and bottom of the via opening;

soaking the conductive member with a halide of the first conductive material, the residual halide of the first conductive material remaining in the via opening after soaking;

reducing the residual halide of the first conductive material to form a second layer of the first conductive material on the first layer;

depositing a conductive via in the via opening on the second layer of the first conductive material; and

forming a conductive line on one or more exposed dielectric surfaces of the trench and in the trench over the conductive via.

2. The method of claim 1, wherein the first conductive material is tungsten and the halide of the first conductive material is tungsten hexafluoride.

3. The method of claim 1, wherein reducing the residual halide of the first conductive material comprises exposing the residual halide to hydrogen.

4. The method of claim 1, wherein forming the conductive line comprises conformally depositing a material of the conductive line in the trench on the one or more exposed dielectric surfaces.

5. The method of claim 4, wherein depositing the material of the conductive lines does not include depositing a seed layer of material for depositing the conductive lines.

6. A method for forming an interconnect structure, comprising:

etching an interconnect opening through one or more dielectric layers over a semiconductor substrate, the interconnect opening having a via opening and a trench over the via opening, the via opening exposing a conductive feature over the semiconductor substrate, the conductive feature comprising a conductive material;

cleaning the through hole opening;

depositing a conductive via in the cleaned via;

subjecting one or more exposed dielectric surfaces of the trench to a nucleation enhancement treatment; and

7. A method for forming an interconnect structure, comprising:

depositing a conductive component over a substrate, the depositing comprising providing a plurality of precursors for a first conductive material;

depositing one or more dielectric layers over the conductive features;

etching an interconnect opening through the one or more dielectric layers, the interconnect opening having a via portion and a line portion above the via portion;

cleaning the sidewalls and bottom surfaces of the interconnect opening with a halide of the first conductive material, which is a precursor for the first conductive material;

depositing a conductive via in the via portion of the cleaned interconnect opening, the conductive via contacting the conductive feature; and

depositing a conductive line in the line portion of the cleaned interconnect opening.

8. An interconnect structure comprising:

a semiconductor substrate;

one or more dielectric layers over the semiconductor substrate; and

an interconnect structure disposed in the one or more dielectric layers, the interconnect structure comprising:

a conductive via; and

a conductive line over the conductive via, the conductive line disposed over a horizontal surface of the one or more dielectric layers, the same substance disposed at the horizontal surface of the one or more dielectric layers and at an upper surface of the conductive via at an interface between the conductive via and a conductive fill material of the conductive line.

9. An interconnect structure comprising:

a semiconductor substrate;

a first dielectric layer over the semiconductor substrate;

a conductive via extending through the first dielectric layer, the conductive via comprising a first conductive material;

a second dielectric layer over the first dielectric layer; and

a conductive line extending through the second dielectric layer, the conductive line including a second conductive material, the conductive line sharing a first interface with the conductive via, the conductive line sharing a second interface with a horizontal surface of the first dielectric layer, the conductive line sharing a third interface with a vertical surface of the second dielectric layer, a same substance disposed at the first interface, the second interface, and the third interface, the first interface and the second interface having more substance than the third interface, the substance being different from the first conductive material and the second conductive material.

10. An interconnect structure comprising:

a semiconductor substrate;

a first conductive feature over the semiconductor substrate;

one or more dielectric layers over the first conductive features;

a first interconnect structure disposed in the one or more dielectric layers, the first interconnect structure comprising a conductive via and a conductive line, the conductive via and the conductive line contacting horizontal surfaces of the one or more dielectric layers and vertical surfaces of the one or more dielectric layers, the same species being disposed at the horizontal surfaces of the one or more dielectric layers and the vertical surfaces of the one or more dielectric layers; and

a second conductive feature over the first interconnect structure,

wherein the conductive via comprises a first conductive material extending continuously between the first conductive component and the conductive line, an

Wherein the conductive line includes a second conductive material extending continuously between the conductive via and the second conductive component.