CN111179837B - Shift register, driving method, driving circuit and display device - Google Patents
Shift register, driving method, driving circuit and display device Download PDFInfo
- Publication number
- CN111179837B CN111179837B CN202010103882.XA CN202010103882A CN111179837B CN 111179837 B CN111179837 B CN 111179837B CN 202010103882 A CN202010103882 A CN 202010103882A CN 111179837 B CN111179837 B CN 111179837B
- Authority
- CN
- China
- Prior art keywords
- switching transistor
- mth
- electrically connected
- pull
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
Abstract
The invention discloses a shift register, a driving method, a driving circuit and a display device.A node control circuit is arranged, so that not only can signals of pull-down nodes be adjusted through the control circuit, but also signals of the pull-down nodes can be adjusted through the node control circuit, and therefore the signal change of the pull-down nodes can be accelerated, for example, the rate of pulling up the pull-down nodes can be increased. Therefore, the node noise reduction capability of the shift register can be improved, and the output stability is further improved.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a shift register, a driving method, a driving circuit, and a display device.
Background
With the rapid development of display technology, display devices are increasingly developed toward high integration and low cost. In the GOA (Gate Driver on Array) technology, a TFT (Thin Film Transistor) Gate Driver circuit is integrated on an Array substrate of a display device to form a scan Driver for the display device. However, the stability of the node signal of the shift register is poor, thereby causing a decrease in output stability.
Disclosure of Invention
The embodiment of the invention provides a shift register, a driving method, a driving circuit and a display device, which can improve output stability.
Accordingly, an embodiment of the present invention provides a shift register, including:
an input circuit configured to provide a signal of an input signal terminal to a pull-up node in response to a signal of the input signal terminal;
a reset circuit configured to provide a signal of a first reference voltage signal terminal to the pull-up node in response to a signal of a reset signal terminal;
a control circuit configured to adjust signals of the pull-up node and the pull-down node;
a node control circuit configured to adjust a signal of the pull-down node in response to a signal of the reset signal terminal;
and the output circuit is configured to enable the output signal end to output signals according to the signals of the pull-up node and the pull-down node.
Optionally, the pull-down nodes include M pull-down nodes; the control circuit comprises M sub-control circuits; wherein the mth sub-control circuit of the M sub-control circuits corresponds to the mth pull-down node of the M pull-down nodes; m is an integer and is more than or equal to 1, M is an integer and is more than or equal to 1 and less than or equal to M;
the mth sub-control circuit is configured to adjust signals of the mth pull-down node and the pull-up node;
the node control circuit is configured to adjust signals of the M pull-down nodes in response to a signal of the reset signal terminal;
the output circuit is configured to enable the output signal end to output signals according to the signals of the pull-up nodes and the signals of the M pull-down nodes.
Optionally, the node control circuit includes: m first switching transistors; wherein an mth first switch transistor of the M first switch transistors corresponds to the mth pull-down node;
the first end of the mth first switch transistor is electrically connected with the mth selection control signal end, the control end of the mth first switch transistor is electrically connected with the reset signal end, and the second end of the mth first switch transistor is electrically connected with the mth pull-down node.
Optionally, the mth sub-control circuit corresponds to the mth selection control signal terminal;
the mth sub-control circuit includes: an mth second switching transistor, an mth third switching transistor, an mth fourth switching transistor, an mth fifth switching transistor, and an mth sixth switching transistor;
a control end and a first end of the mth second switching transistor are both electrically connected to the mth selection control signal end, and a second end of the mth second switching transistor is electrically connected to a control end of the mth third switching transistor;
a first end of the mth third switching transistor is electrically connected to the mth selection control signal end, and a second end of the mth third switching transistor is electrically connected to the mth pull-down node;
a first end of the mth fourth switching transistor is electrically connected with the first reference signal end, a control end of the mth fourth switching transistor is electrically connected with the mth pull-down node, and a second end of the mth fourth switching transistor is electrically connected with the pull-up node;
a first end of the mth fifth switching transistor is electrically connected to the first reference signal end, a control end of the mth fifth switching transistor is electrically connected to the pull-up node, and a second end of the mth fifth switching transistor is electrically connected to a control end of the mth third switching transistor;
a first end of the mth sixth switching transistor is electrically connected to the first reference signal end, a control end of the mth sixth switching transistor is electrically connected to the pull-up node, and a second end of the mth sixth switching transistor is electrically connected to the mth pull-down node.
Optionally, the input circuit includes a seventh switching transistor, a first terminal and a control terminal of the seventh switching transistor are both electrically connected to the input signal terminal, and a second terminal of the seventh switching transistor is electrically connected to the pull-up node.
Optionally, the reset circuit comprises: an eighth switching transistor;
the first end of the eighth switching transistor is electrically connected with the first reference signal end, the control end of the eighth switching transistor is electrically connected with the reset signal end, and the second end of the eighth switching transistor is electrically connected with the pull-up node.
Optionally, the output circuit comprises: a ninth switching transistor, M tenth switching transistors, and a storage capacitor; wherein the content of the first and second substances,
a first end of the ninth switching transistor is electrically connected with a clock signal end, a control end of the ninth switching transistor is electrically connected with the pull-up node, and a second end of the ninth switching transistor is electrically connected with the output signal end;
a first end of an mth switch transistor of the M tenth switch transistors is electrically connected to the first reference signal end, a control end of the mth switch transistor is electrically connected to the mth pull-down node, and a second end of the mth switch transistor is electrically connected to the output signal end;
the first end of the storage capacitor is electrically connected with the pull-up node, and the second end of the storage capacitor is electrically connected with the output signal end.
Optionally, the display device further comprises an eleventh switching transistor, a first terminal of the eleventh switching transistor is electrically connected to the first reference signal terminal, a control terminal of the eleventh switching transistor is electrically connected to the frame reset signal terminal, and a second terminal of the eleventh switching transistor is electrically connected to the pull-up node.
Optionally, the display device further includes a twelfth switching transistor, a first end of the twelfth switching transistor is electrically connected to the first reference signal end, a control end of the twelfth switching transistor is electrically connected to the frame reset signal end, and a second end of the twelfth switching transistor is electrically connected to the output signal end.
Correspondingly, the embodiment of the invention also provides a driving circuit, which comprises a plurality of cascaded shift registers;
the input signal end of the first-stage shift register is electrically connected with the frame trigger signal end;
in each two adjacent stages of shift registers, the input signal end of the next stage of shift register is electrically connected with the output signal end of the previous stage of shift register;
in each adjacent two stages of shift registers, the output signal end of the next stage of shift register is electrically connected with the reset signal end of the previous stage of shift register.
Correspondingly, the embodiment of the invention also provides a display device which comprises the driving circuit.
Correspondingly, an embodiment of the present invention further provides a driving method of the shift register, including:
in the input stage, a first level signal is loaded on the input signal end, a second level signal is loaded on the reset signal end, and a second level signal is loaded on the clock signal end;
in the output stage, a second level signal is loaded on the input signal end, a second level signal is loaded on the reset signal end, and a first level signal is loaded on the clock signal end;
and in the resetting stage, a second level signal is loaded on the input signal end, a first level signal is loaded on the resetting signal end, and a second level signal is loaded on the clock signal end.
The invention has the following beneficial effects:
according to the shift register, the driving method, the driving circuit and the display device provided by the embodiment of the invention, the node control circuit is arranged, so that not only can the signal of the pull-down node be adjusted through the control circuit, but also the signal of the pull-down node can be adjusted through the node control circuit, and therefore, the signal change of the pull-down node can be accelerated, for example, the rate of pulling up the pull-down node can be increased. Therefore, the node noise reduction capability of the shift register can be improved, and the output stability is further improved.
Drawings
Fig. 1 is a schematic structural diagram of a shift register provided in the related art;
FIG. 2 is a signal timing diagram of the shift register shown in FIG. 1;
fig. 3 is a schematic structural diagram of a shift register according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of another shift register according to an embodiment of the present invention;
fig. 5a is a schematic structural diagram of a shift register according to an embodiment of the present invention;
fig. 5b is a schematic diagram of a specific structure of another shift register according to an embodiment of the present invention;
FIG. 6 is a timing diagram of a signal provided by an embodiment of the present invention;
fig. 7 is a flowchart of a driving method according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connect" or "electrically connect," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
As shown in fig. 1, the shift register generally includes: transistors M01-M011 and capacitor CST. Fig. 2 shows a timing chart of signals corresponding to the shift register shown in fig. 1. Moreover, the working process may be substantially the same as that in the related art, and is not described herein again. As can be seen from fig. 2, in the stage t02, the output terminal COUT outputs a high level signal. In the remaining stages except for the t02 stage, the output terminal COUT outputs a low level signal. In practical applications, the transistors M01-M011 cooperate with each other to make the output terminal COUT output corresponding signals.
In practical applications, the transistors may be fabricated differently in size, which results in different discharge capabilities of the transistors. In stage t03, node PU is generally discharged through transistor M02. However, node PU discharges slower due to transistor size issues. Also, the transistors M06 and M05 are typically made larger than the transistors M03 and M04, which results in the node PD pulling up slower, resulting in a shift register with a poor node noise reduction capability and thus reduced output stability.
As shown in fig. 3, a shift register provided in an embodiment of the present invention may include:
an Input circuit 10 configured to supply a signal of an Input signal terminal Input to a pull-up node N1 in response to the signal of the Input signal terminal Input;
a Reset circuit 20 configured to provide a signal of a first reference voltage signal terminal VSS to the pull-up node N1 in response to a signal of a Reset signal terminal Reset;
a control circuit 30 configured to adjust signals of a pull-up node N1 and a pull-down node P;
a node control circuit 40 configured to adjust a signal of the pull-down node P in response to a signal of the Reset signal terminal Reset;
and the Output circuit 50 is configured to enable the Output signal terminal Output to Output a signal according to the signals of the pull-up node N1 and the pull-down node P.
According to the shift register provided by the embodiment of the invention, the node control circuit is arranged, so that not only can the signal of the pull-down node be adjusted through the control circuit, but also the signal of the pull-down node can be adjusted through the node control circuit, thereby accelerating the signal change of the pull-down node, for example, the rate of pulling up the pull-down node can be increased. Therefore, the node noise reduction capability of the shift register can be improved, and the output stability is further improved.
In a specific implementation, in the embodiment of the present invention, the pull-down node P may include M pull-down nodes; the control circuit 30 may include M sub-control circuits; wherein, the mth sub-control circuit 30-M in the M sub-control circuits corresponds to the mth pull-down node Pm in the M pull-down nodes; m is an integer and is more than or equal to 1, M is an integer and is more than or equal to 1 and less than or equal to M;
the mth sub-control circuit 30-m is configured to adjust signals of the mth pull-down node Pm and the pull-up node N1;
the node control circuit 40 is configured to adjust signals of the M pull-down nodes in response to a signal of the Reset signal terminal Reset;
the Output circuit 50 is configured to make the Output signal terminal Output signal according to the signal of the pull-up node N1 and the signals of the M pull-down nodes.
Illustratively, as shown in fig. 4, M may be 2. The pull-down nodes may include the 1 st pull-down node P1 and the 2 nd pull-down node P2. The control circuit 30 may include: a 1 st sub-control circuit 30-1 corresponding to the 1 st pull-down node P1 and a 2 nd sub-control circuit 30-2 corresponding to the 2 nd pull-down node P2; wherein the 1 st sub-control circuit 30-1 is configured to adjust signals of the 1 st pull-down node P1 and the pull-up node N1. The 2 nd sub-control circuit 30-2 is configured to adjust signals of the 2 nd pull-down node P2 and the pull-up node N1. The node control circuit 40 is configured to adjust signals of the 1 st pull-down node P1 and the 2 nd pull-down node P2 in response to a signal of the Reset signal terminal Reset. The Output circuit 50 is configured to cause the Output signal terminal Output to Output a signal according to the signal of the pull-up node N1, the signal of the 1 st pull-down node P1, and the signal of the 2 nd pull-down node P2. In a specific implementation, M may be 1, and M may also be 3, 4, 5, and the like, and specific values of M may be determined according to a design of an actual application environment, and are not limited herein. The following description will be given by taking M as 2.
In specific implementation, in the embodiment of the present invention, the node control circuit 40 may include: m first switching transistors M1; wherein, the mth first switch transistor M1-M in the M first switch transistors corresponds to the mth pull-down node Pm;
the first terminal of the mth first switching transistor M1-M is electrically connected to the mth selection control signal terminal VDD-M, the control terminal of the mth first switching transistor M1-M is electrically connected to the Reset signal terminal Reset, and the second terminal of the mth first switching transistor M1-M is electrically connected to the mth pull-down node Pm.
For example, as shown in fig. 4, M may be made 2, and the node control circuit 40 may include 2 first switching transistors M1; a first terminal of a 1 st first switching transistor M1-1 among the 2 first switching transistors is electrically connected to a 1 st selection control signal terminal VDD-1, and a first terminal of a 2 nd first switching transistor M1-2 is electrically connected to a second selection control signal terminal VDD-2; the control terminals of the 1 st first switching transistor M1-1 and the 2 nd first switching transistor M1-2 are electrically connected to a Reset signal terminal Reset, the second terminal of the 1 st first switching transistor M1-1 is electrically connected to the 1 st pull-down node P1, and the second terminal of the 2 nd first switching transistor M1-2 is electrically connected to the 2 nd pull-down node P2.
In practical implementation, in the embodiment of the present invention, the mth sub-control circuit 30-m may correspond to the mth selection control signal terminal VDD-m;
the mth sub-control circuit 30-m may include: an mth second switching transistor M2-M, an mth third switching transistor M3-M, an mth fourth switching transistor M4-M, an mth fifth switching transistor M5-M, and an mth sixth switching transistor M6-M;
the control end and the first end of the mth second switching transistor M2-M are electrically connected with the mth selection control signal end VDD-M, and the second end of the mth second switching transistor M2-M is electrically connected with the control end of the mth third switching transistor M3-M;
a first terminal of the mth third switching transistor M3-M is electrically connected to the mth selection control signal terminal VDD-M, and a second terminal of the mth third switching transistor M3-M is electrically connected to the mth pull-down node Pm;
a first terminal of the mth fourth switching transistor M4-M is electrically connected to the first reference signal terminal VSS, a control terminal of the mth fourth switching transistor M4-M is electrically connected to the mth pull-down node Pm, and a second terminal of the mth fourth switching transistor M4-M is electrically connected to the pull-up node N1;
a first terminal of the mth fifth switching transistor M5-M is electrically connected to the first reference signal terminal VSS, a control terminal of the mth fifth switching transistor M5-M is electrically connected to the pull-up node N1, and a second terminal of the mth fifth switching transistor M5-M is electrically connected to the control terminal of the mth third switching transistor M3-M;
a first terminal of the mth sixth switching transistor M6-M is electrically connected to the first reference signal terminal VSS, a control terminal of the mth sixth switching transistor M6-M is electrically connected to the pull-up node N1, and a second terminal of the mth sixth switching transistor M6-M is electrically connected to the mth pull-down node Pm.
For example, as shown in fig. 5a and 5b, M may be set to 2, and the 1 st sub-control circuit 30-1 corresponds to the 1 st selection control signal terminal VDD-1, and the 2 nd sub-control circuit 30-2 corresponds to the 2 nd selection control signal terminal VDD-2;
the 1 st sub-control circuit 30-1 includes: a 1 st second switching transistor M2-1, a 1 st third switching transistor M3-1, a 1 st fourth switching transistor M4-1, a 1 st fifth switching transistor M5-1, and a 1 st sixth switching transistor M6-1; the 2 nd sub-control circuit 30-2 includes: a 2 nd second switching transistor M2-2, a 2 nd third switching transistor M3-2, a 2 nd fourth switching transistor M4-2, a 2 nd fifth switching transistor M5-2, and a 2 nd sixth switching transistor M6-2;
a control terminal and a first terminal of the 1 st second switching transistor M2-1 are electrically connected to the 1 st selection control signal terminal VDD-1, and a second terminal of the 1 st second switching transistor M2-1 is electrically connected to a control terminal of the 1 st third switching transistor M3-1; a control terminal and a first terminal of the 2 nd second switching transistor M2-2 are electrically connected to the 2 nd selection control signal terminal VDD-2, and a second terminal of the 2 nd second switching transistor M2-2 is electrically connected to a control terminal of the 2 nd third switching transistor M3-2;
a first terminal of the 1 st third switching transistor M3-1 is electrically connected to the 1 st selection control signal terminal VDD-1, and a second terminal of the 1 st third switching transistor M3-1 is electrically connected to the 1 st pull-down node P1; a first terminal of the 2 nd third switching transistor M3-2 is electrically connected to the 2 nd selection control signal terminal VDD-2, and a second terminal of the 2 nd third switching transistor M3-2 is electrically connected to the 2 nd pull-down node P2;
a first terminal of the 1 st fourth switching transistor M4-1 is electrically connected to the first reference signal terminal, a control terminal of the 1 st fourth switching transistor M4-1 is electrically connected to the 1 st pull-down node P1, and a second terminal of the 1 st fourth switching transistor M4-1 is electrically connected to the pull-up node N1; a first terminal of the 2 nd fourth switching transistor M4-2 is electrically connected to the first reference signal terminal VSS, a control terminal of the 2 nd fourth switching transistor M4-2 is electrically connected to the 2 nd pull-down node P2, and a second terminal of the 2 nd fourth switching transistor M4-2 is electrically connected to the pull-up node N1;
a first terminal of the 1 st fifth switching transistor M5-1 is electrically connected to the first reference signal terminal VSS, a control terminal of the 1 st fifth switching transistor M5-1 is electrically connected to the pull-up node N1, and a second terminal of the 1 st fifth switching transistor M5-1 is electrically connected to the control terminal of the 1 st third switching transistor M3-1; a first terminal of the 2 nd fifth switching transistor M5-2 is electrically connected to the first reference signal terminal VSS, a control terminal of the 2 nd fifth switching transistor M5-2 is electrically connected to the pull-up node N1, and a second terminal of the 2 nd fifth switching transistor M5-2 is electrically connected to the control terminal of the 2 nd third switching transistor M3-2;
a first terminal of the 1 st sixth switching transistor M6-1 is electrically connected to the first reference signal terminal VSS, a control terminal of the 1 st sixth switching transistor M6-1 is electrically connected to the pull-up node N1, and a second terminal of the 1 st sixth switching transistor M6-1 is electrically connected to the 1 st pull-down node P1; a first terminal of the 2 nd sixth switching transistor M6-2 is electrically connected to the first reference signal terminal VSS, a control terminal of the 2 nd sixth switching transistor M6-2 is electrically connected to the pull-up node N1, and a second terminal of the 2 nd sixth switching transistor M6-2 is electrically connected to the 2 nd pull-down node P2.
In practical implementation, in the embodiment of the present invention, as shown in fig. 5a and 5b, the Input circuit 10 may include a seventh switching transistor M7, a first terminal and a control terminal of the seventh switching transistor M7 are electrically connected to the Input signal terminal Input, and a second terminal of the seventh switching transistor M7 is electrically connected to the pull-up node N1.
In practical implementation, in the embodiment of the present invention, as shown in fig. 5a and 5b, the reset circuit 20 may include: an eighth switching transistor M8;
a first terminal of the eighth switching transistor M8 is electrically connected to the first reference signal terminal VSS, a control terminal of the eighth switching transistor M8 is electrically connected to the Reset signal terminal Reset, and a second terminal of the eighth switching transistor M8 is electrically connected to the pull-up node N1.
In practical implementation, in the embodiment of the present invention, as shown in fig. 5a and 5b, the output circuit 50 may include: a ninth switching transistor M9, 2 tenth switching transistors M10-1, M10-2, and a storage capacitor C; wherein the content of the first and second substances,
a first terminal of the ninth switching transistor M9 is electrically connected to the clock signal terminal CLK, a control terminal of the ninth switching transistor M9 is electrically connected to the pull-up node N1, and a second terminal of the ninth switching transistor M9 is electrically connected to the Output signal terminal Output;
first terminals of a 1 st tenth switching transistor M10-1 and a 2 nd tenth switching transistor M10-2 of the 2 nd tenth switching transistors are electrically connected to the first reference signal terminal VSS, a control terminal of the 1 st tenth switching transistor M10-1 is electrically connected to the 1 st pull-down node P1, a control terminal of the 2 nd tenth switching transistor M10-2 is electrically connected to the 2 nd pull-down node P2, and second terminals of the 1 st tenth switching transistor M10-1 and the 2 nd tenth switching transistor M10-2 are electrically connected to the Output signal terminal Output;
a first terminal of the storage capacitor C is electrically connected to the pull-up node N1, and a second terminal of the storage capacitor C is electrically connected to the Output signal terminal Output.
In practical implementation, as shown in fig. 5b, in the embodiment of the present invention, the shift register may further include an eleventh switching transistor M11, a first terminal of the eleventh switching transistor M11 is electrically connected to the first reference signal terminal VSS, a control terminal of the eleventh switching transistor M11 is electrically connected to the frame reset signal terminal STV, and a second terminal of the eleventh switching transistor M11 is electrically connected to the pull-up node N1.
In a specific implementation, as shown in fig. 5b, in the embodiment of the present invention, the shift register may further include a twelfth switching transistor M12, a first terminal of the twelfth switching transistor M12 is electrically connected to the first reference signal terminal VSS, a control terminal of the twelfth switching transistor M12 is connected to the frame reset signal terminal STV, and a second terminal of the twelfth switching transistor M12 is electrically connected to the Output signal terminal Output.
The specific structure of the shift register provided in the embodiment of the present invention is merely illustrated, and in the specific implementation, the specific structure of each circuit is not limited to the structure provided in the embodiment of the present disclosure, and may be other structures known to those skilled in the art, and is not limited herein.
Specifically, in order to make the manufacturing process uniform, in the shift register provided in the embodiment of the present invention, as shown in fig. 5a and 5b, all the switch transistors may be N-type transistors, and the signal of the first reference signal terminal VSS may be a low-level signal. Of course, all the switch transistors may be P-type transistors, and are not limited herein.
Specifically, in the shift register provided in the embodiment of the present invention, the P-type transistor is turned on by a low-level signal and turned off by a high-level signal; the N-type transistor is turned on under the action of a high-level signal and is turned off under the action of a low-level signal.
Specifically, in the shift register provided in the embodiment of the present invention, each of the switch transistors may be a Thin Film Transistor (TFT) or a Metal Oxide semiconductor field effect Transistor (MOS), which is not limited herein. In a specific implementation, the control terminal of each switching transistor may be a gate, and the first terminal of each switching transistor may be a source and the second terminal thereof may be a drain, or the first terminal of each switching transistor may be a drain and the second terminal thereof may be a source, depending on the type of each switching transistor and the input signal, which is not specifically distinguished herein.
In a specific implementation, the signal of the 1 st selection control signal terminal VDD-1 and the signal of the 2 nd selection control signal terminal VDD-2 may be pulse signals switched between a high level and a low level, respectively, and the level of the signal of the 1 st selection control signal terminal VDD-1 is opposite to the level of the signal of the 2 nd selection control signal terminal VDD-2. For example, as shown in FIG. 6, during the stage T10, the 1 st selection control signal terminal VDD-1 is a high signal, and the 2 nd selection control signal terminal VDD-2 is a low signal. In the stage T20, the 1 st selection control signal terminal VDD-1 is a low signal, and the 2 nd selection control signal terminal VDD-2 is a high signal. For example, the sustain duration of the T10 phase may be made the same as the sustain duration of the T20 phase. For example, the duration of the T10 phase and the duration of the T20 phase are set to be 1 display frame duration, multiple display frame durations, 2s, 1h, 24h, or the like, respectively, without limitation.
The sequence of the stages T10 and T20 can be determined according to practical application. For example, the work process in the stage T10 may be performed first, and then the work process in the stage T20 may be performed. Alternatively, the working process in the T20 stage may be executed first, and then the working process in the T10 stage may be executed. The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.
The following describes the operation of the shift register provided in the embodiment of the present invention with reference to the signal timing diagram shown in fig. 6 by taking the structure of the shift register shown in fig. 5a as an example, where 1 represents a high level and 0 represents a low level in the following description. It should be noted that 1 and 0 are logic levels, which are only used to better explain the specific operation of the embodiment of the present invention, and not specific voltage values.
Specifically, the T10 phase and the T20 phase in the signal timing diagram shown in fig. 6 are selected. In addition, the input stage T11, the reset stage T12, and the output stage T13 of the T10 stages are selected. And an input stage T21, a reset stage T22 and an output stage T23 in the selection T20 stages.
In the stage T10, since the 2 nd selection control signal terminal VDD-2 is a low level signal, the 2 nd second switching transistor M2-2 is turned off.
In the Input phase T11, Input is 1, CLK is 0, and Reset is 0.
Since Reset is 0, the 1 st first switching transistor M1-1 is turned off, the 2 nd first switching transistor M1-2 is turned off, and the eighth switching transistor M8 is turned off. Since Input is 1, the seventh switching transistor M7 is turned on, and a high level signal is supplied to the pull-up node N1, so that the pull-up node N1 is at a high level. The pull-up node N1 is at a high level, and the 1 st fifth switching transistor M5-1, the 2 nd fifth switching transistor M5-2, the 1 st sixth switching transistor M6-1, the 2 nd sixth switching transistor M6-2 and the ninth switching transistor M9 are all turned on.
The 1 st fifth switching transistor M5-1 is turned on, and a low level signal of the first reference signal terminal VSS is supplied to the gate of the 1 st third switching transistor M3-1, turning off the 1 st third switching transistor M3-1. The 2 nd fifth switching transistor M5-2 is turned on, and a low level signal of the first reference signal terminal VSS is supplied to the gate of the 2 nd third switching transistor M3-2, turning off the 2 nd third switching transistor M3-2.
The 1 st sixth switching transistor M6-1 is turned on, and a low level signal of the first reference signal terminal VSS is supplied to the 1 st pull-down node P1 to make the 1 st pull-down node P1 low, thereby turning off both the 1 st fourth switching transistor M4-1 and the 1 st tenth switching transistor M10-1. The 2 nd sixth switching transistor M6-2 is turned on, and a low level signal of the first reference signal terminal VSS is supplied to the 2 nd pull-down node P2 to make the 2 nd pull-down node P2 low, thereby turning off both the 2 nd fourth switching transistor M4-2 and the 2 nd tenth switching transistor M10-2.
The ninth switching transistor M9 is turned on, and provides the low level signal of the clock signal terminal CLK to the Output signal terminal Output, so that the Output signal terminal Output outputs the low level signal.
In the output phase T12, Input is 0, CLK is 1, and Reset is 0.
Since Reset is 0, the 1 st first switching transistor M1-1 is turned off, the 2 nd first switching transistor M1-2 is turned off, and the eighth switching transistor M8 is turned off. Since Input is 0, the seventh switching transistor M7 is turned off. Therefore, the pull-up node N1 is in a floating state, and the pull-up node N1 is kept at a high level due to the bootstrap effect of the storage capacitor C, so that the 1 st fifth switching transistor M5-1, the 2 nd fifth switching transistor M5-2, the 1 st sixth switching transistor M6-1, the 2 nd sixth switching transistor M6-2, and the ninth switching transistor M9 are all turned on. Thereby keeping the 1 st and 2 nd pull-down nodes P1 and P2 at a low level and turning off the 1 st, 2 nd, and tenth switching transistors M4-1, M4-2, M10-1 and M10-2, respectively.
The ninth switching transistor M9 is turned on, and provides the high level signal of the clock signal terminal CLK to the Output signal terminal Output, so that the Output signal terminal Output outputs the high level signal, and the voltage difference between the two terminals of the storage capacitor C is kept unchanged, so that the signal level of the pull-up node N1 is further increased, and the ninth switching transistor M9 is turned on more completely, so that the high level signal of the clock signal terminal CLK can be Output to the Output signal terminal Output without voltage loss as much as possible.
In the Reset phase T13, Input is 0, CLK is 0, and Reset is 1.
Since Reset is 1, the 1 st first switching transistor M1-1 is turned on, the 2 nd first switching transistor M1-2 is turned on, and the eighth switching transistor M8 is turned on. Since Input is 0, the seventh switching transistor M7 is turned off.
Since the 1 st selection control signal terminal VDD-1 is a high level signal, the 1 st second switching transistor M2-1 is turned on, and since the 2 nd selection control signal terminal VDD-2 is a low level signal, the 2 nd second switching transistor M2-2 is turned off.
The 1 st first switching transistor M1-1 is turned on, and a high level signal of the 1 st selection control signal terminal VDD-1 is supplied to the 1 st pull-down node P1 to make the 1 st pull-down node P1 high, thereby turning on the 1 st fourth switching transistor M4-1 and the 1 st tenth switching transistor M10-1. The 2 nd fourth switching transistor M4-2 is turned on to supply the low level signal of the first reference signal terminal VSS to the pull-up node N1. The 1 st tenth switching transistor M10-1 is turned on, and provides the low level signal of the first reference signal terminal VSS to the Output signal terminal Output, so that the Output signal terminal Output outputs the low level signal.
The 2 nd first switching transistor M1-2 is turned on, and a low level signal of the 2 nd selection control signal terminal VDD-2 is supplied to the 2 nd pull-down node P2 to make the 2 nd pull-down node P2 low, thereby turning off the 2 nd fourth switching transistor M4-2 and the 2 nd tenth switching transistor M10-2.
The eighth switching transistor M8 provides a low level signal of the first reference signal terminal VSS to the pull-up node N1, so that the pull-up node N1 is low, the ninth switching transistor M9 is turned off, the 1 st fifth switching transistor M5-1 is turned off, the 1 st sixth switching transistor M6-1 is turned off, the 2 nd fifth switching transistor M5-2 is turned off, and the 2 nd sixth switching transistor M6-2 is turned off.
The 1 st fifth switching transistor M5-1 is turned off, the 1 st second switching transistor M2-1 is turned on, and a high level signal of the 1 st selection control signal terminal VDD-1 is supplied to the gate of the 1 st third switching transistor M3-1 to turn on the 1 st third switching transistor M3-1. The high level signal of the 1 st selection control signal terminal VDD-1 is supplied to the 1 st pull-down node P1 via the 1 st third switching transistor M3-1.
The 2 nd fifth switching transistor M5-2 is turned off, the 2 nd second switching transistor M2-2 is turned off, the gate of the 2 nd third switching transistor M3-2 is maintained as a low level signal, and the 2 nd third switching transistor M3-2 is turned off.
In the stage T20, the 1 st second switching transistor M2-1 is turned off because the 1 st selection control signal terminal VDD-1 is a low signal.
In the Input phase T21, Input is 1, CLK is 0, and Reset is 0.
Since Reset is 0, the 1 st first switching transistor M1-1 is turned off, the 2 nd first switching transistor M1-2 is turned off, and the eighth switching transistor M8 is turned off. Since Input is 1, the seventh switching transistor M7 is turned on, and a high level signal is supplied to the pull-up node N1, so that the pull-up node N1 is at a high level. The pull-up node N1 is at a high level, and the 1 st fifth switching transistor M5-1, the 2 nd fifth switching transistor M5-2, the 1 st sixth switching transistor M6-1, the 2 nd sixth switching transistor M6-2 and the ninth switching transistor M9 are all turned on.
The 1 st fifth switching transistor M5-1 is turned on, and a low level signal of the first reference signal terminal VSS is supplied to the gate of the 1 st third switching transistor M3-1, turning off the 1 st third switching transistor M3-1. The 2 nd fifth switching transistor M5-2 is turned on, and a low level signal of the first reference signal terminal VSS is supplied to the gate of the 2 nd third switching transistor M3-2, turning off the 2 nd third switching transistor M3-2.
The 1 st sixth switching transistor M6-1 is turned on, and a low level signal of the first reference signal terminal VSS is supplied to the 1 st pull-down node P1 to make the 1 st pull-down node P1 low, thereby turning off both the 1 st fourth switching transistor M4-1 and the 1 st tenth switching transistor M10-1. The 2 nd sixth switching transistor M6-2 is turned on, and a low level signal of the first reference signal terminal VSS is supplied to the 2 nd pull-down node P2 to make the 2 nd pull-down node P2 low, thereby turning off both the 2 nd fourth switching transistor M4-2 and the 2 nd tenth switching transistor M10-2.
The ninth switching transistor M9 is turned on, and provides the low level signal of the clock signal terminal CLK to the Output signal terminal Output, so that the Output signal terminal Output outputs the low level signal.
In the output phase T22, Input is 0, CLK is 1, and Reset is 0.
Since Reset is 0, the 1 st first switching transistor M1-1 is turned off, the 2 nd first switching transistor M1-2 is turned off, and the eighth switching transistor M8 and the eleventh switching transistor M11 are turned off. Since Input is 0, the seventh switching transistor M7 is turned off. Therefore, the pull-up node N1 is in a floating state, and the pull-up node N1 is kept at a high level due to the bootstrap effect of the storage capacitor C, so that the 1 st fifth switching transistor M5-1, the 2 nd fifth switching transistor M5-2, the 1 st sixth switching transistor M6-1, the 2 nd sixth switching transistor M6-2, and the ninth switching transistor M9 are all turned on. Thereby keeping the 1 st and 2 nd pull-down nodes P1 and P2 at a low level and turning off the 1 st, 2 nd, and tenth switching transistors M4-1, M4-2, M10-1 and M10-2, respectively.
The ninth switching transistor M9 is turned on to provide the high level signal of the clock signal terminal CLK to the Output signal terminal Output, so that the Output signal terminal Output outputs the high level signal, and the voltage difference between the two terminals of the storage capacitor C is kept unchanged, so that the signal level of the pull-up node N1 is further increased.
In the Reset phase T23, Input is 0, CLK is 0, and Reset is 1.
Since Reset is 1, the 1 st first switching transistor M1-1 is turned on, the 2 nd first switching transistor M1-2 is turned on, and the eighth switching transistor M8 and the eleventh switching transistor M11 are turned on. Since Input is 0, the seventh switching transistor M7 is turned off.
Since the 1 st selection control signal terminal VDD-1 is a low level signal, the 1 st second switching transistor M2-1 is turned off, and since the 2 nd selection control signal terminal VDD-2 is a high level signal, the 2 nd second switching transistor M2-2 is turned on.
The 2 nd first switching transistor M1-2 is turned on, and a high level signal of the 2 nd selection control signal terminal VDD-2 is supplied to the 2 nd pull-down node P2 to make the 2 nd pull-down node P2 high, thereby turning on the 2 nd fourth switching transistor M4-2 and the 2 nd tenth switching transistor M10-2. The 1 st fourth switching transistor M4-1 is turned on to supply a low level signal of the first reference signal terminal VSS to the pull-up node N2. The 2 nd tenth switching transistor M10-2 is turned on, and provides the low level signal of the first reference signal terminal VSS to the Output signal terminal Output, so that the Output signal terminal Output outputs the low level signal.
The 1 st first switching transistor M1-1 is turned on, a low level signal of the 1 st selection control signal terminal VDD-1 is supplied to the 1 st pull-down node P1, and the 1 st pull-down node P1 is brought to a low level, thereby turning off the 1 st fourth switching transistor M4-1 and the 1 st tenth switching transistor M10-1.
The eighth switching transistor M8 and the eleventh switching transistor M11 are turned on, a low level signal of the first reference signal terminal VSS is supplied to the pull-up node N1, the pull-up node N1 is at a low level, the ninth switching transistor M9 is turned off, the 1 st fifth switching transistor M5-1 is turned off, the 1 st sixth switching transistor M6-1 is turned off, the 2 nd fifth switching transistor M5-2 is turned off, and the 2 nd sixth switching transistor M6-2 is turned off.
The 2 nd fifth switching transistor M5-2 is turned off, the 2 nd second switching transistor M2-2 is turned on, and a high level signal of the 2 nd selection control signal terminal VDD-2 is supplied to the gate of the 2 nd third switching transistor M3-2 to turn on the 2 nd third switching transistor M3-2. The high level signal of the 2 nd selection control signal terminal VDD-2 is supplied to the 2 nd pull-down node P2 via the 2 nd third switching transistor M3-2.
The 1 st fifth switching transistor M5-1 is turned off, the 1 st second switching transistor M2-1 is turned off, the gate of the 1 st third switching transistor M3-1 is maintained as a low level signal, and the 1 st third switching transistor M3-1 is turned off. In the Reset phase T13, by providing the 1 st first switching transistor M1-1, a high level signal of the 1 st selection control signal terminal VDD-1 can be supplied to the 1 st pull-down node P1 when the signal of the Reset signal terminal Reset changes from a low level to a high level, so that the signal of the 1 st pull-down node P1 can be changed to a high level relatively quickly. In the Reset phase T23, by providing the 2 nd first switching transistor M1-2, a high level signal of the 2 nd selection control signal terminal VDD-2 can be supplied to the 2 nd pull-down node P2 when the signal of the Reset signal terminal Reset changes from a low level to a high level, so that the signal of the 2 nd pull-down node P2 can be changed to a high level relatively quickly. The signal change of the pull-up node is accelerated through the rapid change of the signal of the pull-down node, so that the noise reduction level of the shift register is improved.
The operation of the shift register shown in fig. 5b is substantially the same as described above. The difference is that, in each frame, before the input stage T11, the method may further include: the eleventh switching transistor M11 is turned on under the control of the high level of the frame reset signal terminal STV to supply the low level signal of the first reference signal terminal VSS to the pull-up node N1 to reset the pull-up node N1. And, the twelfth switching transistor M12 is turned on under the control of the high level of the frame reset signal terminal STV to supply the low level signal of the first reference signal terminal VSS to the Output signal terminal Output to reset the Output signal terminal Output. The rest of the specific processes are not described herein.
Based on the same inventive concept, an embodiment of the present invention further provides a driving method of a shift register, as shown in fig. 7, which may include the following steps:
s10, an input stage, namely loading a first level signal to an input signal end, loading a second level signal to a reset signal end and loading a second level signal to a clock signal end;
s20, in the output stage, loading a second level signal to the input signal end, loading a second level signal to the reset signal end, and loading a first level signal to the clock signal end;
and S30, in the reset stage, loading a second level signal to the input signal end, loading a first level signal to the reset signal end, and loading a second level signal to the clock signal end.
The driving method provided by the embodiment of the invention can enable the shift register to output stable signals. In a specific implementation, in the driving method provided in the embodiment of the present invention, the first level may be a high level, and correspondingly, the second level is a low level; or conversely, the first level may be a low level, and correspondingly, the second level is a high level, which is determined according to whether the transistors in the shift register are N-type transistors or P-type transistors. Specifically, fig. 6 shows a signal timing chart in which the transistors in the shift register are N-type transistors, and the first level is a high level and the second level is a low level.
Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit, as shown in fig. 8, including a plurality of cascaded shift registers provided in the embodiment of the present invention: SR (1), SR (2) … … SR (N-1), SR (N) … … SR (N-1), SR (N) (N shift registers, N is more than or equal to 1 and less than or equal to N, and N and N are positive integers),
an Input signal end Input of the first-stage shift register SR (1) is electrically connected with a frame trigger signal end VS;
in each two adjacent stages of shift registers, an Input signal end Input of a next stage of shift register SR (n) is electrically connected with an Output signal end Output of a previous stage of shift register SR (n-1);
in each adjacent two stages of shift registers, an Output signal terminal Output of the next stage shift register SR (n) is electrically connected to a Reset signal terminal Reset of the previous stage shift register SR (n-1).
Specifically, each shift register in the gate driving circuit is identical to the shift register provided in the embodiment of the present invention in function and structure, and repeated descriptions are omitted.
In specific implementation, in the gate driving circuit provided in the embodiment of the invention, as shown in fig. 8, the clock signal terminals CLK of the odd-numbered stage shift registers are electrically connected to the same clock terminal CLK1, and the clock signal terminals CLK of the even-numbered stage shift registers are electrically connected to the same clock terminal CLK 2.
In a specific implementation, in the gate driving circuit provided in the embodiment of the invention, the first reference signal terminal VSS of each stage of the shift register is electrically connected to the same first reference terminal.
Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the driving circuit provided by the invention. The specific implementation of the shift register can be referred to the implementation process of the shift register, and the same parts are not described again.
In a specific implementation, the display device provided in the embodiment of the present invention may be an organic light emitting display device, or may also be a liquid crystal display device, which is not limited herein.
In general, an organic light emitting display device includes a plurality of organic light emitting diodes and pixel circuits connected to the organic light emitting diodes. A light emission control transistor for controlling light emission of the organic light emitting diode and a scan control transistor for controlling input of a data signal are provided in a general pixel circuit. In a specific implementation, when the display device provided in the embodiment of the present invention is an organic light emitting display device, the organic light emitting display device may include the driving circuit provided in the embodiment of the present invention, and the driving circuit may be used as a light emitting driving circuit for providing a light emitting control signal of the light emitting control transistor; alternatively, the driving circuit may be applied to supply a gate scanning signal of the scanning control transistor as a gate driving circuit. Of course, the organic light emitting display device may also include two driving control circuits provided in the embodiments of the present invention, where one of the driving circuits may be used as a light emitting driving circuit and applied to provide a light emitting control signal for the light emitting control transistor; the other driving circuit is used as a gate driving circuit for providing a gate scanning signal of the scanning control transistor, and is not limited herein.
In general, a liquid crystal display device includes a plurality of pixel electrodes and switching transistors connected to the pixel electrodes. In a specific implementation, when the display device provided by the embodiment of the present invention is a liquid crystal display device, the driving circuit provided by the embodiment of the present invention can be used as a gate driving circuit for providing a gate scanning signal of a switching transistor.
The display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.
According to the shift register, the driving method, the driving circuit and the display device provided by the embodiment of the invention, the node control circuit is arranged, so that not only can the signal of the pull-down node be adjusted through the control circuit, but also the signal of the pull-down node can be adjusted through the node control circuit, and therefore, the signal change of the pull-down node can be accelerated, for example, the rate of pulling up the pull-down node can be increased. Therefore, the node noise reduction capability of the shift register can be improved, and the output stability is further improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. A shift register, comprising:
an input circuit configured to provide a signal of an input signal terminal to a pull-up node in response to a signal of the input signal terminal;
a reset circuit configured to provide a signal of a first reference signal terminal to the pull-up node in response to a signal of a reset signal terminal;
a control circuit configured to adjust signals of the pull-up node and the pull-down node;
a node control circuit configured to adjust a signal of the pull-down node in response to a signal of the reset signal terminal;
an output circuit configured to cause an output signal terminal to output a signal according to signals of the pull-up node and the pull-down node;
the pull-down nodes comprise M pull-down nodes; the control circuit comprises M sub-control circuits; wherein the mth sub-control circuit of the M sub-control circuits corresponds to the mth pull-down node of the M pull-down nodes; m is an integer and is more than or equal to 1, M is an integer and is more than or equal to 1 and less than or equal to M;
the mth sub-control circuit is configured to adjust signals of the mth pull-down node and the pull-up node;
the node control circuit is configured to adjust signals of the M pull-down nodes in response to a signal of the reset signal terminal;
the output circuit is configured to enable an output signal end to output signals according to the signals of the pull-up nodes and the signals of the M pull-down nodes;
the mth sub-control circuit corresponds to the mth selection control signal terminal;
the mth sub-control circuit includes: an mth second switching transistor, an mth third switching transistor, an mth fourth switching transistor, an mth fifth switching transistor, and an mth sixth switching transistor;
a control end and a first end of the mth second switching transistor are both electrically connected to the mth selection control signal end, and a second end of the mth second switching transistor is electrically connected to a control end of the mth third switching transistor;
a first end of the mth third switching transistor is electrically connected to the mth selection control signal end, and a second end of the mth third switching transistor is electrically connected to the mth pull-down node;
a first end of the mth fourth switching transistor is electrically connected with the first reference signal end, a control end of the mth fourth switching transistor is electrically connected with the mth pull-down node, and a second end of the mth fourth switching transistor is electrically connected with the pull-up node;
a first end of the mth fifth switching transistor is electrically connected to the first reference signal end, a control end of the mth fifth switching transistor is electrically connected to the pull-up node, and a second end of the mth fifth switching transistor is electrically connected to a control end of the mth third switching transistor;
a first end of the mth sixth switching transistor is electrically connected to the first reference signal end, a control end of the mth sixth switching transistor is electrically connected to the pull-up node, and a second end of the mth sixth switching transistor is electrically connected to the mth pull-down node;
the size of the mth fifth switching transistor and the mth sixth switching transistor is larger than the size of the mth second switching transistor and the mth third switching transistor;
the node control circuit includes: m first switching transistors; wherein an mth first switch transistor of the M first switch transistors corresponds to the mth pull-down node;
a first end of the mth first switch transistor is electrically connected with the mth selection control signal end, a control end of the mth first switch transistor is electrically connected with the reset signal end, and a second end of the mth first switch transistor is electrically connected with the mth pull-down node;
the shift register further includes: a first end of the eleventh switching transistor is electrically connected to the first reference signal terminal, a control terminal of the eleventh switching transistor is electrically connected to the frame reset signal terminal, and a second end of the eleventh switching transistor is electrically connected to the pull-up node.
2. The shift register of claim 1, wherein the input circuit includes a seventh switching transistor, a first terminal and a control terminal of the seventh switching transistor are electrically connected to the input signal terminal, and a second terminal of the seventh switching transistor is electrically connected to the pull-up node.
3. The shift register of claim 1, wherein the reset circuit comprises: an eighth switching transistor;
the first end of the eighth switching transistor is electrically connected with the first reference signal end, the control end of the eighth switching transistor is electrically connected with the reset signal end, and the second end of the eighth switching transistor is electrically connected with the pull-up node.
4. The shift register of claim 1, wherein the output circuit comprises: a ninth switching transistor, M tenth switching transistors, and a storage capacitor; wherein the content of the first and second substances,
a first end of the ninth switching transistor is electrically connected with a clock signal end, a control end of the ninth switching transistor is electrically connected with the pull-up node, and a second end of the ninth switching transistor is electrically connected with the output signal end;
a first end of an mth switch transistor of the M tenth switch transistors is electrically connected to the first reference signal end, a control end of the mth switch transistor is electrically connected to the mth pull-down node, and a second end of the mth switch transistor is electrically connected to the output signal end;
the first end of the storage capacitor is electrically connected with the pull-up node, and the second end of the storage capacitor is electrically connected with the output signal end.
5. The shift register of claim 1, further comprising a twelfth switching transistor, a first terminal of the twelfth switching transistor being electrically connected to the first reference signal terminal, a control terminal of the twelfth switching transistor being electrically connected to a frame reset signal terminal, and a second terminal of the twelfth switching transistor being electrically connected to the output signal terminal.
6. A driving circuit comprising a plurality of shift registers according to any one of claims 1 to 5 in cascade;
the input signal end of the first-stage shift register is electrically connected with the frame trigger signal end;
in each two adjacent stages of shift registers, the input signal end of the next stage of shift register is electrically connected with the output signal end of the previous stage of shift register;
in each adjacent two stages of shift registers, the output signal end of the next stage of shift register is electrically connected with the reset signal end of the previous stage of shift register.
7. A display device comprising the driver circuit according to claim 6.
8. A driving method of a shift register according to any one of claims 1 to 5, wherein an output circuit of the shift register is electrically connected to a clock signal terminal, comprising:
in the input stage, a first level signal is loaded on the input signal end, a second level signal is loaded on the reset signal end, and a second level signal is loaded on the clock signal end;
in the output stage, a second level signal is loaded on the input signal end, a second level signal is loaded on the reset signal end, and a first level signal is loaded on the clock signal end;
and in the resetting stage, a second level signal is loaded on the input signal end, a first level signal is loaded on the resetting signal end, and a second level signal is loaded on the clock signal end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010103882.XA CN111179837B (en) | 2020-02-20 | 2020-02-20 | Shift register, driving method, driving circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010103882.XA CN111179837B (en) | 2020-02-20 | 2020-02-20 | Shift register, driving method, driving circuit and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111179837A CN111179837A (en) | 2020-05-19 |
| CN111179837B true CN111179837B (en) | 2021-08-24 |
Family
ID=70654992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010103882.XA Active CN111179837B (en) | 2020-02-20 | 2020-02-20 | Shift register, driving method, driving circuit and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111179837B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102654986A (en) * | 2011-11-25 | 2012-09-05 | 京东方科技集团股份有限公司 | Shift register electrode, grid electrode driver, array substrate and display device |
| CN202905121U (en) * | 2012-09-13 | 2013-04-24 | 北京京东方光电科技有限公司 | Shift register unit circuit, shift register, array substrate and display apparatus |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103198781B (en) * | 2013-03-01 | 2015-04-29 | 合肥京东方光电科技有限公司 | Shifting register unit and gate driving device and display device |
| CN105118414B (en) * | 2015-09-17 | 2017-07-28 | 京东方科技集团股份有限公司 | Shift register and its driving method, gate driving circuit, display device |
| CN108573668B (en) * | 2017-03-10 | 2021-05-18 | 京东方科技集团股份有限公司 | Shifting register unit and driving method thereof, grid driving circuit and display device |
| CN108564930B (en) * | 2018-05-04 | 2020-03-13 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
| KR102047973B1 (en) * | 2018-12-03 | 2019-12-02 | 성균관대학교산학협력단 | Gate Drive Circuit and Display Device including the same |
-
2020
- 2020-02-20 CN CN202010103882.XA patent/CN111179837B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102654986A (en) * | 2011-11-25 | 2012-09-05 | 京东方科技集团股份有限公司 | Shift register electrode, grid electrode driver, array substrate and display device |
| CN202905121U (en) * | 2012-09-13 | 2013-04-24 | 北京京东方光电科技有限公司 | Shift register unit circuit, shift register, array substrate and display apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111179837A (en) | 2020-05-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108154835B (en) | Shifting register unit, driving method thereof, grid driving circuit and display device | |
| US10127862B2 (en) | Shift register unit, gate drive circuit and display panel | |
| US9965986B2 (en) | Shift register unit and driving method thereof, shift register and display device | |
| WO2017124721A1 (en) | Shift register, gate drive circuit, and display device | |
| US20170178582A1 (en) | Shift register, gate driving circuit, display panel, driving method thereof and display device | |
| CN107909959B (en) | Shifting register unit, driving method thereof, grid driving circuit and display device | |
| CN108231034B (en) | Shifting register unit, grid driving circuit, display panel and display device | |
| CN110706656B (en) | Shift register, driving method thereof, driving circuit and display device | |
| CN111145678B (en) | Shift register, driving method thereof, driving circuit and display device | |
| CN111445866B (en) | Shift register, driving method, driving control circuit and display device | |
| US10403188B2 (en) | Shift register unit, gate driving circuit and display device | |
| CN107610736B (en) | Shifting register, grid driving circuit and display device | |
| CN111710281A (en) | Shifting register, driving method thereof, grid driving circuit and display device | |
| US11961582B2 (en) | Shift register unit, driving method thereof, and device | |
| CN110634528B (en) | Shift register, driving method thereof, driving control circuit and display device | |
| CN107516492B (en) | Shifting register, grid driving circuit and display device | |
| CN111223515B (en) | Shift register, driving method thereof, driving circuit and display device | |
| KR102235950B1 (en) | Shift registers, gate drive circuits and display devices | |
| CN111179837B (en) | Shift register, driving method, driving circuit and display device | |
| CN111243651B (en) | Shift register, driving method, driving circuit and display device | |
| CN111462675B (en) | Shifting register, grid driving circuit and display device | |
| CN111583885B (en) | Driving method and device of shift register | |
| CN113851173A (en) | Shift register unit, drive control circuit, display device and drive method | |
| CN109817137B (en) | Shift register circuit, driving method thereof and related device | |
| CN113971919B (en) | Shift register unit, driving method and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |