CN111178374B

CN111178374B - Damage mode determination method and device, electronic equipment and storage medium

Info

Publication number: CN111178374B
Application number: CN201811334416.1A
Authority: CN
Inventors: 陈予郎; 潘晓东
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-11-09
Filing date: 2018-11-09
Publication date: 2022-04-12
Anticipated expiration: 2038-11-09
Also published as: CN111178374A

Abstract

The disclosure relates to a method and a device for determining a damage mode, an electronic device and a storage medium, and relates to the technical field of integrated circuits, wherein the method comprises the following steps: dividing a target array in a target chip to obtain a plurality of preset graphs, wherein the target chip comprises a plurality of failure bits; classifying the preset graphs through a deep learning model, and determining the category of each preset graph; and determining a combination of potential damage modes consisting of the failure bits in a preset graph corresponding to the target type, and determining the target damage mode of the target array when the combination of the potential damage modes meets a preset condition. The method and the device can reduce the calculation amount, reduce the calculation cost, and quickly determine the target damage mode, thereby improving the chip yield.

Description

Damage mode determination method and device, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and in particular, to a failure mode determination method, a failure mode determination apparatus, an electronic device, and a computer-readable storage medium.

Background

In the product analysis of integrated circuits, it is necessary to perform cutting analysis on chips with DP (Defect Patterns) to determine whether the cause of test failure is a design cause or a process cause.

In the related art, in a chip bitmap (bit map) with a huge data volume, the damage patterns in the chip bitmap which is continuously, clustered and locally and discretely distributed can be directly and manually perceived, and the damage patterns in the chip bitmap which is randomly distributed cannot be identified. In this way, the distribution of the chip bitmaps is determined by statistical methods, which may lead to problems of low recognition and inaccurate recognition of the bad patterns. In addition, statistical methods can be used to mine all failure modes, but tens of thousands of Fail Bits (FBs) are always distributed in a chip, and any possible combination of FBs is a Potential failure mode (PDPs). When the statistical method is adopted to mine the damage mode, the calculation amount is large, the calculation cost is high, and therefore the damage mode cannot be mined and determined quickly and accurately, and the yield of chips is affected.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure is directed to a method and an apparatus for determining a failure mode, an electronic device, and a storage medium, so as to overcome at least a problem of a low chip yield caused by a failure to determine a failure mode quickly and accurately due to limitations and defects of related technologies.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

According to an aspect of the present disclosure, there is provided a damage mode determination method including: dividing a target array in a target chip to obtain a plurality of preset graphs, wherein the target chip comprises a plurality of failure bits; classifying the preset graphs through a deep learning model, and determining the category of each preset graph; and determining a combination of potential damage modes consisting of the failure bits in a preset graph corresponding to the target type, and determining the target damage mode of the target array when the combination of the potential damage modes meets a preset condition.

In an exemplary embodiment of the present disclosure, the deep learning model includes a convolutional neural network model.

In an exemplary embodiment of the present disclosure, the categories of the preset map include one or more of full defects, clustering phenomena, special errors, and randomness.

In an exemplary embodiment of the disclosure, determining a combination of potential damage patterns composed of the fail bits in a preset map corresponding to a target class, and determining the target damage pattern of the target array when the combination of the potential damage patterns satisfies a preset condition includes: determining a combination of significant damage modes according to a combination of potential damage modes consisting of the current number of fail bits in the preset graph, and taking the combination of significant damage modes as a combination of reference damage modes; and performing joint statistics on the combination of the reference damage modes and each failure bit to obtain a counted potential damage mode, and determining a target damage mode of the target array when the combination of the counted potential damage modes meets the preset condition.

In an exemplary embodiment of the present disclosure, determining a combination of significant damage patterns from a combination of potential damage patterns consisting of the current number of fail bits in the preset map includes: determining a combination of potential failure modes consisting of the current number of failed bits in each preset map; counting the number of combinations of potential damage patterns consisting of the current number of fail bits in all preset graphs, and determining the combinations with the number larger than the first preset value as the combinations of the significant damage patterns.

In an exemplary embodiment of the disclosure, jointly counting the combination of the reference failure modes and each failed bit, and determining the target failure mode of the target array when the counted combination of the potential failure modes satisfies the preset condition includes: matching the combination of the reference failure modes in each preset graph with each failure bit to obtain a combination of potential failure modes consisting of the next number of failure bits; counting the number of combinations of potential damage patterns consisting of the next number of failed bits in all preset graphs, and determining the combination of which the number is greater than a first preset value as the combination of significant damage patterns consisting of the next number of failed bits; and re-using the combination of the significant damage patterns composed of the next number of failed bits as the combination of the reference damage patterns, and matching the re-determined combination of the reference damage patterns with each failed bit until the number of the obtained combinations of the significant damage patterns meets a second preset value so as to determine the target damage pattern of the target array.

In an exemplary embodiment of the present disclosure, the method further comprises: determining a combination of all significant damage patterns as the target damage pattern of the target array.

In an exemplary embodiment of the present disclosure, the method further comprises: counting the number of combinations of each significant damage mode in the target damage mode, and judging whether the target damage mode is a non-single mode according to the number of combinations of each significant damage mode; if the target failure mode is not a single mode, determining a category for each combination of significant failure modes.

In an exemplary embodiment of the present disclosure, the category of each combination of significant failure modes includes clustering or special errors.

According to an aspect of the present disclosure, there is provided a damage mode determination apparatus including: the array dividing module is used for dividing a target array in a target chip to obtain a plurality of preset graphs, wherein the target chip comprises a plurality of failure bits; the category determination module is used for classifying the preset maps through a deep learning model and determining the category of each preset map; and the mode determining module is used for determining the combination of potential damage modes consisting of the failure bits in a preset graph corresponding to the target type and determining the target damage mode of the target array when the combination of the potential damage modes meets a preset condition.

According to an aspect of the present disclosure, there is provided an electronic device including: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform any of the above-described failure mode determination methods via execution of the executable instructions.

According to an aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a failure mode determination method as described in any one of the above.

In the damage mode determination method, the damage mode determination apparatus, the electronic device, and the computer-readable storage medium provided in the exemplary embodiment of the present disclosure, on one hand, the classification of the divided preset maps is performed by the deep learning model, and the category of the preset map including the fail bit can be accurately determined, so that the recognition degree is improved, and the problem of erroneous determination of the damage mode due to inaccurate determination of the category of the fail bit map is avoided. On the other hand, when the combination of the potential damage modes consisting of the failure bits in the preset graph corresponding to the target category meets the preset condition, the target damage modes of the target array are determined, the combinations which do not meet the preset condition are filtered out, the number of the combinations of the potential damage modes is reduced, compared with a statistical method, the calculation amount is reduced, the calculation cost is also reduced, the target damage modes can be quickly and accurately determined according to the combination of the potential damage modes, and therefore the chip yield is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

FIG. 1 schematically illustrates a failure mode determination method in an exemplary embodiment of the disclosure;

FIG. 2 schematically illustrates a schematic diagram of partitioning an array of targets in an exemplary embodiment of the disclosure;

FIG. 3 schematically illustrates a schematic diagram of determining a target damage pattern in an exemplary embodiment of the disclosure;

FIG. 4 schematically illustrates a specific flow chart for determining a failure mode of a preset map in an exemplary embodiment of the present disclosure;

FIG. 5 schematically illustrates a block diagram of a damage mode determination apparatus in an exemplary embodiment of the present disclosure;

FIG. 6 schematically illustrates a block diagram of an electronic device in an exemplary embodiment of the disclosure;

fig. 7 schematically illustrates a program product in an exemplary embodiment of the disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

In the related art, tens of thousands of fail bits are always distributed in a chip, and any possible combination of fail bits is a potential failure mode(Potential Defect Patterns, PDPs). For example, if there are N fail bits, the number of potential failure modes for all possible combinations is 2^N-1 (empty set) -N (set of single elements). Assuming that N is only a very small number of 1000, there will be about 2¹⁰⁰⁰Potential failure modes of each combination. Therefore, a combination of significant failure modes with a high frequency of occurrence is obtained from a combination of potential failure modes with a large amount of data, and a large amount of calculation is required, so that the calculation efficiency is low.

In order to solve the above problem, the exemplary embodiment first provides a failure mode determination method, which can be applied to an application scenario in which a failure bitmap in a chip is analyzed and mined. The damage mode determination method is described in detail with reference to fig. 1.

In step S110, a target array in a target chip is divided into a plurality of preset graphs, where the target chip includes a plurality of fail bits.

In the present exemplary embodiment, the target chip refers to a chip for which it is determined that a plurality of fail bits exist after the chip test. The target chip may be composed of a plurality of array arrangements, the target array refers to any one of the plurality of arrays, and each target array may be composed of 16384 cells × 32768 cells, in which the number of cell cells included is 5.3 hundred million. In the present exemplary embodiment, in order to avoid the need to determine the damage pattern from all the cells included in the target array each time, the target array may be divided into preset maps of a fixed size, and the damage pattern may be determined from the preset maps each time, so as to reduce the amount of calculation. The preset map may be represented by map, and the fixed size of the preset map may be, for example, 128 cells × 128 cells, or 256 cells × 256 cells, and the like, which is not limited herein. Thus, a target array can be divided into 128map by 128map arrays, wherein the number of default maps is 3.2 ten thousand, and each default map can include fail bits. By dividing the target array into the preset map and performing subsequent processing through the preset map, the calculation efficiency can be improved because the number of the units included in the preset map is small.

Since true failure modes can occur many times at many locations within a single array, cutting a target array into default maps allows the true failure mode location to fall between any two default maps, thereby reducing the amount of computation.

In step S120, the plurality of preset maps are classified by a deep learning model, and a category of each preset map is determined.

In this exemplary embodiment, after obtaining a plurality of preset maps corresponding to the target array, since the distribution situation of each preset map may be different, each preset map needs to be classified to determine the category of each preset map. The category herein refers to a category for describing a distribution situation of the preset map. The deep learning model may be a convolutional neural network model, where the convolutional neural network model refers to a trained convolutional neural network model, and thus the model may be trained first. Specifically, first, some preset maps may be obtained and used as input of the convolutional neural network model; next, manually determining the category of the distribution condition of the preset graph; and then, training the convolutional neural network model by adopting the manually determined type of the preset graph and the preset graph so as to continuously adjust the weight of each convolutional kernel in the convolutional neural network model, thereby obtaining the trained convolutional neural network model.

On the basis, the trained convolutional neural network model can be tested through another preset graph of which the category is determined, so that the accuracy of model classification is further ensured. It should be noted that the deep learning model may also be other suitable models, such as a classifier, etc.

The deep learning model in the present exemplary embodiment may be a three-layer convolutional neural network, and specifically may include 3 convolutional layers, where each convolutional layer may include one convolutional layer and one maximum pooling layer, the first convolutional layer may include 16 convolutional kernels of size 3 × 3, the second convolutional layer may include 32 convolutional kernels of size 3 × 3, the third convolutional layer may include 64 convolutional kernels of size 3 × 3, and so on. The pooling layers may each be 2 x 2 in size for reducing the dimensionality of the preset map features. In addition, the convolutional neural network model may further include a fully-connected layer, wherein the last fully-connected layer is related to the number of classes, the fully-connected layer may be denoted as FC-N, and when the number of classes is 4, N may be 2; when the number of classifications is 8, N may be 3, and so on.

On this basis, each preset graph may be input into the trained deep learning model, the output of the deep learning model may be the category of the preset graph, the category of the preset graph may be represented as, for example, 1 category, 2 categories, 3 categories, 4 categories, and the like, and the specific representation form is not particularly limited in this disclosure. In addition, the result output by the deep learning model may be the probability of the preset map belonging to each category, and after the probability belonging to each category is obtained, the category with the highest probability value may be used as the category of the preset map.

The categories of the preset map may specifically include one or more of full defects, clustering phenomena, special errors, and randomness. Wherein, full defect refers to a category in which the number of defects exceeds half; clustering refers to performing mode clustering by using a clustering algorithm to find out the category of common fault characteristics; the special errors refer to uniform and regular dispersion and have certain types of error occurrence reasons; randomness refers to a class that has no special features and rules, but may contain unknown patterns that are difficult to find. The category of the preset map can be uniquely represented by a numeric identifier or other identifiers, such as an all-defect identifier 1, a clustering phenomenon identifier 2, a specific error identifier 3, and a random identifier 4, and is not limited herein.

In the step, the deep learning model constructed by the three layers of convolutional neural networks is used for classifying the preset graphs according to the distribution conditions of the preset graphs, and the types of the distribution conditions of the preset graphs including the failure bits can be accurately determined, so that the identification degree is improved, and the problem that the damage mode is determined wrongly due to inaccurate distribution condition determination is solved.

Next, in step S130, a combination of potential failure modes composed of the failed bits in the preset map corresponding to the target category is determined, and a target failure mode of the target array is determined when the combination of the potential failure modes satisfies a preset condition.

In the present exemplary embodiment, the target category refers to the randomness category determined by step S120. The potentially defective mode refers to any combination of a plurality of fail bits, that is, any combination of a number of fail bits can be regarded as a potentially defective mode, and thus the potentially defective mode may include any combination of a number of fail bits, for example, 2, 3, or 4, and so on. For example, in each default map, all combinations of 2 fail bits are potential failure mode PDPs consisting of 2 fail bits, and all combinations of 4 fail bits are potential failure mode PDPs consisting of 4 fail bits. The target damage pattern refers to a combination of all the potential damage patterns corresponding to each preset map, which satisfies a preset condition, that is, only a part of the combination corresponding to the potential damage pattern. The preset condition may be, for example, a condition that limits the number of combinations in the potential damage patterns, and the calculation amount can be reduced by screening all the potential damage patterns by the preset condition.

Specifically, determining a combination of potential damage modes in a preset map corresponding to a target category, and determining a target damage mode of the target array when the combination meets a preset condition includes: step one, determining a combination of significant damage modes according to a combination of potential damage modes composed of the current number of failure bits contained in the preset graph, and taking the combination of significant damage modes as a combination of reference damage modes; and step two, performing joint statistics on the combination of the reference damage modes and each failure bit, and determining a target damage mode of the target array when the combination of the counted potential damage modes meets the preset condition.

For step one, a potential failure mode refers to a failure mode that includes a combination of the current number of failed bits. The current number refers to a combination of the smallest number of fail bits, and may be 2 in this example. Significant failure modes refer to a fixed permutation of a number of failed bits that are part of the potential failure modes, which occur frequently. The combination of significant defective patterns consisting of the current number of failed bits can be determined according to the number of combinations of potential defective patterns in the preset map, which specifically includes: determining a combination of potential failure modes consisting of the current number of failed bits in each preset map; counting the number of combinations of potential damage patterns consisting of the current number of fail bits in all preset graphs, and determining the combinations with the number larger than the first preset value as the combinations of the significant damage patterns.

Referring to diagram a in fig. 3, the combinations of 2 fail bits in each preset diagram can be first determined to determine the number of combinations of potential failure modes consisting of 2 fail bits. For example, in each Map, all combinations of 2 fail bits are calculated, and all existing combinations are considered regardless of the number of occurrences in each Map, which are potential failure modes of the 2 fail bit combinations. The number of combinations of potential failure modes may be, for example, N (N-1)/2.

Further, the combination of the potential damage patterns composed of 2 failed bits in each preset map can be determined by the same method, and the number of the combinations of the potential damage patterns composed of 2 failed bits in all the preset maps is counted to obtain the number of all the combinations of the potential damage patterns composed of 2 failed bits corresponding to the target array. And then the combination with the number larger than the first preset value can be used as the combination of the significant defective modes in the potential defective modes consisting of 2 failed bits. The first preset value may be set according to actual requirements, for example, may be set to 100 or other values, so long as the number of combinations of significant damage patterns is less than 10% of the number of combinations of potential damage patterns. Continuing with fig. 3, the 2-PDPs in all the preset graphs are summed up, and if the number of combinations of the potential failure modes is greater than the first preset value τ, the SDPs (significant failure modes) that are considered as potential failure modes consisting of 2 fail bits can be represented by 2-base SDPs or 2-SDPs. Wherein the number of combinations of 2-SDPs is less than about 10% of the number of combinations in 2-PDPs, and the number of combinations of 2-SDPs can be expressed as M2.

After the significant damage patterns are obtained, the combination of significant damage patterns can be used as a combination of reference damage patterns, and the reference damage patterns are matched and jointly counted with each failed bit to re-determine the counted potential damage patterns. Specifically, the combination of potential failure modes consisting of the next number of failed bits can be determined first from the already calculated combination of significant failure modes consisting of the current number of failed bits. Wherein the next number is the current number plus one, for example, the current number is 2, and the next number is 3. The combination of reference damage patterns refers to the combination of significant damage patterns for each calculation, e.g., after the first calculation, the combination of reference damage patterns is 2-SDPs; after the second calculation, the combination of reference failure modes is 3-SDPs, and so on. Matching and joint statistics of the reference failure pattern with each failed bit to re-determine the statistical potential failure patterns can be understood as: the combinations of 3-PDPs are determined from the combinations of 2-SDPs and each fail bit, the combinations of 4-PDPs are determined from the combinations of 3-SDPs and each fail bit, and so on. Referring to fig. 3, as shown in fig. B, a is set to 3 and B is set to a-1. In each Map, all combinations of all b-SDPs paired with each failing bit are calculated, the occurrence frequency in each Map is not considered, only all existing combinations are considered, the combinations are a-PDPs, and the number of the combinations of the a-PDPs is M_b(N-b)/2。

Further, the number of combinations of potential failure modes consisting of the next number of failed bits in all preset graphs is counted, and the combination of which number is greater than the first preset value is determined as a significant failure mode consisting of the next number of failed bits. The first preset value may be the same as the value set in the above process to ensure that the number of combinations of significant failure modes is 10% of the number of combinations of potential failure modes. Referring to fig. 3, diagram B, from among the combinations of 3-PDPs, a portion of potential damage modes having a number of combinations greater than the first preset value τ is taken as the combination of significant damage modes 3-SDPs.

Then, the significant damage pattern composed of the next number of fail bits may be re-used as a combination of reference damage patterns, and the re-determined combination of reference damage patterns may be matched with each of the fail bits until the number of the resulting combinations of significant damage patterns satisfies a second preset value, so as to obtain the target damage pattern of the preset map. That is, after the 3-SDPs are determined, the combination of 3-SDPs is re-used as the combination of reference failure patterns to match each failing bit, resulting in a potential failure pattern consisting of the next number of failing bits, i.e., the combination of 4-PDPs, and further the combination of 4-SDPs can be determined when the number of combinations of 4-PDPs reaches the first preset value, as shown in FIG. 3, Panel C. The cycle is thus repeated until the number of resulting combinations of significant damage patterns meets a second preset value, which here may be 0. Through circulation, 2-SDPs, 3-SDPs, 4-SDPs and a-SDPs can be obtained, and the obtained combination of the significant damage modes containing any number of failure bits (failure bits of 2-SDPs to a-SDPs) can be determined as the combination of the target damage modes of the target array.

In the exemplary embodiment, the specific process of determining the target damage Pattern of the target array by Big Data Pattern Mining (BDPM) algorithm may be implemented by a for loop h or other functions, which are not described in detail herein. The combination number in the a-PDPs is larger than the first preset value and is determined as a-SDPs, and the a-SDPs is used as a basis to be combined with each failure bit for statistics, so that all combinations of potential failure modes are mined, most combinations of failure bits which are not the failure modes can be filtered, the number of operation combinations is greatly reduced, and the operation cost is greatly reduced.

After obtaining a combination of target damage patterns for the target array, the method further comprises: counting the number of combinations of each significant damage mode in the target damage mode, and judging whether the target damage mode is a non-single mode according to the number of combinations of each significant damage mode; if the target failure mode is not a single mode, determining a category for each combination of significant failure modes. That is, the number of combinations of a-SDPs is counted, and if the number of combinations of a-SDPs is greater than 0, the mode is considered to be a non-single mode. The classification of each combination of significant impairment modes, i.e., the classification of each combination of a-SDPs, may be determined at this point. The class of each combination of a-SDPs can be any one of a clustering phenomenon class or a special error class. After determining the category of each combination of significant failure modes, the number of combinations of significant failure modes corresponding to the clustering phenomenon category or the special error category may be counted.

Through steps S110 to S130, the target failure mode is determined when the combination of the potential failure modes composed of the fail bits in the preset map corresponding to the target category satisfies the preset condition, combinations that do not satisfy the preset condition are filtered out, the number of combinations of the potential failure modes of the preset map is reduced, compared with a statistical method, the calculation amount is reduced, the calculation cost is also reduced, the target failure mode can be determined quickly and accurately according to the number of combinations of the potential failure modes, and thus the chip yield is improved. In addition, the target damage mode of each target array can be obtained, and then the damage mode of the chip is excavated, so that the failure reason of the chip can be analyzed conveniently, and the yield of the chip is improved.

A specific flow chart for determining a target damage pattern is shown in fig. 4, which may include the steps of:

in step S401, fail bit data in one wafer is obtained.

In step S402, data of each chip is sequentially removed from the wafer.

In step S403, it is determined whether chip data exists in the wafer. If yes, go to step S404; if not, the process is finished.

In step S404, the data of each array bank is sequentially retrieved from the chip.

In step S405, it is determined whether array data exists. If yes, go to step S406; if not, go to step S407.

In step S406, each array is divided into a plurality of preset patterns, and each preset pattern includes a fail bit.

In step S4061, the preset map is classified by the deep learning model.

In step S4062, it is determined whether the category of the preset map is random; if yes, go to step S4063; if not, go to step S4064.

In step S4063, the preset map is determined as the randomness map, and the process returns to step S404 to continue to extract data of the next array.

In step S4064, it is determined whether the category of the preset map is a clustering phenomenon; if yes, go to step S4065; if not, go to step S4066.

In step S4065, the preset map is determined as the cluster phenomenon map, and the process returns to step S404 to continue extracting data of the next array.

In step S4066, the preset map is determined as a special error map, and the process returns to step S404 to continue to fetch data of the next array.

In step S407, all significant damage patterns in each array are determined by Big Data Pattern Mining (BDPM), i.e., all a-SDPs are obtained, where a is any positive integer greater than or equal to 2.

In step S4071, the number of each of the a-SDPs is counted.

In step S4072, the number of times each of the a-SDPs is counted.

In step S4073, it is determined whether or not the mode is the non-single mode.

In step S408, if the pattern is not a single pattern, clustering is performed by a clustering algorithm.

In step S4081, the number of combinations of each clustering pattern is counted.

In step S4082, the number of times of each clustering pattern is counted.

In step S409, the number of special errors is counted. Further, go to step S402.

In step S4091, the number of special errors is counted.

In the step in fig. 4, the preset map is obtained by dividing the array, and the preset map is classified, so that the data calculation amount is reduced. The target damage mode is determined when the combination of the potential damage modes meets the preset condition, the combinations which do not meet the preset condition are filtered, the number of the combinations of the potential damage modes is reduced, compared with a statistical method, the calculation amount is reduced, the calculation cost is also reduced, the target damage mode can be determined quickly and accurately according to the number of the combinations of the potential damage modes, and therefore the chip yield is improved. In addition, whether the target damage mode belongs to a clustering phenomenon or a special error can be determined, so that the failure reason can be determined according to the type of the target damage mode, and the chip yield is improved.

The present disclosure also provides a damage mode determination apparatus. Referring to fig. 5, the damage mode determining apparatus 500 may include:

an array dividing module 501, configured to divide a target array in a target chip to obtain multiple preset graphs, where the target chip includes multiple fail bits;

a category determining module 502, configured to classify the multiple preset maps through a deep learning model, and determine a category of each preset map;

a mode determining module 503, configured to determine a combination of potential failure modes composed of the failed bits in a preset map corresponding to the target category, and determine a target failure mode of the target array when the combination of the potential failure modes satisfies a preset condition.

It should be noted that the specific details of each module in the above-mentioned damage mode determining apparatus have been described in detail in the corresponding damage mode determining method, and therefore are not described herein again.

It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.

Moreover, although the steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that the steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.

In an exemplary embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or program product. Thus, various aspects of the invention may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.

An electronic device 600 according to this embodiment of the invention is described below with reference to fig. 6. The electronic device 600 shown in fig. 6 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present invention.

As shown in fig. 6, the electronic device 600 is embodied in the form of a general purpose computing device. The components of the electronic device 600 may include, but are not limited to: the at least one processing unit 610, the at least one memory unit 620, and a bus 630 that couples the various system components including the memory unit 620 and the processing unit 610.

Wherein the storage unit stores program code that is executable by the processing unit 610 to cause the processing unit 610 to perform steps according to various exemplary embodiments of the present invention as described in the above section "exemplary methods" of the present specification. For example, the processing unit 610 may perform the steps as shown in fig. 1.

The storage unit 620 may include readable media in the form of volatile memory units, such as a random access memory unit (RAM)6201 and/or a cache memory unit 6202, and may further include a read-only memory unit (ROM) 6203.

The memory unit 620 may also include a program/utility 6204 having a set (at least one) of program modules 6205, such program modules 6205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.

Bus 630 may be one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

The display unit 640 may be a display having a display function to show a processing result obtained by the processing unit 610 performing the method in the present exemplary embodiment through the display. The display includes, but is not limited to, a liquid crystal display or other display.

The electronic device 600 may also communicate with one or more external devices 800 (e.g., keyboard, pointing device, bluetooth device, etc.), with one or more devices that enable a user to interact with the electronic device 600, and/or with any devices (e.g., router, modem, etc.) that enable the electronic device 600 to communicate with one or more other computing devices. Such communication may occur via an input/output (I/O) interface 650. Also, the electronic device 600 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network such as the Internet) via the network adapter 660. As shown, the network adapter 660 communicates with the other modules of the electronic device 600 over the bus 630. It should be appreciated that although not shown in the figures, other hardware and/or software modules may be used in conjunction with the electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.

In an exemplary embodiment of the present disclosure, there is also provided a computer-readable storage medium having stored thereon a program product capable of implementing the above-described method of the present specification. In some possible embodiments, aspects of the invention may also be implemented in the form of a program product comprising program code means for causing a terminal device to carry out the steps according to various exemplary embodiments of the invention described in the above section "exemplary methods" of the present description, when said program product is run on the terminal device.

Referring to fig. 7, a program product 700 for implementing the above method according to an embodiment of the present invention is described, which may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited in this regard and, in the present document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

A computer readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., through the internet using an internet service provider).

Furthermore, the above-described figures are merely schematic illustrations of processes involved in methods according to exemplary embodiments of the invention, and are not intended to be limiting. It will be readily understood that the processes shown in the above figures are not intended to indicate or limit the chronological order of the processes. In addition, it is also readily understood that these processes may be performed synchronously or asynchronously, e.g., in multiple modules.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A failure mode determination method, comprising:

dividing a target array in a target chip to obtain a plurality of preset graphs, wherein the target chip comprises a plurality of failure bits; the target chip is a chip which is determined to have a plurality of failure bits after being tested;

classifying the preset graphs through a deep learning model, and determining the category of each preset graph;

determining a combination of potential damage modes consisting of the failure bits in a preset graph corresponding to a target type, and determining a target damage mode of the target array when the combination of the potential damage modes meets a preset condition; the potentially defective mode refers to any combination of multiple fail bits.

2. The damage mode determination method of claim 1 wherein the deep learning model comprises a convolutional neural network model.

3. The failure mode determination method of claim 1, wherein the categories of the preset map include one or more of full defects, clustering phenomena, special errors, and randomness.

4. The method of claim 1, wherein determining a combination of potential failure modes consisting of the failed bits in a preset map corresponding to a target class, and determining the target failure mode of the target array when the combination of potential failure modes satisfies a preset condition comprises:

determining a combination of significant damage modes according to a combination of potential damage modes consisting of the current number of fail bits in the preset graph, and taking the combination of significant damage modes as a combination of reference damage modes;

and performing joint statistics on the combination of the reference damage modes and each failure bit to obtain a counted potential damage mode, and determining a target damage mode of the target array when the combination of the counted potential damage modes meets the preset condition.

5. The method of claim 4, wherein determining the combination of significant failure modes according to the combination of potential failure modes consisting of the current number of failed bits in the preset map comprises:

determining a combination of potential failure modes consisting of the current number of failed bits in each preset map;

counting the number of combinations of potential damage patterns consisting of the current number of fail bits in all preset graphs, and determining the combinations with the number larger than the first preset value as the combinations of the significant damage patterns.

6. The method of claim 4, wherein jointly counting the combinations of reference patterns and each failing bit, and determining the target pattern of the target array when the counted combinations of potential patterns satisfy the predetermined condition comprises:

matching the combination of the reference failure modes in each preset graph with each failure bit to obtain a combination of potential failure modes consisting of the next number of failure bits;

counting the number of combinations of potential damage patterns consisting of the next number of failed bits in all preset graphs, and determining the combination of which the number is greater than a first preset value as the combination of significant damage patterns consisting of the next number of failed bits;

and re-using the combination of the significant damage patterns composed of the next number of failed bits as the combination of the reference damage patterns, and matching the re-determined combination of the reference damage patterns with each failed bit until the number of the obtained combinations of the significant damage patterns meets a second preset value so as to determine the target damage pattern of the target array.

7. The failure mode determination method according to claim 5 or 6, characterized in that the method further comprises:

determining a combination of all significant damage patterns as the target damage pattern of the target array.

8. The failure mode determination method of claim 7, further comprising:

counting the number of combinations of each significant damage mode in the target damage mode, and judging whether the target damage mode is a non-single mode according to the number of combinations of each significant damage mode;

if the target failure mode is not a single mode, determining a category for each combination of significant failure modes.

9. The damage pattern determination method of claim 8 wherein the category of each combination of significant damage patterns includes clustering or special errors.

10. A damage mode determination device, comprising:

the array dividing module is used for dividing a target array in a target chip to obtain a plurality of preset graphs, wherein the target chip comprises a plurality of failure bits; the target chip is a chip which is determined to have a plurality of failure bits after being tested;

the category determination module is used for classifying the preset maps through a deep learning model and determining the category of each preset map;

the mode determining module is used for determining a combination of potential damage modes consisting of the failure bits in a preset graph corresponding to a target type and determining a target damage mode of the target array when the combination of the potential damage modes meets a preset condition; the potentially defective mode refers to any combination of multiple fail bits.

11. An electronic device, comprising:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform the failure mode determination method of any of claims 1-9 via execution of the executable instructions.

12. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the failure mode determination method according to any one of claims 1 to 9.