CN111176734A

CN111176734A - Startup control method and equipment of server and storage medium

Info

Publication number: CN111176734A
Application number: CN201911287824.0A
Authority: CN
Inventors: 孟庆振; 杨艳兴
Original assignee: Suzhou Inspur Intelligent Technology Co Ltd
Current assignee: Suzhou Inspur Intelligent Technology Co Ltd
Priority date: 2019-12-15
Filing date: 2019-12-15
Publication date: 2020-05-19

Abstract

The invention discloses a startup control method of a server, which comprises the following steps based on a CPLD: receiving a power-on enabling signal sent by the PCH; judging whether a valid starting up enabling signal is received or not; in response to not receiving the valid power-on enable signal, masking the power-on enable signal; establishing connection with a checking device outside the server; and controlling the server to start up according to the input data acquired from the verification equipment. The invention also discloses a computer device and a readable storage medium. The scheme provided by the invention realizes password verification of first power-on starting after the CMOS data is cleared based on the CPLD, and reduces the risk of the server caused by clearing the BIOS password.

Description

Startup control method and equipment of server and storage medium

Technical Field

The invention relates to the field of servers, in particular to a startup control method and equipment of a server and a storage medium.

Background

At present, the leakage of network data information is more serious, the security of the data information is more and more important, most data information is stored on a server, and the security encryption of the data of the server is the most important factor. The boot password is the first barrier for data protection, and password protection is set before the server and the personal computer log in the system. The BIOS password is a common host password protection method, the BIOS password is stored in the CMOS, the BIOS cannot be loaded and started without inputting the password after the power-on of the computer, and the BIOS password has deeper protection compared with the password of a common operating system. However, the BIOS setting can be easily cleared by removing the CMOS battery, and in the existing server motherboard design, after the CMOS data is cleared by removing the battery, when the motherboard is connected to the AC power supply again and is powered on, even if the power-on enable signal (such as the power-on key, the BMC power-on signal, the XDP power-on signal, and the like) is not input, the server motherboard will automatically power on and enter the system, and only after the motherboard runs the BIOS Setup will the CMOS register be automatically reset, so that the automatic power-on phenomenon will not occur when the AC is powered on next time. The BIOS password is not particularly secure. The existing server design has no any protection measure for the operation of removing the BIOS password by detaching the RTC battery, and the design of directly powering on and starting up the server after clearing the password also has greater potential safety hazard.

Disclosure of Invention

In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a method for controlling booting of a server, including:

receiving a power-on enabling signal sent by the PCH;

judging whether a valid starting up enabling signal is received or not;

in response to not receiving the valid power-on enable signal, masking the power-on enable signal;

establishing connection with a checking device outside the server;

and controlling the server to start up according to the input data acquired from the verification equipment.

In some embodiments, further comprising:

and controlling the server to be started up in response to the received effective starting up enabling signal.

In some embodiments, establishing a connection with a verification device external to the server further comprises:

an enable signal is sent to the switching device to establish a connection with a verification device that is conductive to the switching device.

In some embodiments, controlling the server to power on according to the input data obtained from the verification device further includes:

checking the input data according to data pre-stored in the CPLD;

and responding to the verification passing, and controlling the server to be powered on.

In some embodiments, verifying the input data according to pre-stored data in the CPLD further comprises:

and checking at least one of the input character data, the fingerprint data or the face image data according to the data prestored in the CPLD.

Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:

at least one processor; and

a memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of:

receiving a power-on enabling signal sent by the PCH;

judging whether a valid starting up enabling signal is received or not;

establishing connection with a checking device outside the server;

In some embodiments, further comprising:

checking the input data according to data pre-stored in the CPLD;

Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program that, when executed by a processor, performs the steps of the power-on control method of any one of the servers described above.

The invention has one of the following beneficial technical effects: the scheme provided by the invention realizes password verification of first power-on starting after the CMOS data is cleared based on the CPLD, and reduces the risk of the server caused by clearing the BIOS password.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

Fig. 1 is a schematic flowchart of a boot control method of a server according to an embodiment of the present invention;

fig. 2 is a schematic block diagram of a motherboard structure for implementing a method for controlling booting of a server according to an embodiment of the present invention;

FIG. 3 is a truth table of states of the S5 and SLP4 signals defined by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

According to an aspect of the present invention, an embodiment of the present invention provides a method for controlling a server to start up, as shown in fig. 1, which may include the steps of: s1, receiving a power-on enabling signal sent by the PCH; s2, judging whether a valid starting up enabling signal is received; s3, responding to the condition that the effective starting up enabling signal is not received, and shielding the power-on enabling signal; s4, establishing connection with a verification device outside the server; and S5, controlling the server to start according to the input data acquired from the verification equipment.

The scheme provided by the invention is based on CPLD monitoring and realizes the verification function of the key so as to control the power-on time sequence of the server. When the CPLD detects that no power-on enable signal (such as a power-on key, a BMC power-on signal, an XDP power-on signal, etc.) is input on the motherboard, but the SLP4 signal sent by the PCH is pulled high, it means that data in the CMOS may be cleared. In order to ensure the data security of the server, the CPLD shields the request of the SLP4 power-on enable signal under such a condition, the main power supply on the motherboard cannot be started, at this time, verification data needs to be input through the external interface, and the next server power-on request can be responded after the data verification in the CPLD passes.

In some embodiments, the method further comprises:

Specifically, as shown in fig. 2, during the power-on process, the CPLD102 first receives a power-on enable signal S5 (such as a power-on key, a BMC power-on signal, an XDP power-on signal, etc.) from the outside, and inputs the S5 'signal after S5 debounces into the PCH101, and under a normal condition that the COMS data is not cleared, the PCH101 sends an SLP4 signal to the CPLD102 after receiving the power-on enable signal S5' input from the outside, and the CPLD102 controls the power-on timing according to a normal power-on procedure after receiving the SLP4 signal. At power-up initiation, CPLD102 will detect the status of the S5 and SLP4 signals, and when there is a valid input at S5, CPLD102 will respond to the SLP4 signal from the PCH and initiate the main power-up flow. When the CMOS battery is unloaded to cause CMOS data to be cleared, and the AC power supply is turned on again, even if the valid power-on enable signal S5' is not received, the PCH101 sends a high-level valid SLP4 signal to the CPLD102, although the CPLD102 detects that the S5 is not valid input, the PCH still sends an SLP4 high-level signal, which represents a situation that data in the CMOS is cleared, and the CPLD will mask off the request of the SLP4 power-on enable signal under such a situation, and enter the key verification stage.

In some embodiments, the switching device may be a USB signal gating switch and the verification device may be a USB device.

Specifically, as shown in fig. 2, SW 103 is a USB signal gating switch for connecting an external USB interface, CPLD102 and PCH 101. By default, CPLD102 will output enable signal S4, gate path S2 of control 103, and allow external USB interface 104 to normally connect to PCH 101. When the CPLD102 detects that the CMOS data is cleared through the above steps, the S4 signal output by the CPLD102 will gate the S3 channel and disconnect the S2 channel, so that the externally-attached USB device is connected to the CPLD 102.

It should be noted that the switch device and the verification device may also be connected to the CPLD through other types of switches/interfaces.

checking the input data according to data pre-stored in the CPLD;

Specifically, as shown in fig. 2, when the paths S1-S3 are gated, a data acquisition device needs to be inserted into the USB interface 104, at this time, the CPLD102 reads data acquired by the USB device through S1-S3, and if the CPLD correctly verifies the acquired data according to the internal key, the CPLD outputs a power-on enable signal S6 to the VR power module 105, and starts a normal main power-on process. If the key verification is not passed, the main power on the mainboard cannot be started, and the server is in a state of being incapable of being started.

Specifically, the received externally acquired data may be any one or more of a password input by the user, a fingerprint of the user, or data recognized by a human face.

In some embodiments, the truth tables for the states of the S5 and SLP4 signals can be as shown in FIG. 3, where the signal S5 is defined as low to indicate that the active power-on enable signal is present, and the SLP4 is defined as high to indicate that the active power-on enable signal is present. When S5& SLP4 is 01, the CPLD starts a normal main power-on timing sequence when receiving the SLP4 signal sent by the PCH, and at this time, the USB signal gating switch gates to the PCH under the action of S4; when S5& SLP4 is equal to 11, it indicates that no power-on enable signal (such as power-on key, BMC power-on signal, XDP power-on signal, etc.) is input on the motherboard, but the SLP4 signal sent by the PCH is pulled high, which means that the data in the CMOS may be cleared. At this time, CPLD will shield SLP4 from entering the key verification process.

In some embodiments, taking the USB keyboard as an example for inputting a character password, when the CPLD detects that the CMOS data is cleared through the above steps, the S4 signal output by the CPLD gates the S3 channel, so that the externally-attached USB keyboard is communicated to the CPLD, the CPLD collects password data input from the keyboard and checks the password data, and if the check is passed, the CPLD sends a power-on enable signal S5 to the power module 105; if the key verification is not passed, the main power on the mainboard cannot be started, and the server is in a state of being incapable of being started.

The scheme provided by the invention aims at the problem that the mainboard is automatically powered on and started after CMOS data is removed from the server, and provides a method for carrying out encryption protection on the power-on process of the server after the CMOS battery is unloaded. When the CPLD detects that the data in the CMOS is possibly emptied, the CPLD shields an SLP4 power-on enabling signal sent by the PCH at the moment, a main power supply on the mainboard cannot be started, a key needs to be input through an external interface at the moment, and the next server power-on request can be responded after the data check in the CPLD passes. The method realizes the password verification of power-on startup after the CMOS data is cleared based on the CPLD, protects the risk caused by clearing the BIOS password of the server due to the CMOS data clearing, and is suitable for startup encryption of common users and encryption in the debugging and developing processes of server developers.

Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 4, an embodiment of the present invention further provides a computer apparatus 501, including:

at least one processor 520; and

the memory 510, the memory 510 stores a computer program 511 that can be executed on the processor, and the processor 520 executes the computer program to perform the steps of the boot control method of any of the servers.

Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 5, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610, when executed by a processor, perform the steps of the power-on control method of any one of the servers as above.

Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program to instruct related hardware to implement the methods. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.

In addition, the apparatuses, devices, and the like disclosed in the embodiments of the present invention may be various electronic terminal devices, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television, and the like, or may be a large terminal device, such as a server, and the like, and therefore the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of apparatus, device. The client disclosed by the embodiment of the invention can be applied to any one of the electronic terminal devices in the form of electronic hardware, computer software or a combination of the electronic hardware and the computer software.

Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.

Further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.

Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM may be available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A startup control method of a server comprises the following steps based on a CPLD:

receiving a power-on enabling signal sent by the PCH;

judging whether a valid starting up enabling signal is received or not;

establishing connection with a checking device outside the server;

2. The method of claim 1, further comprising:

3. The method of claim 1, wherein establishing a connection with a verification device external to the server, further comprises:

4. The method of claim 1, wherein controlling the server to power up based on input data obtained from the verification device, further comprising:

checking the input data according to data pre-stored in the CPLD;

5. The method of claim 4, wherein the input data is verified based on pre-stored data in the CPLD, further comprising:

6. A computer device, comprising:

at least one processor; and

receiving a power-on enabling signal sent by the PCH;

judging whether a valid starting up enabling signal is received or not;

establishing connection with a checking device outside the server;

7. The computer device of claim 6, further comprising:

8. The computer device of claim 6, wherein establishing a connection with a verification device external to the server further comprises:

9. The computer device of claim 6, wherein the server is controlled to power up based on input data obtained from the verification device, further comprising:

checking the input data according to data pre-stored in the CPLD;

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method of any one of claims 1 to 5.