CN111176040B - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
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- CN111176040B CN111176040B CN202010002047.7A CN202010002047A CN111176040B CN 111176040 B CN111176040 B CN 111176040B CN 202010002047 A CN202010002047 A CN 202010002047A CN 111176040 B CN111176040 B CN 111176040B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- Microelectronics & Electronic Packaging (AREA)
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- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides an array substrate and a display panel. The array substrate has a display area, the display area includes picture display area, through-hole encapsulation district and hole digging district, and the through-hole encapsulation district is around setting up around the hole digging district, and picture display area is around setting up around the through-hole encapsulation district, and hole digging district is used for forming the through-hole, includes: the first signal lines are arranged at intervals along the first direction, each first signal line comprises a first section of signal line which is positioned in the through hole packaging area and is arranged around a part of the hole digging area, the first section of signal line comprises a plurality of sections of first sub-signal lines which are electrically connected in sequence, wherein two adjacent sections of first sub-signal lines are arranged on different layers and are electrically connected through the through holes. Therefore, the antenna effect generated by the long lead-through of the first section of signal wire can be avoided, static electricity caused by the antenna effect is further avoided, the bad phenomena of dark spots and the like in the display panel generated by the antenna effect are further improved, the product yield is improved, and the picture display quality of the display panel is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a display panel.
Background
Along with the continuous improvement of the display screen duty ratio, the hole digging screen becomes an important scheme for improving the screen duty ratio, but the display screen around the through hole is not provided with an anti-static unit (EDS), so that signal wires around the hole are easy to generate static electricity due to external environment, and a plurality of adverse effects are caused, and the adverse effects of products are greatly reduced.
Accordingly, studies on the hole digging screen are in progress.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, an object of the present invention is to provide an array substrate in which static electricity is not easily generated on signal lines around a hole digging region.
In one aspect of the invention, an array substrate is provided. According to an embodiment of the present invention, the array substrate has a display area including a picture display area, a via packaging area, and a hole digging area, the via packaging area being disposed around the hole digging area, the picture display area being disposed around the hole digging area, and the hole digging area being used for forming a via, including: the first signal lines are arranged at intervals along a first direction, each first signal line comprises a first section of signal line which is positioned in the through hole packaging area and surrounds a part of the hole digging area, the first section of signal line comprises a plurality of sections of first sub-signal lines which are electrically connected in sequence, wherein two adjacent sections of first sub-signal lines are arranged on different layers and are electrically connected through holes. Because the adjacent two sections of the first sub-signal lines are arranged in different layers, the antenna effect generated by the long lead-away of the first section of the signal line can be avoided, static electricity caused by the antenna effect is further avoided, and adverse phenomena such as dark spots in the display panel generated by the antenna effect are further improved, so that the yield of products such as an array substrate and the display panel is improved, and the picture display quality of the display panel is improved.
According to an embodiment of the present invention, in the first direction, the outer peripheral line of the hole-bored area includes a left segment portion and a right segment portion, a straight line A-A extends in the second direction and intersects the hole-bored area, the first segment of the first signal lines located on the left side of the straight line A-A is disposed around the left segment portion, and the first segment of the first signal lines located on the right side of the straight line A-A is disposed around the right segment portion.
According to an embodiment of the present invention, the first sub-signal line located at the left side of the straight line A-A and disposed adjacent to the straight line A-A is disposed at a different layer from the first sub-signal line located at the right side of the straight line A-A and disposed adjacent to the straight line A-A, and is not electrically connected.
According to an embodiment of the present invention, the array substrate further includes: the second signal lines are arranged at intervals along the second direction, each second signal line comprises a second section of signal line which is positioned in the through hole packaging area and surrounds a part of the hole digging area, the second section of signal line comprises a plurality of sections of second sub-signal lines which are electrically connected in sequence, wherein two adjacent sections of second sub-signal lines are arranged in different layers and are electrically connected through the through holes.
According to an embodiment of the present invention, in the second direction, the outer peripheral line of the hole-bored area includes an upper section and a lower section, a straight line B-B extends in the first direction and intersects the hole-bored area, the second section of the second signal line located on the upper side of the straight line B-B is disposed around the upper section, and the second section of the second signal line located on the lower side of the straight line B-B is disposed around the lower section.
According to an embodiment of the present invention, the second sub-signal line located at the lower side of the straight line B-B and disposed adjacent to the straight line B-B is disposed at a different layer from the second sub-signal line located at the upper side of the straight line B-B and disposed adjacent to the straight line B-B, and is not electrically connected.
According to an embodiment of the present invention, each of the first sub-signal lines in the first segment signal line is formed by a one-time patterning process with any one of a source drain electrode, a first gate electrode, and a second gate electrode in a thin film transistor in the picture display region, and each of the second sub-signal lines in the second segment signal line is formed by a one-time patterning process with any one of the source drain electrode, the first gate electrode, and the second gate electrode.
According to an embodiment of the present invention, the array substrate further includes: the shielding wires are arranged around the hole digging area, the orthographic projection of the shielding wires on the substrate in the array substrate is positioned between the orthographic projection of the hole digging area on the substrate and the orthographic projection of the first section of signal wires and the second section of signal wires on the substrate, and the shielding wires are electrically connected with a constant potential.
According to an embodiment of the present invention, the shielding line and at least one of a source drain electrode, a first gate electrode and a second gate electrode in the thin film transistor in the picture display region are formed through a one-time patterning process.
In another aspect of the present invention, a display panel is provided. According to an embodiment of the present invention, the display panel includes the array substrate described above. Therefore, static electricity is not easy to generate in the display panel area around the through hole, and the comprehensive yield of the display panel is greatly improved. Those skilled in the art will appreciate that the display panel has all the features and advantages of the array substrate described above, and will not be described in detail herein.
Drawings
Fig. 1 is a top view of a display area of an array substrate according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of an array substrate according to another embodiment of the invention.
FIG. 3 is a cross-sectional view taken along line I-I' of FIG. 2.
Fig. 4 is a schematic structural diagram of an array substrate according to another embodiment of the present invention.
Fig. 5 is a cross-sectional view taken along N-N' in fig. 4.
Fig. 6 is a schematic structural diagram of an array substrate according to another embodiment of the present invention.
Fig. 7 is a schematic structural diagram of an array substrate according to another embodiment of the present invention.
Fig. 8 is a schematic structural diagram of an array substrate according to another embodiment of the present invention.
Fig. 9 is a schematic structural view of an array substrate according to another embodiment of the present invention.
Fig. 10 is a schematic structural view of an array substrate according to another embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below. The following examples are illustrative only and are not to be construed as limiting the invention. The examples are not to be construed as limiting the specific techniques or conditions described in the literature in this field or as per the specifications of the product.
In one aspect of the invention, an array substrate is provided. Referring to fig. 1 and 2 (wherein fig. 2 shows only a schematic top view of the hole-digging region and the signal line in the via-hole-sealing region in fig. 1, and the insulating layer between the layer structures is not shown in the drawings, etc.), the array substrate has a display region 100, the display region 100 including a picture display region 103, a via-hole-sealing region 102, and a hole-digging region 101, the via-hole-sealing region 102 being disposed around the hole-digging region 101, the picture display region 103 being disposed around the hole-sealing region 102, and the hole-digging region 101 being for forming a via hole, the array substrate comprising: a plurality of first signal lines 10 disposed at intervals along the first direction X, each first signal line 10 including a first segment of signal lines 11 disposed around a portion of the hole-digging region 101 and located in the through-hole-sealing region 102, the first segment of signal lines 11 including a plurality of segments of first sub-signal lines 111 (two segments of first sub-signal lines 111 are taken as an example in fig. 2) electrically connected in sequence, wherein adjacent first sub-signal lines 111 are disposed in different layers and electrically connected through vias (refer to fig. 3, fig. 3 is a cross-sectional view along I-I' in fig. 2). Because the adjacent two sections of the first sub-signal lines are arranged in different layers, the antenna effect generated by the long lead-away of the first section of the signal line can be avoided, static electricity caused by the antenna effect is further avoided, and adverse phenomena such as dark spots and the like generated by the antenna effect are further improved, so that the yield of products such as an array substrate and a display panel is improved, and the picture display quality of the display panel is improved.
Referring to fig. 3, two sections of first sub-signal lines in fig. 2, wherein a section of first sub-signal line 111 is disposed on a surface of a substrate 200, an insulating layer 210 is formed on a side of the first sub-signal line 111 away from the substrate, and the insulating layer 210 covers the surface of the substrate 200 not covered by the first sub-signal line 111 and the surface of the first sub-signal line 111; another section is disposed on a surface of the insulating layer 210 remote from the substrate 200, and the two sections of the first sub-signal lines are electrically connected through vias penetrating through the insulating layer 210. The insulating layer 210 may have a single-layer or multi-layer structure, and those skilled in the art may flexibly select the insulating layer according to the actual situation such as the number of insulating layers between the two first sub-signal lines.
As will be appreciated by those skilled in the art, the first signal line further includes a portion of the first signal line in the display area, and the portion of the first signal line is electrically connected to the first segment of the signal line; in addition, after the entire display panel is subsequently completed, the hole-digging region is cut along the edge of the hole-digging region 101 by a laser cutting method or the like to form a through hole, wherein in the embodiment of the present invention, the specific shape of the hole-digging region is not particularly limited, and includes, for example, but not limited to, a circular shape, an oval shape, a square shape, or other special-shaped holes.
According to an embodiment of the present invention, referring to fig. 2, in the first direction X, the outer peripheral line of the cutout area 101 includes a left segment 1011 and a right segment 1012, the straight line A-A extends in the second direction Y and intersects the cutout area 101, the first segment signal line 11 in the first signal line 10 located on the left side of the straight line A-A is disposed around the left segment 1011, and the first segment signal line 11 in the first signal line 10 located on the right side of the straight line A-A is disposed around the right segment 1012. Therefore, the plurality of first signal lines 11 arranged at intervals in the first direction X are distributed on two sides of the straight line A-A, so that the space can be fully utilized, and the plurality of first signal lines 11 are arranged in a more reasonable layout, so that the plurality of first signal lines 11 are prevented from being distributed on one side, and space congestion is avoided.
According to the embodiment of the invention, the straight line A-A passes through the middle point of the hole digging area 101, so that the plurality of first section signal wires 11 can be evenly distributed on the left side and the right side of the hole digging area 101, and further, the space can be more fully and reasonably utilized, and the plurality of first section signal wires 11 are distributed.
The first direction X and the second direction Y are disposed to intersect each other.
According to an embodiment of the present invention, referring to fig. 2, a first sub-signal line 111a located at the left side of a straight line A-A and disposed adjacent to the straight line A-A is disposed at a different layer from a first sub-signal line 111b located at the right side of the straight line A-A and disposed adjacent to the straight line A-A, and is not electrically connected. Thus, the antenna effect can be further avoided.
According to an embodiment of the present invention, referring to fig. 4, the array substrate further includes: the second signal lines 20 are disposed at intervals along the second direction Y, each second signal line 20 includes a second segment signal line 21 disposed in the through hole packaging region 102 and surrounding a portion of the hole digging region 101, and the second segment signal line 21 includes a plurality of segments of second sub-signal lines 211 (in the drawing, two segments of second sub-signal lines 211 are taken as an example) electrically connected in sequence, wherein two adjacent segments of second sub-signal lines 211 are disposed in different layers (refer to fig. 5, fig. 5 is a cross-sectional view along N-N' in fig. 4) and are electrically connected through the through hole. Because the two adjacent sections of second sub-signal lines are arranged in different layers, the antenna effect generated by long lead-away of the second section of signal lines can be avoided, and static electricity caused by the antenna effect is avoided, so that the product yield of the array substrate is improved, and the picture display quality of the display panel is improved.
As will be appreciated by those skilled in the art, the second signal line further includes a portion of the second signal line located in the picture display region, and the portion of the second signal line is electrically connected to the second segment of the signal line.
According to an embodiment of the present invention, referring to fig. 4, in the second direction Y, the outer peripheral line of the cutout region 101 includes an upper stage 1013 and a lower stage 1014, a straight line B-B extends in the first direction X and intersects the cutout region 101, a second stage signal line 21 of the second signal lines 20 located on the upper side of the straight line B-B is disposed around the upper stage 1013, and a second stage signal line 21 of the second signal lines 20 located on the lower side of the straight line B-B is disposed around the lower stage 1014. Therefore, the plurality of second-section signal lines 21 arranged at intervals in the second direction Y are distributed on two sides of the straight line B-B, so that the space can be fully utilized, and the plurality of second-section signal lines 21 are arranged in a more reasonable layout, so that the plurality of second-section signal lines 21 are prevented from being distributed on one side, and space congestion is avoided.
According to an embodiment of the present invention, referring to fig. 4, the second sub-signal line 211a located at the lower side of the straight line B-B and disposed adjacent to the straight line B-B is disposed at a different layer from the second sub-signal line 211B located at the upper side of the straight line B-B and disposed adjacent to the straight line B-B, and is not electrically connected. Thus, the antenna effect can be further avoided.
According to the embodiment of the invention, one of the first signal line and the second signal line is a data line, and the other is a scanning line, so that the antenna effect generated by the signal line and the data line around the hole digging area can be avoided.
According to the embodiment of the invention, each of the first sub-signal lines in the first segment signal line and any one of the source and drain electrodes, the first gate electrode and the second gate electrode in the thin film transistor in the picture display region are formed by a one-time patterning process, and each of the second sub-signal lines in the second segment signal line and any one of the source and drain electrodes, the first gate electrode and the second gate electrode are formed by a one-time patterning process. Therefore, the structure is formed with the existing structure in the array substrate by one-step process, and further the process flow for manufacturing the array substrate can be saved.
The following takes an example that the first section signal line and the second section signal line each include two sections of sub-signal lines, and referring to fig. 6, specific arrangement structures of the first section signal line and the second section signal line in some embodiments will be described in detail:
in some embodiments, the first sub-signal line 111b located in the upper right direction and the lower left direction of the first segment signal line 11 is disposed on 370 layers with the source and drain electrodes (i.e. prepared by using the same patterning process), the first sub-signal line 111a located in the upper left direction and the lower right direction of the first segment signal line 11 is disposed on 370 layers with the first gate electrode 330, and the schematic structure of the schematic structure is shown in fig. 7 (fig. 7 further includes a substrate 300, an active layer 320, a first gate insulating layer 310, a first gate electrode 330, a second gate insulating layer 340, a second gate electrode 350, an interlayer dielectric layer 360, and a source and drain electrode 370 sequentially disposed), where the insulating layer 210 in fig. 3 includes the second gate insulating layer 340 and the interlayer dielectric layer 360); the second sub-signal lines 211b of the second segment signal lines 21 located in the upper right direction and the lower left direction are arranged in the same layer as the first gate electrode 330, and the second sub-signal lines 211a of the second segment signal lines 21 located in the upper left direction and the lower right direction are arranged in the same layer as the source drain electrode 370 (see fig. 8).
In some embodiments, the first sub-signal lines 111b located in the upper right direction and the lower left direction in the first segment of signal lines 11 are arranged in the same layer as the first gate electrode, and the first sub-signal lines 111a located in the upper left direction and the lower right direction in the first segment of signal lines 11 are arranged in the same layer as the source drain electrode; the second sub-signal lines 211b located in the upper right direction and the lower left direction of the second segment signal lines 21 are arranged in the same layer as the source and drain electrodes, and the second sub-signal lines 211a located in the upper left direction and the lower right direction of the second segment signal lines 21 are arranged in the same layer as the first gate electrodes.
In some embodiments, the first sub-signal lines 111b located in the upper right direction and the lower left direction in the first segment of signal lines 11 are arranged in the same layer as the second gate electrode, and the first sub-signal lines 111a located in the upper left direction and the lower right direction in the first segment of signal lines 11 are arranged in the same layer as the source drain electrode; the second sub-signal lines 211b located in the upper right direction and the lower left direction of the second segment signal lines 21 are arranged in the same layer as the source and drain electrodes, and the second sub-signal lines 211a located in the upper left direction and the lower right direction of the second segment signal lines 21 are arranged in the same layer as the second gate electrodes.
In some embodiments, the first sub-signal lines 111b located in the upper right direction and the lower left direction of the first segment signal line 11 are arranged in the same layer as the source and drain electrodes, and the first sub-signal lines 111a located in the upper left direction and the lower right direction of the first segment signal line 11 are arranged in the same layer as the second gate electrode; the second sub-signal lines 211b located in the upper right and lower left directions of the second segment signal lines 21 are arranged in the same layer as the second gate electrode, and the second sub-signal lines 211a located in the upper left and lower right directions of the second segment signal lines 21 are arranged in the same layer as the source and drain electrodes.
In some embodiments, the first sub-signal lines 111b located in the upper right and lower left directions of the first segment signal lines 11 are arranged in the same layer as the first gate electrode, and the first sub-signal lines 111a located in the upper left and lower right directions of the first segment signal lines 11 are arranged in the same layer as the second gate electrode; the second sub-signal lines 211b located in the upper right and lower left directions of the second segment signal lines 21 are arranged in the same layer as the second gate electrode, and the second sub-signal lines 211a located in the upper left and lower right directions of the second segment signal lines 21 are arranged in the same layer as the first gate electrode.
In some embodiments, the first sub-signal lines 111b located in the upper right and lower left directions of the first segment signal lines 11 are arranged in the same layer as the second gate electrode, and the first sub-signal lines 111a located in the upper left and lower right directions of the first segment signal lines 11 are arranged in the same layer as the first gate electrode; the second sub-signal lines 211b located in the upper right and lower left directions of the second segment signal lines 21 are arranged in the same layer as the first gate electrode, and the second sub-signal lines 211a located in the upper left and lower right directions of the second segment signal lines 21 are arranged in the same layer as the second gate electrode.
In still other embodiments of the present invention, referring to fig. 9, the first section of signal line 10 includes three sections of first sub-signal lines 111 electrically connected in sequence, wherein one section of first sub-signal line 111 is arranged in the same layer as the source and drain electrodes, one section of first sub-signal line 111 is arranged in the same layer as the first gate electrode, and the other section of first sub-signal line 111 is arranged in the same layer as the second gate electrode; the second section of signal line 20 includes three sections of second sub-signal lines 211 electrically connected in sequence, wherein one section of second sub-signal line 211 is arranged on the same layer as the source and the drain, one section of second sub-signal line 211 is arranged on the same layer as the first grid, and the other section of second sub-signal line 211 is arranged on the same layer as the second grid. Therefore, the lengths of the first sub-signal line and the second sub-signal line of each section can be further shortened, and the antenna effect is further effectively avoided.
As will be understood by those skilled in the art, the above-mentioned first signal lines and second signal lines refer only to signal lines which are closer to the hole digging region and have first signal lines and second signal lines which need to be disposed around the hole digging region, respectively, and in addition to the above-mentioned first signal lines and second signal lines, the array substrate further includes first signal lines and second signal lines which are farther from the hole digging region, the first signal lines and the second signal lines do not have the first signal lines and the second signal lines which are disposed around the hole digging region, and are located in the screen display region, and the first signal lines and the second signal lines are still each independently disposed at intervals in the first direction and the second direction.
According to an embodiment of the present invention, referring to fig. 10, the array substrate further includes: at least one closed loop shielding line 30 in the through hole packaging region, at least one shielding line 30 is disposed around the hole digging region 101, and the orthographic projection of the shielding line 30 on the substrate 300 (not shown in the figure) in the array substrate is located between the orthographic projection of the hole digging region 101 on the substrate 300 and the orthographic projection of the first section signal line 11 and the second section signal line 21 on the substrate 300 (i.e. the orthographic projection includes the orthographic projection of the first section signal line 11 on the substrate 300 and the orthographic projection of the second section signal line 21 on the substrate 300), wherein the shielding line is electrically connected with a constant potential. Therefore, after the display panel is manufactured (namely, the hole digging area is dug out to form a through hole), the shielding wire electrically connected with the constant potential can shield static electricity from the inner side of the through hole (namely, the static electricity introduced into the array substrate by the through hole in the external environment), so that the display quality of a display picture is improved, and the comprehensive yield of the array substrate and the display panel is further improved.
According to an embodiment of the present invention, the shielding line and at least one of the source and drain electrodes, the first gate electrode, and the second gate electrode in the thin film transistor in the picture display region are formed through a one-time patterning process. Therefore, the structure is formed with the existing structure in the array substrate by one-step process, and further the process flow for manufacturing the array substrate can be saved.
According to the embodiment of the invention, the specific structure of the constant potential is not particularly required, and the person skilled in the art can flexibly select the constant potential according to actual situations. In some embodiments, the potentiostatic potential includes, but is not limited to, a drive voltage signal line and an initialization voltage signal line. Therefore, static electricity at the through hole can be effectively shielded, connection of a circuit is facilitated, and implementation in the process is facilitated.
In another aspect of the present invention, a display panel is provided. According to an embodiment of the present invention, the display panel includes the array substrate described above. Therefore, static electricity is not easy to generate in the display panel area around the through hole, and the comprehensive yield of the display panel is greatly improved. Those skilled in the art will appreciate that the display panel has all the features and advantages of the array substrate described above, and will not be described in detail herein.
According to the embodiment of the invention, the display panel can be an LCD display panel or an OLED display panel, and those skilled in the art can flexibly select the display panel according to practical situations.
According to the embodiment of the invention, the specific application of the display panel is not particularly required, and a person skilled in the art can flexibly select the display panel according to actual requirements, for example, the display panel can be used in all devices and apparatuses with display functions, such as mobile phones, televisions, notebooks, iPads, game machines, kine and the like.
It will be appreciated by those skilled in the art that the display panel includes, in addition to the aforementioned array substrate, the necessary structures or components of a conventional display panel, for example, an LCD mobile phone, and includes, in addition to the array substrate, structures such as a barrier layer, a color film substrate, and a liquid crystal layer.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (7)
1. An array substrate, characterized in that, the array substrate has a display area, the display area includes picture display area, through-hole encapsulation district and hole digging district, the through-hole encapsulation district is around setting up the circumference of hole digging district, picture display area is around setting up the circumference of through-hole encapsulation district, just hole digging district is used for forming the through-hole, includes:
the first signal lines are arranged at intervals along a first direction, each first signal line comprises a first section of signal line which is positioned in the through hole packaging area and surrounds a part of the hole digging area, the first section of signal line comprises three sections of first sub-signal lines which are electrically connected in sequence, wherein two adjacent sections of first sub-signal lines are arranged in different layers and are electrically connected through a through hole, one section of first sub-signal lines is arranged in the same layer as a source electrode and a drain electrode, one section of first sub-signal lines is arranged in the same layer as a first grid electrode, and the other section of first sub-signal lines is arranged in the same layer as a second grid electrode;
in the first direction, the outer peripheral line of the hole digging region includes a left segment portion and a right segment portion, a straight line A-A extends in a second direction and intersects the hole digging region, the first segment of the first signal lines located on the left side of the straight line A-A is disposed around the left segment portion, the first segment of the first signal lines located on the right side of the straight line A-A is disposed around the right segment portion,
a plurality of second signal lines arranged at intervals along the second direction, wherein each second signal line comprises a second section of signal line which is positioned in the through hole packaging area and surrounds a part of the hole digging area, the second section of signal line comprises three sections of second sub-signal lines which are electrically connected in sequence, wherein two adjacent sections of second sub-signal lines are arranged in different layers and are electrically connected through the through holes, one section of second sub-signal line is arranged in the same layer as the source drain electrode, one section of second sub-signal line is arranged in the same layer as the first grid electrode, the other section of second sub-signal line is arranged in the same layer as the second grid electrode,
and the second sub-signal line with two different layers on the left side of the A-A overlaps the same first sub-signal segment, and the second sub-signal line with two different layers on the right side of the A-A overlaps the same first sub-signal segment.
2. The array substrate of claim 1, wherein the first sub signal line positioned at the left side of the straight line A-A and disposed adjacent to the straight line A-A is disposed at a different layer from the first sub signal line positioned at the right side of the straight line A-A and disposed adjacent to the straight line A-A, and is not electrically connected.
3. The array substrate according to claim 1, wherein in the second direction, an outer peripheral line of the hole-digging region includes an upper section and a lower section, a straight line B-B extends in the first direction and intersects the hole-digging region, the second section of the second signal lines located on an upper side of the straight line B-B being disposed around the upper section, and the second section of the second signal lines located on a lower side of the straight line B-B being disposed around the lower section.
4. The array substrate of claim 3, wherein the second sub signal lines positioned at the lower side of the straight line B-B and disposed adjacent to the straight line B-B are disposed at different layers from the second sub signal lines positioned at the upper side of the straight line B-B and disposed adjacent to the straight line B-B, and are not electrically connected.
5. The array substrate of claim 3, further comprising: the shielding wires are arranged around the hole digging area, the orthographic projection of the shielding wires on the substrate in the array substrate is positioned between the orthographic projection of the hole digging area on the substrate and the orthographic projection of the first section of signal wires and the second section of signal wires on the substrate, and the shielding wires are electrically connected with a constant potential.
6. The array substrate of claim 5, wherein the shielding line and at least one of the source and drain electrodes, the first gate electrode, and the second gate electrode in the thin film transistor in the picture display region are formed through a one-time patterning process.
7. A display panel comprising the array substrate of any one of claims 1 to 6.
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| CN202010002047.7A CN111176040B (en) | 2020-01-02 | 2020-01-02 | Array substrate and display panel |
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| CN202010002047.7A CN111176040B (en) | 2020-01-02 | 2020-01-02 | Array substrate and display panel |
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| CN111599852B (en) * | 2020-06-02 | 2023-02-07 | 京东方科技集团股份有限公司 | Display panel, display device and manufacturing method of display panel |
| CN113571567B (en) * | 2021-07-26 | 2024-01-05 | 云谷（固安）科技有限公司 | Display panel and display device |
| CN113920920B (en) * | 2021-11-04 | 2024-03-29 | 厦门天马微电子有限公司 | Array substrate, display panel and display device |
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