CN111162800A - Parallel convolutional coding method and coder - Google Patents
Parallel convolutional coding method and coder Download PDFInfo
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- CN111162800A CN111162800A CN201911373236.9A CN201911373236A CN111162800A CN 111162800 A CN111162800 A CN 111162800A CN 201911373236 A CN201911373236 A CN 201911373236A CN 111162800 A CN111162800 A CN 111162800A
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
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Abstract
The invention discloses a parallel convolutional coding method and a coder, wherein K input bits to be coded are received in the same clock period according to a coding rate, and the received K input bits and 6 register bits which are pre-loaded in a coding register are applied to an exclusive-or array through a logic arithmetic unit to carry out exclusive-or operation so as to output N coded output bits, wherein K is more than or equal to 4, and N is the length of a required code group; by adopting the parallel convolutional coding method, because of adopting parallel multi-bit input and output, the clock frequency can be greatly reduced, thereby effectively saving electric energy, and the effect is more obvious particularly when the constraint length and the code group length required by coding are both larger; in addition, in the encoding process, the punching data is directly created by adopting a logical operation mode, and independent punching operation is not required, so that the hardware design is simplified to the maximum extent.
Description
Technical Field
The present invention relates to the field of communication coding technology, and in particular, to a parallel convolutional coding method and a parallel convolutional encoder applied to a wireless communication device.
Background
The encoder is used for a transmitting end of the wireless digital communication equipment. In a binary block code (N, K), containing K information bits, the length of the code block is N, and the (N-K) check bits of each code block are related to the K information bits of the code block only and are not related to other code blocks. In order to achieve a certain error correction capability and coding efficiency (K/N), the block length N of a block code is usually large. The whole information code group must be stored when coding and decoding, and the delay generated by the storage increases linearly with the increase of N. To reduce this delay, various solutions have been proposed, among which convolutional codes are a better way of channel coding. This coding also encodes K information bits into N bits, but K and N are usually small and are particularly suitable for transmitting information in serial form. Fig. 2 shows a conventional convolutional encoder with a coding rate of 1/3, which can generate different code rates, such as 1/2, 5/8 or 3/4, by using puncturing and bit padding. However, as K and N increase, the clock frequency of the convolutional encoder becomes higher, which results in higher power consumption, and the encoding efficiency is not ideal due to the need of the puncturing operation.
Disclosure of Invention
It is an object of the present invention to solve the above-mentioned technical problems by providing a parallel convolutional encoding method which has a low clock frequency and does not require a separate puncturing operation.
It is another object of the present invention to provide a parallel convolutional encoder with a low clock frequency and which does not require a separate puncturing operation.
In order to achieve the above object, the present invention discloses a parallel convolutional encoding method, which includes: receiving K input bits to be coded in the same clock period according to a coding rate, applying the received K input bits and 6 register bits pre-loaded in a coding register in an XOR array through a logic arithmetic unit to carry out XOR operation so as to output N coded output bits, wherein K is larger than or equal to 4, N is the required code block length, and after the coding is finished, updating the coding register by adopting the K input bits received in the coding period.
Compared with the prior art, the parallel convolutional coding method can simultaneously code a plurality of input bits in each clock period, and the coding process adopts a logic operation mode, namely, the XOR operation is carried out on the K input bits and the 6 register bits registered in the coding register, so as to obtain output bits, therefore, by adopting the parallel convolutional coding method, the constant frequency can be greatly reduced due to the adoption of parallel multi-bit input and output, so that the electric energy is effectively saved, and the effect is more obvious particularly when the constraint length and the code group length required by coding are both larger; in addition, in the encoding process, the punching data is directly created by adopting a logical operation mode, and independent punching operation is not required, so that the hardware design is simplified to the maximum extent.
Preferably, the encoding rate is 1/2, and each clock cycle receives 4 input bits to encode and generates 8 output bits.
Preferably, when the input bits received in the present encoding clock cycle are used to update the encoding register, and the input bits are less than 6 bits, register bits of different data bits in the encoding register may be assigned to each other for updating.
The invention also discloses a parallel convolution encoder, which comprises an input unit, an encoding calculation unit and an output unit; the input unit is used for controlling each clock cycle to input K input bits to be coded to the coding calculation unit, the coding calculation unit comprises a coding register and a logic arithmetic unit, the coding register is used for preloading 6-bit register bits before each coding clock cycle starts, the logic arithmetic unit applies the received K input bits and the 6-bit register bits preloaded in the coding register to an exclusive-or array for exclusive-or operation so as to output N coded output bits to the output unit, wherein K is more than or equal to 4, N is the required code group length, and the output unit is used for receiving and latching the calculation result of the coding calculation unit; and in each coding clock period, after the coding work is finished, updating the coding register by adopting K input bits received in the current coding period.
Preferably, the input unit includes an input register for storing input bits to be input, and an input controller for controlling the number of input bits input to the encoding calculation unit per encoding clock.
Preferably, the encoding rate is 1/2, and each clock cycle receives 4 input bits to encode and generates 8 output bits.
Preferably, when the input bits received in the present encoding clock cycle are used to update the encoding register, and the input bits are less than 6 bits, register bits of different data bits in the encoding register may be assigned to each other for updating.
Preferably, the output unit includes an output register whose number of bits takes a least common multiple of a code group length corresponding to a plurality of desired coding rates.
The present invention also discloses a parallel convolutional encoder, comprising:
one or more processors;
a memory;
and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs comprising instructions for performing the parallel convolutional encoding method as described above.
The present invention also discloses a computer readable storage medium comprising a computer program for testing, the computer program being executable by a processor to perform the parallel convolutional encoding method as described above.
Drawings
FIG. 1 is a block diagram of a parallel convolutional encoder according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a conventional convolutional encoder.
Detailed Description
In order to explain technical contents, structural features, and objects and effects of the present invention in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
The invention discloses a parallel convolution encoder, which comprises an input unit 10, an encoding calculation unit 11 and an output unit 12, as shown in figure 1. The input unit 10 is configured to control each clock cycle to input K input bits to be encoded to the encoding calculation unit 11, the encoding calculation unit 11 includes an encoding register 110 and a logic operator 111, the encoding register 110 is configured to pre-load 6-bit register bits before each encoding clock cycle starts, the logic operator 111 applies the received K input bits and the 6-bit register bits pre-loaded in the encoding register 110 to an xor array for performing an xor operation, so as to output N encoded output bits to the output unit 12, where K is greater than or equal to 4, N is a required code group length, and the output unit 12 is configured to receive and latch a calculation result of the encoding calculation unit 11; in each coding clock period, after the coding operation is finished, the coding register 110 is updated by using the K input bits received in the current coding period. The working method for coding by adopting the parallel convolutional encoder comprises the following steps: according to the encoding rate, receiving K input bits to be encoded in the same clock cycle, applying the received K input bits and 6 register bits pre-loaded in the encoding register 110 to an XOR array through the logic arithmetic unit 111 to perform XOR operation so as to output N encoded output bits, and after the encoding is finished, updating the encoding register 110 by using the K input bits received in the encoding cycle. The parallel convolutional encoder is adopted for encoding, a plurality of input bits can be encoded at the same time in each clock period, and the encoding process adopts a logic operation mode, namely, the XOR operation is carried out on the K input bits and the 6 register bits registered in the encoding register 110, so as to obtain output bits; in addition, in the encoding process, the punctured data is directly created by adopting a logical operation mode, and a separate puncturing operation is not required, so that the hardware design is simplified to the maximum extent. Preferably, the input unit 10 includes an input register 100 and an input controller 101, the input register 100 is used for storing input bits to be input, and the input controller 101 is used for controlling the number of input bits input to the encoding calculation unit 11 per encoding clock. The output unit 12 includes an output register 120.
The following takes parallel convolutional encoders with four code rates as examples, and specifically describes the encoding principle of the parallel convolutional encoding.
1. 1/2 code rate parallel convolution encoder
in the above calculation formula (1), ⊕ represents exclusive or calculation, X0、Y0、X1、Y1、X2、Y2、X3、Y3To operate the register bits, the subscripts in the register bits indicate each state increment corresponding to a conventional convolutional encoder, and after the encoding calculation, and the output bits are latched into the output register 120, the encoding register 110 may be updated in the following calculation manner:
in the above updating process of the coding register 110, since the input bits are less than 6 bits, the register bits of different data bits in the coding register 110 can be mutually assigned to update, i.e. R is assigned1And R0Respectively assign to R5And R4To R with5And R4And (6) updating. However, the update sequence is not fixed, i.e. I can be set0Is assigned to R1、R2Etc. other register bits, other than R, may be used5The value of any external register bit is assigned to R5Such as by reacting R2Is assigned to R5。
After the clock cycle is completed, the input controller 101 selects the other 4 input bits (I) from the input register 100 in the next clock cycle4、I5、I6、I7) The encoder prepares to calculate a second set of 8 encoded bits, which can be clocked continuously as long as input bits are available.
It should be noted that, since the output bits of 8 output bits obtained in each clock cycle are directly calculated, they need to be the same as the output values of the conventional convolutional encoder at 4 clocks, according to fig. 2 and the above equation (1), X0And Y0Is the same as the conventional encoder in fig. 1, in order to calculate X1And Y1Conventional encoders synchronize shift registers at one clock cycle position, but in the parallel convolutional encoder of the present invention, since the correct input to the xor function is already present, no shifting is required, only from the already present dataTaking, also for X2、Y2、X3、Y3As well as so. Thus, the 8 output bits latched into the output register 120 can directly compute all output bits at the same time.
2. 3/4 code rate parallel convolution encoder
In this embodiment, M is 8, i.e. the input register 100 has 8 input bits, the output register 120 has 8 output bits, the input controller 101 controls the first 6 input bits to be read from the input register 100 every clock cycle, the encoding result obtains 8 output bits, and since the punch position is not calculated, the 8 output formats of the parallel convolutional encoder are set as X0、Y0、Y1、X2、X3、Y3、Y4、X5They can be directly calculated by the following calculation method (3) without deleting any unnecessary bits.
After latching the computation result into output register 120, 6 current input bits (I)5..I0) Is loaded into the encoding register 110 to update the encoding register 110, but it should be noted that since the input register 100 is a fixed 8-bit input, i.e. each time an input word comprising 8 input bits is read from memory, 2 input bits (I) are input6，I7) Not used, requiring 4 bits (I) latched with the next input word11..I8) Used together to form the next 6-bit input word of the parallel convolutional encoder, and the remaining 4 unused input bits (I) are calculated15..I12) Can be latched up with 2 bits (I) of the next input word17..I16) Used together to form the next input set. Finally, the current input word (I) may be used23..I18) The last 6 bits and the sequence is repeated.
3. 7/8 code rate parallel convolution encoder
In the same manner as the code rate of 3/4, the code rate 7/8 encoding computes 8 output bits directly from 7 input bits without a separate puncturing operation. The 8 outputs can be directly calculated from the following equation (4). Similar to the input control of rate 3/4, 7 of the 8 input bits are used with the latched unused bits for use with the next input word.
4. 2/3 and 5/6 code rate parallel convolution encoder
Encoding at rates 2/3 and 5/6 is similar, but the encoded output bits and input bits are both 6, i.e., M is 6, the output bits encoded at a rate 2/3 are calculated according to the following equation (5), and the output bits encoded at a rate 5/6 are calculated according to the following equation (6):
in the above embodiment, the output bits of the 1/2 rate, 3/4 rate and 7/8 rate parallel convolutional encoders are all 8 bits, but the output bits of the 2/3 rate and 5/6 rate parallel convolutional encoders are 6 bits, so when the coding rate is changed from 1/2 to 2/3, the number of bits of the output register is changed accordingly, so that in order to make the same encoder adaptable to different coding rates, the number of bits of the output register 120 may be the least common multiple of the block lengths corresponding to a plurality of required coding rates, for the above four coding rates, the output register 120 may be expanded to M-24 bits, then the output bits for the above four coding rates will completely fill the output register 120, for the 1/2 rate, the 3/4 rate and the 7/8 rate, since 8 is a common factor of 24, the output result of 8-bit bytes can be extracted from the output of the parallel convolutional encoder, and the same is true for the 2/3 code rate and the 5/6 code rate.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the scope of the present invention, therefore, the present invention is not limited by the appended claims.
Claims (10)
1. A parallel convolution coding method is characterized in that K input bits to be coded are received in the same clock cycle according to a coding rate, a logic arithmetic unit is used for applying the received K input bits and 6 register bits pre-loaded in a coding register to an XOR array for XOR operation so as to output N coded output bits, wherein K is larger than or equal to 4, N is the required code group length, and after the coding is finished, the coding register is updated by adopting the K input bits received in the coding cycle.
2. The parallel convolutional encoding method of claim 1, wherein the code rate is 1/2, and 4 input bits are received per clock cycle for encoding and 8 output bits are generated.
3. The parallel convolutional encoding method of claim 1, wherein when the encoding register is updated with the input bits received in the present encoding clock cycle, if the input bits are less than 6 bits, the register bits of different data bits in the encoding register are assigned to each other for updating.
4. A parallel convolution encoder is characterized by comprising an input unit, an encoding calculation unit and an output unit; the input unit is used for controlling each clock cycle to input K input bits to be coded to the coding calculation unit, the coding calculation unit comprises a coding register and a logic arithmetic unit, the coding register is used for preloading 6-bit register bits before each coding clock cycle starts, the logic arithmetic unit applies the received K input bits and the 6-bit register bits preloaded in the coding register to an exclusive-or array for exclusive-or operation so as to output N coded output bits to the output unit, wherein K is more than or equal to 4, N is the required code group length, and the output unit is used for receiving and latching the calculation result of the coding calculation unit; and in each coding clock period, after the coding work is finished, updating the coding register by adopting K input bits received in the current coding period.
5. The parallel convolutional encoder of claim 4, wherein the input unit comprises an input register for storing input bits to be input and an input controller for controlling the number of input bits input to the encoding calculation unit per encoding clock.
6. The parallel convolutional encoder of claim 4, wherein the code rate is 1/2, and wherein each clock cycle receives 4 input bits for encoding and generates 8 output bits.
7. The parallel convolutional encoder of claim 4, wherein when the input bits received in the present encoding clock cycle are used to update the encoding register, if the input bits are less than 6 bits, the register bits of different data bits in the encoding register are also used to assign values to each other for updating.
8. The parallel convolutional encoder of claim 4, wherein the output unit comprises an output register whose number of bits takes the least common multiple of the block length corresponding to the plurality of desired coding rates.
9. A parallel convolutional encoder, comprising:
one or more processors;
a memory;
and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs comprising instructions for performing the parallel convolutional encoding method of any of claims 1 to 3.
10. A computer-readable storage medium comprising a test computer program executable by a processor to perform the parallel convolutional encoding method as claimed in any one of claims 1 to 3.
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