CN111162795A

CN111162795A - LDPC coding hardware implementation method based on check sub-matrix segmentation

Info

Publication number: CN111162795A
Application number: CN202010010183.0A
Authority: CN
Inventors: 朱胜利; 谢玲; 王宇舟; 张庭兰
Original assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Current assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Priority date: 2020-01-06
Filing date: 2020-01-06
Publication date: 2020-05-15
Anticipated expiration: 2040-01-06
Also published as: CN111162795B

Abstract

The invention discloses an LDPC coding hardware implementation method based on coding sub-matrix segmentation, and aims to provide an LDPC coding hardware implementation method which is high in parallelism, low in operand, good in expandability and convenient for hardware implementation. The invention is realized by the following technical scheme: when FPGA codes, firstly, the check part of a generated matrix is divided into rows and columns according to the size of a cyclic subarray, and the first row of the cyclic subarray belonging to the same subblock is stored in a ROM (read only memory) table and is used as a basic coding unit (PE); the coding state machine controls the coding submodule PE to read out data from the ROM table and store the data into the coding shift register, expands input one-bit information into row vectors with the same number as the basic coding subarrays, completes the verification of a plurality of circular subarray rows through the operation of AND and XOR operation, and completes the division of the coding subarray based on the subarray storage of the ROM table and the block coding hardware of the generated matrix, and completes the coding of the submodule.

Description

LDPC coding hardware implementation method based on check sub-matrix segmentation

Technical Field

The invention relates to the technical field of channel coding, in particular to an LDPC coding hardware implementation method based on check sub-matrix segmentation, which can be applied to optical fiber communication, satellite communication and wireless communication.

Background

With the rapid development of communication technology and the continuous improvement of reliability requirements of various transmission modes, the channel coding technology is an important means of anti-interference technology, and plays an increasingly important role in the fields of digital communication technology and digital transmission. With the advent of digital cellular telephones, digital televisions, and high resolution digital storage devices, encoding techniques have increasingly been successfully employed in a variety of information communication and storage devices. One of the most commonly used error correction coding techniques is a Low Density Parity Check (LDPC) code, which is one of the codes commonly used in the CCSDS standard in the field of channel coding today. The check matrix is a sparse matrix, and is a linear block code based on the sparse check matrix. The name of the LDPC code is derived from that a check matrix is a sparse matrix, namely the number of non-O elements in the matrix is far less than that of the O elements, or the row weight and the column weight of the matrix are very small numbers compared with the code length. To design an LDPC code, the most straightforward and efficient method is to construct a low-density parity-check matrix H according to a specified standard. The sparse check matrix is a check matrix in which the number of "1" included in each row and each column is very small relative to the code length. And dividing the LDPC code into a regular LDPC code and an irregular LDPC code according to whether the row weight of each row in the check matrix is the same as the column weight of each column. The LDPC code is parallel in structure, and the codec is easy to implement in hardware, and is widely considered as a channel coding scheme capable of meeting high-speed data transmission and high-performance requirements of a fourth-generation mobile communication system. The LDPC code has the most significant characteristic that the check matrix is a large sparse matrix, but also results in a huge operation amount in the encoding process. In reality, the LDPC code can be applied not only to deep space communication with a large throughput, but also to an ultra-low speed wireless communication system, a transmission system of control and command information such as space flight, and the like. As one of the code patterns with the strongest error correction capability in channel coding, the LDPC code can obtain a high throughput with less resource consumption due to its simple decoder structure, but the application of the LDPC code is restricted by the complexity problem of the encoder as a negative factor. Although the check matrix of the LDPC code is a sparse matrix, the generated matrix is not sparse, so that the encoding complexity is proportional to the square of the code length. Because the code length of the LDPC code is long, from thousands to hundreds of thousands of bits, the encoding thereof becomes complicated, which hinders the application of the LDPC code to some extent. Meanwhile, the amount of operation of encoding is in the form of the square of the code length, when the code length is large. Measures need to be taken to reduce complexity. The quality of a coding method is completely determined by its check matrix, i.e. the structure of the check matrix is decisive for the performance of the code. The check matrix mainly has two types: a random check matrix and a structured check matrix. Although the randomly generated check matrix has good error correction performance, simple encoding cannot be realized due to the randomness of the check matrix, and the check matrix is high in storage complexity during decoding and is not beneficial to realization. The structured check matrix can be generated by algebraic geometry, combined construction and other modes, can overcome the generation of short circulation, has a determined structure, generates the LDPC code which is a cyclic code or a quasi-cyclic code, can realize linear time coding and simple decoding, can design a code with larger Girth, and has the error correction performance reaching the code generated by the random check matrix.

At present, there are many construction methods related to LDPC codes, and there are different construction methods for long codes, medium-long codes, and short codes, wherein the LDPC code construction methods can be mainly divided into two categories: one type is LDPC code with random structure, although the code has good error correction capability in long code, the code group is too long and the irregularity of the generated matrix and the check matrix makes the code too complex to be realized by hardware; the other is a structural code constructed by methods of geometric, algebraic and combinatorial design. Most LDPC structure codes have a cyclic or quasi-cyclic structure, and the quasi-cyclic codes have quite strong error correction capability in medium-short codes, and the performance is close to the optimal LDPC codes with random structures. Because the check part of the LDPC code generating matrix has poor sparsity and does not have too many rules, a large amount of resources are consumed by directly storing the generating matrix. The general method is to construct a lower triangular matrix or similar lower triangular matrix which is easy to encode, and encode by using the constraint relation between information bits and check bits in the matrix. Thus, although a linear encoding-capable LDPC code can be obtained, the LDPC code set is not only constrained by the node degree distribution, but also constrained by the check matrix form. Since the traditional encoding method generates code words by generating a matrix, the complexity is proportional to the square of the code length, which makes the LDPC code require a large amount of hardware resources and a long delay in encoding. The generator matrix of the LDPC code is non-sparse, when the LDPC code is long, the storage of a huge generator matrix is difficult, and the encoding by the generator matrix also has high time complexity. Compared with the simplicity of the LDPC decoding algorithm, the encoding algorithm is too complex, and particularly for the LDPC code with low sparsity and poor check matrix regularity, the hardware implementation of encoding is difficult, more hardware resources are consumed, and the encoding efficiency is low. Both the encoding step and the encoding complexity are proportional to the code length n. How to implement LDPC coding hardware quickly and efficiently has been a problem of great concern.

In order to solve the problem of encoding complexity of the LDPC code, various LDPC code encoding algorithms are proposed in the prior art, and common LDPC code encoding algorithms include an RU algorithm-based encoding method, a quasi-cyclic LDPC code and an encoding method thereof, a fast quasi-cyclic LDPC code encoding method, and the like. The traditional coding algorithm of the LDPC code is very similar to the general linear block code, and a generator matrix needs to be solved first. If an input information vector M of length k is known, and a generator matrix G of k × n is known, a codeword can be obtained by matrix multiplication: c ═ mxg. The generator matrix is obtained from the check matrix, and after the check matrix H is obtained, the generator matrix G can be obtained by a Gaussian elimination method by utilizing the orthogonality between H and G. The conventional encoding algorithm of the LDPC code mainly includes two steps of preprocessing and actual encoding. The precoding converts the check matrix H into an approximate lower triangular matrix form H' through row-column transformation, and the precoding is performed only once and can be preprocessed in software. Then dividing H' into 6 sparse matrixes, and obtaining p1 and p2 through step calculation, wherein the complexity of p1 is O (N + g2), and the calculation complexity of p2 is O (N). However, there is no satisfactory method for obtaining the approximate lower triangular matrix, and the check matrix rearranged by the greedy algorithm by t.j. Especially when the code length is long, this coding method is not an ideal implementation.

The quasi-cyclic LDPC code is an LDPC code with a special structure and an increasingly wide application range, and the check matrix Hqc is composed of a series of small cyclic square matrices, which may be permutation matrices or matrices based on finite geometry. Because of the quasi-cyclic characteristic of Hqc, a generator matrix with a systematic code form and a quasi-cyclic characteristic can be obtained, and the coding operation of the input information and the generator matrix can be realized only by adopting a shift register. Because the LDPC code is a linear block error correction code, its conventional encoding algorithm is similar to a linear block code, and its generator matrix must be calculated. Aiming at some special quasi-cyclic LDPC codes, D.E, Hocevar et al propose a method for fast coding by using a shift register only by using a check matrix, which is superior to an LDPC coding scheme based on an RU algorithm in view of low implementation complexity, but is only suitable for the LDPC codes with the quasi-cyclic characteristic.

In the common coding algorithm, H2-1 obtained by the Gaussian elimination method is neither a sparse matrix nor an obvious quasi-cyclic characteristic, so that the computational complexity is high in the computational process, the computational speed is reduced, and the overall coding speed and efficiency are influenced.

At present, the LDPC code fast coding structure based on matrix partitioning becomes a research hotspot due to the performance close to the Shannon limit and the high-speed parallel decoding structure. However, the hardware implementation of the codec becomes difficult when the code length is long. In order to solve the hardware implementation difficulty of the codec, the prior art documents disclose a Gallager structure method, a Mackay structure method and a short code length LDPC fully parallel decoder hardware structure with good error correction performance. Because the check matrixes of the Gallager construction method and the Mackay construction method are randomly generated, although the error correction performance of the check matrixes is good, simple coding cannot be realized due to the randomness of the check matrixes, and meanwhile, the decoding complexity is high, so that the system design becomes very complicated; and the hardware implementation complexity of LDPC codes constructed in this manner can be significant. Because the generating matrix of the LDPC code is non-sparse, when the LDPC code is long, it is difficult to store a huge generating matrix, and the encoding directly by using the generating matrix usually has higher time complexity, which is not beneficial to hardware implementation.

Disclosure of Invention

Aiming at solving the problem of coding complexity of the LDPC code, the invention aims to overcome the defects of large direct coding operand and high complexity of the existing LDPC coding technology and provides the LDPC coding hardware implementation method which has high parallelism, low operand, good expandability, is convenient for hardware implementation, has low coding complexity, and can adapt to any code rate and code length and is based on coding sub-matrix division.

The above object of the present invention can be achieved by the following technical solutions, and an LDPC coding hardware implementation method based on coding sub-matrix partitioning has the following technical features: in order to improve the parallelism of coding, modularize the coding, save hardware resources and realize modular coding, when the FPGA codes, based on the VHDL language of the FPGA, firstly, the check part of a generated matrix is divided into columns and blocks according to the size of a cyclic sub-matrix, and each column block comprises one or more cyclic sub-matrices; storing the first row of each cyclic subarray in a ROM (read only memory) table, wherein the number of the ROM tables is consistent with the number of the P matrix column blocks; the ROM tables correspond to a part of the LDPC generator matrix check part, each of the ROM tables being an encoding sub-module (PE) of one basic encoding unit; the coding state machine calls different first rows of the cyclic subarrays to block the check part of the generated matrix according to columns, the number of columns of each subarray is equal to the multiple of the number of the cyclic subarray, a coding submodule (PE) reads out one piece of data from a ROM (read only memory) table and stores the data into a coding shift register, input one piece of information is expanded into row vectors with the same number as the basic coding subarray, checking of a plurality of cyclic subarray rows is completed simultaneously by using 1 piece of input information through the operation of AND (exclusive OR) operation, a check sequence and an information sequence corresponding to LDPC coding are realized, partitioning of the coding subarray is realized on the basis of subarray storage of the ROM table and the block coding hardware of the generated matrix, and coding of the submodule is completed.

Compared with the prior art, the invention has the following beneficial effects.

High parallelism and low computation. Aiming at the problems that the check part of an LDPC code generation matrix is poor in sparsity and has no too many rules, a large amount of resources are consumed by directly storing the generation matrix, and the like, the invention provides a method for realizing the partition of a coding sub-matrix based on sub-matrix storage of a ROM (read only memory) table and block coding of the generation matrix, the sparse check sub-matrix is partitioned into rows and columns according to the size of a cyclic sub-matrix, the sub-matrix after being partitioned into columns is stored in corresponding ROM table 1 and ROM table 2 … ROM table N to serve as coding sub-modules PE, and the number of columns of each sub-block PE is equal to the multiple of the number of columns of the cyclic sub-matrix. The hardware implementation structure of the coding structure is simple, the parallelism is high, and the operation amount is low. Can be flexibly applied to various types of LDPC codes, and can effectively allocate memory units and realize parallel processing in the operation process to the maximum extent possible.

With lower coding complexity. The check part of the generated matrix is divided into blocks according to columns, the division standard can be determined according to practical application, and the row of each block can contain one cyclic subarray or a plurality of cyclic subarrays in consideration of hardware resources. In the process of coding each basic unit, only the first row of each cyclic sub-matrix needs to be stored, and the acquisition of the first rows of different sub-matrices is controlled by a state machine, so that hardware resources are effectively saved, and the hardware implementation is very simple. During coding, each part is used as a coding sub-module (PE), and the coding of all the parts only needs to be implemented by multiple instantization coding sub-modules. The coding mode is flexible, easy to expand and simple in hardware implementation structure. The huge operation amount requirement and storage amount requirement of the LDPC code with random construction on the coding are greatly reduced.

In order to improve the parallelism of the codes and modularize the codes so as to save hardware resources, the invention divides the generated matrix into blocks according to columns and realizes modularized coding. During coding, one bit of input information completes the verification of a plurality of cyclic subarrays simultaneously, the coding parallelism is increased, the coding complexity is further simplified, and the coding speed is greatly improved. Due to the particularity of the cyclic subarray, only the first row of the cyclic subarray can be stored in the ROM table, resources are saved, and other rows of the subarray can be obtained by right shifting according to the cycle of the first row. Therefore, when encoding, only need to judge whether need to read the new head line, and this process is realized by the state control module. In other cases, the encoding of the sub-modules can be completed through AND and XOR operation.

Convenient to expand, the practicality is strong. The invention reads out a datum from a ROM table, stores the datum in the coding shift register, inputs a bit of information, expands the bit into a row vector with the same order as a cyclic sub-array, then completes the coding of the sub-module through simple AND and XOR operation, and can adapt to LDPC coding with any code rate and code length. The coding mode is flexible and easy to expand, and can reduce the consumption of FPGA resources. By storing the first row of the cyclic submatrix in each basic coding unit and storing the first row in the ROM table, the corresponding generated submatrix can be obtained by looking up the ROM table when the FPGA codes conveniently, and the method has strong practicability.

Drawings

FIG. 1 is a schematic diagram of an LDPC hardware coding scheme based on sub-matrix partitioning according to the present invention.

FIG. 2 is a flow chart of the LDPC coding algorithm based on the sub-matrix partitioning of the present invention.

Detailed Description

See fig. 1. According to the invention, in order to improve the parallelism of coding and modularize the coding, save hardware resources and realize modularized coding, when the FPGA codes, firstly, the check part of a generated matrix is divided into rows and columns according to the size of a cyclic sub-matrix, and each row block comprises one or more cyclic sub-matrices; the first row of each cyclic sub-array is stored in a ROM table. Because the first row of each column of block cyclic array is stored in the ROM table, the ROM table corresponds to a part of the check part of the LDPC generator matrix, when in coding, each ROM table is used as a coding sub-module (PE) of a basic coding unit, and how to call different cyclic sub-array first rows is controlled by a coding state machine; after the check part of the generated matrix is blocked according to columns, the number of columns of each sub-matrix is equal to the multiple of the number of the cyclic sub-matrix, because each sub-block can be spliced together by a plurality of parallel cyclic sub-blocks, in order to utilize the cyclic characteristic of the cyclic sub-matrix, colleagues also save resources, and only the first row of the cyclic sub-matrix in each basic coding unit is saved and stored in a ROM table; when the basic coding unit is coded, reading out a datum from a ROM table and storing the datum into a coding shift register, inputting a bit of information, expanding the bit into a row vector with the same number as the basic coding subarray, and then completing the coding of the submodule through AND and XOR operation; and after all the basic coding units are coded, obtaining code word information bits and check bits, partitioning the check part of the generated matrix according to columns, storing the sub-matrix after column division into corresponding ROM table 1 and ROM table 2 … ROM table N as parallel sub-blocks of the coding sub-modules, and enabling the number of columns of each sub-block to be equal to the multiple of the number of columns of the cyclic sub-array. In order to utilize the characteristics of the cyclic sub-matrix and save resources, the first row of the cyclic sub-matrix in each basic coding unit is stored in the ROM table in order. When the basic coding unit is coded, reading out a datum from a ROM table and storing the datum into a coding shift register, inputting a bit of information, expanding the bit into a row vector with the same order as a coding sub-array, and then completing the coding of the sub-module through simple operations of phase addition, exclusive or and the like; and when all the basic coding units finish coding, obtaining a code word information bit and a check bit, and executing the above operation on each coding subarray to realize that the check of all the cyclic subarray rows is finished by using 1-bit input information simultaneously so as to increase the coding parallelism. And after all the basic coding units finish coding, obtaining a code word information bit and a check bit, and finally finishing output from the data output interface.

During encoding, each row divided into one block comprises one cyclic subarray or a plurality of cyclic subarrays, different cyclic subarrays are switched by reading different ROM addresses, the process is realized through a state control module, the state control module performs independent encoding on each submodule through state control, and finally results of all submodules are spliced to form total encoding, so that encoding of the LDPC code is realized.

In an optional embodiment, in order to obtain an LDPC code that meets the requirement of a satellite communication system for high reliability of channel error correction coding, a generation matrix G of the LDPC code is obtained by using an original pattern expansion method recommended by the CCSDS standard for expansion splitting of an original pattern base matrix structure, the expansion method uses a progressive edge growth PEG (PEG) algorithm, uses an AR4JA code optimized construction method based on original pattern expansion, and establishes an AR4JA coding stereo Tanner graph model by expanding a composite node associated with a check node on the basis of an original pattern construction template. And finally obtaining the required LDPC generator matrix G.

In an alternative embodiment, considering a quasi-cyclic LDPC code, let the LDPC code generator matrix G ═ I, P]Where I is a K × K identity matrix of LDPC, and P is a dense quasi-cyclic matrix of dimension K × (N-K), whose dense quasi-cyclic matrix P is as follows:

wherein, Mij represents a cyclic subarray forming the LDPC code check matrix, and m and n respectively represent the row number and the column number of the cyclic subarray.

L-order cyclic matrix M of check matrix P_i,jAs will be shown below, in the following,

where aij denotes each element of the cyclic sub-array, i 1, 2.

The performance of the proposed algorithm is explained in the present invention using LDPC (980, 784) codes, where L is 14, m is 56, and n is 14 when the simulation is performed using the LDPC code.

Referring to fig. 2, each data in the ROM table may be the first row of a plurality of cyclic sub-arrays, as the case may be, each data is exactly one row of one cyclic sub-array, a bit of information is input to expand the bit into a row vector having the same order as the cyclic sub-array for the convenience of calculation of the following check code word, when the basic coding unit is coded, the coding starts from the i-th 1 information bit, the j-th 1 row of the cyclic sub-array, when the basic coding unit is coded, the i-th information bit α data is read from the ROM table and stored in the coding shift register, and the input bit of information α is bit expanded and is compared with the bit of the input bit of information αThe bit is expanded into a row vector with the same number L as the cyclic subarray; becomes bit information after spreading

Then, the bit information A and the value in the coding shift register are summed to obtain an intermediate vector B; performing XOR on the result B of the AND and the median value of the check shift register to enable the result of the XOR to cover the current check shift register; and judging whether a new subarray needs to be read again and stored in the coding register, if so, reading the new subarray from the ROM table, otherwise, circularly moving the current coding register to the right, continuing coding, repeating the process until all the coding subarrays participate in operation, and finishing output after all the basic coding units finish coding to obtain a code word information bit and a check bit.

When judging whether a new subarray needs to be read again, judging whether the shift frequency j of the register is smaller than the order L of the quasi-cyclic subarray, if the check bit j is smaller than the order L, shifting the value in the coding shift register by one bit to the right according to the cycle of a first row, feeding the value back to the step of inputting one-bit information, continuing to circulate downwards, and ending the program after obtaining a code word information bit and a check bit; otherwise, encoding the next information, i is i +1, encoding the next cyclic sub-array, at the moment, j is 1, then judging whether i is smaller than the number m of quasi-cyclic matrixes in each sub-array of the check matrix P, continuously reading out one data from the ROM table, storing the data in the encoding shift register, and continuously encoding until all cyclic sub-arrays finish checking.

Claims

1. An LDPC coding hardware realization method based on coding sub-matrix segmentation has the following technical characteristics: in order to improve the parallelism of coding, modularize the coding, save hardware resources and realize modular coding, when the FPGA codes, based on the VHDL language of the FPGA, firstly, the check part of a generated matrix is divided into columns and blocks according to the size of a cyclic sub-matrix, and each column block comprises one or more cyclic sub-matrices; storing the first row of the cyclic subarrays belonging to the same column block in a ROM table; the ROM tables correspond to a part of the check part of the LDPC generating matrix, and each ROM table is used as an encoding submodule PE of a basic encoding unit; the coding state machine calls different coding sub-modules PE, reads out data from a ROM table and stores the data in a coding shift register, expands input one-bit information into row vectors with the same number as the basic coding sub-array, uses 1-bit input information to simultaneously complete the check of a plurality of cyclic sub-array rows through the operation of AND and XOR operation, realizes the check sequence and the information sequence corresponding to the LDPC coding, and realizes the partition of the coding sub-matrix based on the sub-array storage of the ROM table and the block coding hardware of the generating matrix, thereby completing the coding of the sub-modules.

2. The LDPC coding hardware implementation method based on coding submatrix partitioning of claim 1, wherein: and after all the basic coding units finish coding, obtaining a code word information bit and a check bit, and finally finishing output from the data output interface.

3. The LDPC coding hardware implementation method based on coding submatrix partitioning of claim 1, wherein: during encoding, each row divided into one block comprises one cyclic subarray or a plurality of cyclic subarrays, different cyclic subarrays are switched by reading different ROM addresses, the process is realized through a state control module, the state control module performs independent encoding on each submodule through state control, and finally results of all submodules are spliced to form total encoding, so that encoding of the LDPC code is realized.

4. The LDPC coding hardware implementation method based on coding submatrix partitioning of claim 1, wherein: aiming at the expansion splitting of the basic matrix structure of the original pattern, the original pattern expansion method recommended by the CCSDS standard is adopted to obtain the generating matrix G of the LDPC code, the expansion method uses a gradual edge growth PEG algorithm, an AR4JA code optimization construction method based on the original pattern expansion is adopted, and on the basis of constructing a template by the original pattern, an AR4JA coding three-dimensional Tanner graph model is established by expanding compound nodes associated with check nodes, so that the required LDPC generating matrix G is obtained.

5. The LDPC coding hardware implementation method based on coding submatrix partitioning of claim 1, wherein: if an LDPC code generation matrix is set, and P is a K × (N-K) -dimensional dense quasi-cyclic matrix, the dense quasi-cyclic matrix P is as follows: g ═ I, P ], where I is the K × K identity matrix of LDPC.

6. The method of claim 5 for implementing LDPC coding hardware based on coding submatrix partitioning, wherein: the dense quasi-cyclic matrix P is shown below:

wherein, M represents the cyclic subarray forming the LDPC code check matrix, and M and n respectively represent the row number and the column number of the cyclic subarray.

7. The method of claim 6 for implementing LDPC coding hardware based on coding submatrix partitioning, wherein: l-order cyclic matrix M of check matrix P_i,jAs will be shown below, in the following,

wherein a represents each element of the cyclic sub-array, i 1, 2.. and m, j 1, 2.. and n; when the LDPC code is used for simulation, L is 14, m is 56, and n is 14.

8. The method of claim 1, wherein when the basic coding unit is coded, the coding starts from the ith 1 information bit and the jth 1 row of the cyclic sub-matrix, when the basic coding unit is coded, the ith information bit α is read from the ROM table, the data is stored in the coding shift register, the input bit information α is bit-expanded to the row vector with the same order L as the cyclic sub-matrix, and the bit information becomes the bit information after the expansion

Then, the bit information A and the value in the coding shift register are summed to obtain an intermediate vector B; and performing XOR on the result B of the AND and the median value of the check shift register to enable the result of the XOR to cover the current check shift register.

9. The LDPC coding hardware implementation method based on coding submatrix partitioning of claim 8, wherein: and after the result of the XOR covers the check shift register, judging whether a new subarray needs to be read again and stored in the coding register, if so, reading the new subarray from the ROM table, otherwise, circularly right-shifting the current coding register, continuing coding, repeating the process until all the coding subarrays participate in operation, and finishing output after all the basic coding units finish coding to obtain a code word information bit and a check bit.

10. The LDPC coding hardware implementation method based on coding submatrix partitioning of claim 1, wherein: when judging whether a new subarray needs to be read again, judging whether the shift frequency j of the register is smaller than the order L of the quasi-cyclic subarray, if the check bit j is smaller than the order L, shifting the value in the coding shift register by one bit to the right according to the cycle of a first row, feeding the value back to the step of inputting one-bit information, continuing to circulate downwards, and ending the program after obtaining a code word information bit and a check bit; otherwise, encoding the next information, i is i +1, encoding the next cyclic sub-array, at the moment, j is 1, then judging whether i is smaller than the number m of quasi-cyclic matrixes in each sub-array of the check matrix P, continuously reading out one data from the ROM table, storing the data in the encoding shift register, and continuously encoding until all cyclic sub-arrays finish checking.