CN111162083A - Semiconductor structure, three-dimensional memory and preparation method - Google Patents

Semiconductor structure, three-dimensional memory and preparation method Download PDF

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Publication number
CN111162083A
CN111162083A CN202010000511.9A CN202010000511A CN111162083A CN 111162083 A CN111162083 A CN 111162083A CN 202010000511 A CN202010000511 A CN 202010000511A CN 111162083 A CN111162083 A CN 111162083A
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connection
auxiliary
etching
area
region
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CN111162083B (en
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孙中旺
苏睿
周文犀
夏志良
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Abstract

The invention provides a semiconductor structure, a three-dimensional memory and respective preparation methods, wherein the preparation method of the semiconductor structure comprises the following steps: providing a semiconductor substrate, forming a laminated structure on the semiconductor substrate, wherein the laminated structure comprises a storage area and a connection area which are divided along the X direction, the connection area at least comprises a first connection subarea and a second connection subarea, carrying out preset etching on the laminated structure of the first connection subarea in preset layer number, then carrying out synchronous etching on the residual laminated structure of the first connection subarea, and carrying out synchronous etching on the laminated structure of the second connection subarea to obtain a step to be formed. The method adopts a process combining the preset etching (chop) and the synchronous etching (trim and etch), reduces the process difficulty of device preparation, reduces the number of masks, realizes the preparation of required steps by combining the etching in the X direction and the Y direction, cuts off the continuity of the steps in the Y direction, improves the stress and the expansion of materials, and improves the stability of the device.

Description

Semiconductor structure, three-dimensional memory and preparation method
Technical Field
The invention belongs to the field of integrated circuit manufacturing, and particularly relates to a semiconductor structure, a three-dimensional memory and a preparation method.
Background
A Flash Memory (Flash Memory) is a Non-volatile Memory (NVM), i.e. when power is turned off, the data stored in the Flash Memory will not disappear. Correspondingly, Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) are Volatile Memories (VM), and when the power is turned off, the stored data will disappear.
The different structures of Flash Memory cells (Memory cells) are classified into two types, namely NOR Flash and NAND Flash, wherein NOR Flash has a high reading speed but is slow in writing and erasing, the capacity of NOR Flash is much smaller than that of NAND Flash, and NORFlash can access any selected byte. The Embedded Flash (Flash) in a general IC is NORFlash, and is mainly used for storing the start-up, application program, operating system and XIP (eXecute-in-Place) codes in mobile devices and computers. NOR Flash has a much larger memory cell size than NAND Flash, and is inherently more reliable than NAND Flash due to the structure of the memory cell. NAND Flash has a somewhat slower read speed, but writes and erases data much faster than NOR Flash, and has an IC capacity of up to 128GB, but it cannot access specific bytes, but rather processes data in small blocks (pages). NAND Flash is commonly used as a mass data storage, and is used in gb (gigabyte) grade U disks (USB Flash Drive) and SSD Solid State disks (Solid State Drive/Disk) on the market.
However, the existing steps are distributed on a single side of the array region, and mostly are long steps (long ladder cases) which are sequentially increased or decreased, the steps are often divided into different partitions (two, three, and four partitions), for example, three partitions and increased in a certain direction (e.g., X direction) and consecutive steps in another direction (e.g., Y direction), and the X direction is perpendicular to the Y direction. Generally, after the step formation, oxide filling and chemical mechanical polishing are performed, and for example, since the step is continuous in the Y direction, the filling is also continuous. The filled oxide and the Step are made of different materials, and under the same heat treatment, the deformation is inconsistent, and the stress and expansion difference is caused, so that the structural performance of a core area (core) and a Step area (Stair-Step, SS for short) of the device is deteriorated, and even the device fails.
Therefore, it is necessary to provide a semiconductor structure, a three-dimensional memory and a fabrication method thereof to solve the above-mentioned problems in the prior art.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor structure, a three-dimensional memory and a method for fabricating the same, which are used to solve the problems of the prior art, such as difficulty in the step fabrication process, and deterioration and even failure of the device structure due to stress and expansion.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, the method comprising the steps of:
providing a semiconductor substrate, defining an X direction and a Y direction which are vertical to each other in a plane where the semiconductor substrate is located, and defining a Z direction in a direction which is vertical to the plane where the semiconductor substrate is located;
forming a laminated structure on the semiconductor substrate, wherein the laminated structure comprises a plurality of laminated material units stacked along the Z direction, the laminated structure comprises a storage area and a connection area which are divided along the X direction, and the connection area at least comprises a first connection subarea and a second connection subarea;
performing preset etching of preset levels on the part of the laminated structure located in the first connection partition, wherein the laminated structure remaining in the first connection partition after etching comprises a first etching area and a second etching area which are sequentially divided along the X direction, the part of the laminated structure located in the first etching area is etched, so that the bottom surface of the first etching area is lower than the bottom surface of the second etching area by at least one level, one level comprises a laminated material unit, the parts of the laminated structure located in the first etching area and the second etching area are synchronously etched to form a first stepped structure located in the first etching area and a second stepped structure located in the second etching area, the first stepped structure is gradually raised from the center outwards, and the second stepped structure is gradually raised from the center outwards, so that each stepped surface forms a plurality of continuous first leading-out steps with different levels, and the first leading-out steps of adjacent series have S levels, S is more than or equal to 1
The second connecting subarea comprises a third etching area and a fourth etching area which are sequentially divided along the X direction, the part of the laminated structure, which is positioned in the third etching area, is etched, so that the bottom surface of the third etching area is lower than the bottom surface of the fourth etching area by at least one level, the parts of the laminated structure, which are positioned in the third etching area and the fourth etching area, are synchronously etched, and a third step structure positioned in the third etching area and a fourth step structure positioned in the fourth etching area are formed, the third step structure is gradually increased from the center to the outside, the fourth step structure is gradually increased from the center to the outside, so that each step surface forms a plurality of continuous second leading-out steps with different levels, and the difference between the second leading-out steps of adjacent levels is S levels, the sum of the number of the second leading-out steps and the number of the first leading-out steps is equal to the number of the steps to be formed.
Optionally, the connection area further includes a third connection partition to an nth connection partition, where N is an integer greater than three, the portion of the stacked structure located between the third connection partition and the nth connection partition is subjected to preset etching of a preset number of levels, respectively, to obtain a plurality of continuous third leading-out steps of different levels to a plurality of continuous nth leading-out steps of different levels, the preset number of levels of the preset etching of each connection partition is different, the preset number of levels of the preset etching of the first connection partition is also different, a sum of the number of levels of the first leading-out step to the nth leading-out step is equal to the number of levels of the step to be formed, for each group of leading-out steps, in other groups of leading-out steps, a lowest step of one group of leading-out steps differs from a highest step of the group of leading-out steps by the number of S, and a highest step of another group of leading-out steps exists from the highest step of the other group of leading-out steps and a lowest step of the group of leading-out steps of the other groups of leading With the S levels in between.
Optionally, the sum of the number of steps of each group of leading-out steps and the number of preset levels of the preset etching of the corresponding connection partition is equal to the number of steps to be formed, and the number of steps from the first leading-out step to the nth leading-out step is equal.
Optionally, the step of forming the first step-structure and the second step-structure includes:
a) forming a mask layer with an opening on the first connection partition, wherein the opening divides the mask layer into a first mask positioned on the first etching area and a second mask positioned on the second etching area, and the opening exposes a preset distance of the edge of the first etching area close to the second etching area;
b) etching the first connection subarea based on the mask layer so as to form a first step in the first etching area, wherein the etching depth is M levels, and M is an integer greater than or equal to 1;
c) trimming the second mask to enable the second mask to retract the preset distance from one side close to the first mask to the direction far away from the first mask, and etching the first connecting partition based on the trimmed mask layer, wherein the etching depth is M levels, so that a second step is formed in the second etching area, and the first step descends the M levels;
d) trimming the first mask to enable the first mask to retract to the preset distance from one side close to the second mask to the direction far away from the second mask, etching the first connecting partition based on the trimmed mask layer, wherein the etching depth is M levels, so that a third step is formed in the first etching area, and the first step and the second step both descend by the M levels;
e) repeating the steps c) to d) at least once to increase the number of steps.
Optionally, the storage area includes a first storage partition and a second storage partition, and the first storage partition, the connection area, and the second storage partition are sequentially arranged.
Optionally, the connection area includes a first portion and a second portion, and the first portion, the storage area, and the second portion are sequentially disposed, where the first portion includes at least the first connection partition, and the second portion includes at least the second connection partition.
Optionally, the method further includes, after the performing the predetermined etching on the first connection partition and before the performing the etching on the first connection partition and the second connection partition in the X direction, a step of dividing the connection area into at least a first portion and a second portion in the X direction, and dividing the connection area into a first auxiliary area and a second auxiliary area which are symmetrical in the Y direction, where a portion of the first portion overlapping with the first auxiliary area or the second auxiliary area constitutes the first connection partition, a portion of the second portion overlapping with the first auxiliary area or the second auxiliary area constitutes the second connection partition, and a portion of the second portion opposing to the first connection partition in the Y direction constitutes the second connection auxiliary area, and further includes:
and synchronously etching at least the overlapped parts of the laminated structure, which are positioned in the first auxiliary area and the second auxiliary area, and the first part and the second part along the Y direction to form a first auxiliary stepped structure positioned in the first auxiliary area and a second auxiliary stepped structure positioned in the second auxiliary area, wherein the first auxiliary stepped structure is gradually reduced from the center outwards, and the second auxiliary stepped structure is gradually reduced from the center outwards.
Optionally, the first auxiliary step structure and the second auxiliary step structure have the same level number, and are equal to the level number of the bottom surface of the first etching area lower than the bottom surface of the second etching area and the level number of the bottom surface of the third etching area lower than the bottom surface of the fourth etching area; the laminated material unit comprises a laminated dielectric layer and a sacrificial layer.
Optionally, the step of forming the first auxiliary stair-step structure and the second auxiliary stair-step structure includes:
f) forming a photoresist layer on at least the first auxiliary area and the second auxiliary area and the overlapped part of the first part and the second part, and exposing a preset auxiliary interval of the edges of the first auxiliary area and the second auxiliary area;
g) performing K-level etching on the laminated structure based on the photoresist layer to form a first auxiliary step in the first auxiliary area and a second auxiliary step in the second auxiliary area, wherein K is an integer greater than or equal to 1;
h) trimming the photoresist layer to enable the photoresist layer to respectively retract the preset auxiliary spacing from two sides to the center in the Y direction, and etching the laminated structure based on the trimmed photoresist layer to form a third auxiliary step in the first auxiliary area and a fourth auxiliary step in the second auxiliary area, wherein the first auxiliary step and the second auxiliary step both descend to the K level;
i) repeating the step h) at least once to increase the number of the auxiliary steps.
Optionally, the connection area at least includes a first auxiliary area and a second auxiliary area along the Y direction, the first connection sub-area and the second connection sub-area are arranged in parallel along the X direction and have the same width along the Y direction, the first auxiliary area and the second auxiliary area are respectively arranged on two sides of the connection area along the Y direction, and the heights of the first auxiliary area and the second auxiliary area are equal to the height of the highest leading-out step in the first connection sub-area and the second connection sub-area.
The invention also provides a preparation method of the three-dimensional memory, which comprises the step of preparing the semiconductor structure by adopting the preparation method of the semiconductor structure in any scheme.
The invention also provides a semiconductor structure, wherein the semiconductor structure is preferably prepared by the preparation method of the semiconductor structure provided by the invention, and can be prepared by other methods, and the semiconductor structure comprises:
the semiconductor device comprises a semiconductor substrate, a first substrate and a second substrate, wherein the plane of the semiconductor substrate is defined with an X direction and a Y direction which are vertical to each other, and the direction vertical to the plane of the semiconductor substrate is defined with a Z direction;
the laminated structure comprises a plurality of laminated material units stacked along the Z direction, the laminated structure comprises a storage area and a connection area which are divided along the X direction, and the connection area at least comprises a first connection subarea and a second connection subarea;
the laminated structure of the first connecting subarea is provided with a first stepped structure and a second stepped structure which are arranged along the Z direction, the first stepped structure is gradually raised from the center to the outside, the second stepped structure is gradually raised from the center to the outside, so that each stepped surface forms a plurality of continuous first leading-out steps with different levels, wherein the bottom surface of the first stepped structure is less than the bottom surface of the second stepped structure by at least one level, one level comprises one laminated material unit, the difference S between the first leading-out steps of adjacent levels is S, and S is an integer greater than or equal to 1;
the laminated structure of the second connecting subarea is provided with a third stepped structure and a fourth stepped structure which are arranged along the Z direction, the third stepped structure gradually rises from the center to the outside, the fourth stepped structure gradually rises from the center to the outside, so that each step surface forms a plurality of continuous second leading-out steps with different levels, the difference between the second leading-out steps of adjacent levels is S levels, wherein the sum of the levels of the second leading-out steps and the levels of the first leading-out steps is equal to the level of the step to be formed.
Optionally, the connection area further includes a third connection partition to an nth connection partition, where N is an integer greater than three, where each connection partition correspondingly includes a plurality of consecutive third leading-out steps of different levels to a plurality of consecutive nth leading-out steps of different levels, where a sum of the levels of the first leading-out step to the nth leading-out step is equal to the level of the step to be formed, and for each group of leading-out steps, in other groups of leading-out steps, a lowest level step in one group of leading-out steps differs by S levels from a highest level step in the group of leading-out steps, and a highest level step in another group of leading-out steps differs by S levels from a lowest level step in the group of leading-out steps.
Optionally, the number of the first lead-out step is equal to the number of the nth lead-out step; the laminated material unit comprises a dielectric layer and a grid conducting layer which are laminated.
Optionally, the storage area includes a first storage partition and a second storage partition, and the first storage partition, the connection area, and the second storage partition are sequentially arranged.
Optionally, the connection area includes a first portion and a second portion, and the first portion, the storage area, and the second portion are sequentially disposed, where the first portion includes at least the first connection partition, and the second portion includes at least the second connection partition.
Optionally, the connection area is divided into at least a first portion and a second portion along the X direction, and is divided into a first auxiliary area and a second auxiliary area which are symmetrical along the Y direction, a portion of the first portion overlapping with the first auxiliary area or the second auxiliary area constitutes the first connection sub-area, a portion of the second portion overlapping with the first auxiliary area or the second auxiliary area constitutes the second connection sub-area, a portion opposite to the first connection sub-area along the Y direction constitutes a first connection auxiliary area, and a portion opposite to the second connection sub-area along the Y direction constitutes a second connection auxiliary area, wherein:
the laminated structure of the first auxiliary area is formed with a first auxiliary stepped structure arranged along the Z direction, the laminated structure of the second auxiliary area is formed with a plurality of layers of second auxiliary stepped structures arranged along the Z direction, the first auxiliary stepped structure is gradually reduced from the center outwards, and the second auxiliary stepped structure is gradually reduced from the center outwards.
Optionally, the first auxiliary stair-step structure and the second auxiliary stair-step structure have the same number of levels, and the number of levels of the bottom surface of the first stair-step structure is equal to the number of levels of the bottom surface of the second stair-step structure which are lower than the number of levels of the bottom surface of the third stair-step structure which is lower than the number of levels of the bottom surface of the fourth stair-step structure; the step surfaces of adjacent levels in the steps to be formed have a difference of one level.
Optionally, the connection area at least includes a first auxiliary area and a second auxiliary area along the Y direction, the first connection sub-area and the second connection sub-area are arranged in parallel along the X direction and have the same width along the Y direction, the first auxiliary area and the second auxiliary area are respectively arranged on two sides of the connection area along the Y direction, and the heights of the first auxiliary area and the second auxiliary area are equal to the height of the highest leading-out step in the first connection sub-area and the second connection sub-area.
The invention also provides a three-dimensional memory structure comprising a semiconductor structure as defined in any of the above aspects.
As described above, the semiconductor structure and the method for manufacturing the same, and the three-dimensional memory structure and the method for manufacturing the same according to the present invention adopt a process combining the preset etching (chop) and the synchronous etching (trim and etch processes alternately perform on the mask layer), reduce the process difficulty of device manufacturing, reduce the number of mask plates, realize the manufacturing of steps required by combining the etching in the X direction and the Y direction, cut off the continuity of the steps in the Y direction, also cut off the continuity of the subsequent filling of materials such as oxides on the steps, improve the stress and expansion of the materials, improve the stability of the device, divide the steps to be formed into at least two parts to be respectively formed, dispose the connection region in the middle or both sides of the storage region, can realize the flexible arrangement of the steps, reduce the process difficulty of manufacturing, and shorten the length of word lines, the control capability of the word line is enhanced, and the time delay is reduced.
Drawings
FIG. 1 is a process flow diagram illustrating the fabrication of a semiconductor structure according to the present invention.
Fig. 2 is a schematic structural diagram illustrating a second connection partition according to a first embodiment of the present invention.
Fig. 3 is a schematic diagram illustrating the formation of a first step according to a first embodiment of the invention.
Fig. 4 is a schematic diagram illustrating the formation of a second step in accordance with a first embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating the formation of a third step in accordance with a first embodiment of the present invention.
Fig. 6 is a schematic diagram illustrating the formation of a fourth step according to a first embodiment of the invention.
Fig. 7 is a schematic diagram illustrating a first connection partition and a surrounding stacked structure partition according to an embodiment of the invention.
Fig. 8 is a schematic structural diagram illustrating a first connection partition after performing a predetermined etching process according to a first embodiment of the present invention.
Fig. 9 is a diagram illustrating a first step formed by performing Y-direction etching on the first connection partition according to a first embodiment of the invention.
Fig. 10 is a diagram illustrating a first connection partition being etched in the Y direction to form a second step according to a first embodiment of the invention.
Fig. 11 is a diagram illustrating a first connection partition being etched in the Y direction to form a third step according to a first embodiment of the invention.
Fig. 12 is a schematic diagram illustrating a step structure formed by performing Y-direction etching on the second connection partition according to a first embodiment of the invention.
Fig. 13 shows a step distribution diagram illustrating the formation of 144 steps according to an example of the first embodiment of the present invention.
Fig. 14 is a schematic view showing a cross-sectional structure of the step formed in the example of fig. 13.
Fig. 15 shows a step distribution diagram for forming 144 steps as an example in the second embodiment of the present invention.
Fig. 16 is a schematic diagram illustrating an example of an arrangement of a connection area and a storage area in an embodiment of the invention.
Fig. 17 is a schematic diagram illustrating another example of the arrangement of the connection areas and the storage areas in the first embodiment of the present invention.
Description of the element reference numerals
100 semiconductor substrate
200 laminated structure
201a, 202a, 203a, 204a, 205a, 206a, 207a, 208a dielectric layer
201b, 202b, 203b, 204b, 205b, 206b, 207b, 208b sacrificial layer
200a third etching area
200b fourth etch region
300 mask layer
301 first mask
302 second mask
400a first connection zone surrounding a stack structure
400b first connection zone
500A photoresist layer
A1, A2, A3, A4, B1, B2, B3, C1, C2, C3, D1, and steps
D2、D3、E1、E2、E3
701. 601 first connection zone
702. 602 second connection partition
703. 603 third linking partition
800 attachment area
801 first connection zone
802 second connection partition
803 third connection partition
804 first memory partition
805 second memory partition
900 memory area
901 first connection part
902 second connection portion
903 first connection partition
904 second connected partition
905 third connection partition
S1-S4
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
The first embodiment is as follows:
as shown in fig. 1, the present embodiment provides a method for manufacturing a semiconductor structure, the method comprising the steps of:
providing a semiconductor substrate, defining an X direction and a Y direction which are vertical to each other in a plane where the semiconductor substrate is located, and defining a Z direction in a direction which is vertical to the plane where the semiconductor substrate is located;
forming a laminated structure on the semiconductor substrate, wherein the laminated structure comprises a plurality of laminated material units stacked along the Z direction, the laminated structure comprises a storage area and a connection area which are divided along the X direction, and the connection area at least comprises a first connection subarea and a second connection subarea;
performing preset etching of preset levels on the part of the laminated structure located in the first connection partition, wherein the laminated structure remaining in the first connection partition after etching comprises a first etching area and a second etching area which are sequentially divided along the X direction, the part of the laminated structure located in the first etching area is etched, so that the bottom surface of the first etching area is lower than the bottom surface of the second etching area by at least one level, one level comprises a laminated material unit, the parts of the laminated structure located in the first etching area and the second etching area are synchronously etched to form a first stepped structure located in the first etching area and a second stepped structure located in the second etching area, the first stepped structure is gradually raised from the center outwards, and the second stepped structure is gradually raised from the center outwards, so that each stepped surface forms a plurality of continuous first leading-out steps with different levels, the difference between the first leading-out steps of adjacent series is S levels, and S is more than or equal to 1;
the second connecting subarea comprises a third etching area and a fourth etching area which are sequentially divided along the X direction, the part of the laminated structure, which is positioned in the third etching area, is etched, the bottom surface of the third etching area is lower than the bottom surface of the fourth etching area by at least one level, the parts of the laminated structure, which are positioned in the third etching area and the fourth etching area, are synchronously etched, a third step structure positioned in the third etching area and a fourth step structure positioned in the fourth etching area are formed, the third step structure is gradually increased from the center to the outside, the fourth step structure is gradually increased from the center to the outside, so that each step surface forms a plurality of continuous second leading-out steps with different levels, and the second leading-out steps with adjacent levels are different by the S levels, wherein the sum of the levels of the second leading-out steps and the levels of the first leading-out steps is equal to the level of the step to be formed, the highest-level step of the first lead-out steps and the lowest-level step of the second lead-out steps differ by the S levels.
The method for fabricating the semiconductor structure of the present invention will be described in detail with reference to the accompanying drawings.
As shown in S1 of fig. 1 and fig. 2, a semiconductor substrate 100 is provided, an X direction and a Y direction perpendicular to each other are defined in a plane of the semiconductor substrate 100, and a Z direction is defined in a direction perpendicular to the plane of the semiconductor substrate 100, wherein only the X direction and the Z direction are shown in fig. 2, and the X direction, the Y direction, and the Z direction may form a three-dimensional coordinate system. In addition, the semiconductor substrate 100 includes, but is not limited to, a semiconductor substrate of Si, Ge, SiGe, SiC, a III-V compound, silicon-on-insulator (SOI), or the like.
As shown in S1 in fig. 1 and fig. 2, a stacked structure 200 is formed on the semiconductor substrate 100, the stacked structure 200 includes a plurality of stacked material units stacked in the Z direction, the stacked structure 200 includes a storage region and a connection region divided in the X direction, and the connection region includes at least a first connection region and a second connection region, where fig. 2 is merely an example, and other layer structures may be disposed between the semiconductor substrate 100 and the stacked structure 200, and the scope of the present invention should not be limited too.
For the stacked material unit, in an example, the stacked material unit may be a dielectric layer and a sacrificial layer alternately stacked in the Z direction, and as an example, the dielectric layer and the sacrificial layer are alternately deposited on the semiconductor substrate by using a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method, and the like, for example, 8 levels, 16 levels, 32 levels, 64 levels, 96 levels, 128 levels, 136 levels, 144 levels, and the like, wherein one level includes one stacked material unit, that is, one level includes a pair of stacked dielectric layers and sacrificial layers. In this embodiment, the dielectric layers 201a, the sacrificial layers 201b, the dielectric layers 202a, the sacrificial layers 202b, the dielectric layers 203a, the sacrificial layers 203b, the dielectric layers 204a, the sacrificial layers 204b, the dielectric layers 205a, the sacrificial layers 205b, the dielectric layers 206a, the sacrificial layers 206b, the dielectric layers 207a, the sacrificial layers 207b, the dielectric layers 208a, and the sacrificial layers 208b are alternately stacked to form 8 levels (tier).
In addition, in the division of the stacked structure 200 along the X direction, the connection area at least includes two connection sub-areas, namely, a first connection sub-area and a second connection sub-area, and it should be noted here that the etching of the first connection sub-area and the second connection sub-area by different methods may be considered to represent two connection sub-areas. Of course, the connection area may further include three or more connection partitions, which may be named as a third connection partition and an nth connection partition, where N is an integer greater than or equal to 3. In an example, steps are formed in each connection partition, and each step is connected with a storage region of the device structure, and further, can be electrically connected with a gate in the storage region, so that electrical leading-out of the gate is realized based on the subsequently formed steps.
The following is a continued description of the method for fabricating a semiconductor structure based on steps S3 and S4, taking two connection partitions as an example. For the description of the present embodiment, it is to be noted that fig. 1 shows a process flow of the semiconductor structure manufacturing method of the present invention; FIGS. 2-6 are schematic diagrams showing the structure of an etching process for etching in the X direction of a connecting partition; FIGS. 7-8 are schematic structural views of another connection partition after the predetermined etching; FIGS. 9-11 are schematic views showing the structure of an etching process for performing Y-direction etching on a linking sub-area of the kind shown in FIGS. 7-8; FIG. 12 is a schematic diagram showing a structure of an etching process for performing Y-direction etching on a connection partition of the kind shown in FIGS. 2-6; FIGS. 13 to 15 are schematic views showing steps obtained by etching the differently distributed connection regions in the X direction and the Y direction at the same time according to the present invention, wherein FIG. 14 is a schematic view showing a cross-sectional structure of the step formed in the structure of FIG. 13; fig. 16-17 show schematic diagrams of different divisions, i.e. distributions, of storage areas and connection areas.
As shown in fig. 2 to 8, the schematic diagram of the X-direction etching of the stacked structure 200 in the first connection sub-area and the second connection sub-area is shown, wherein the difference of the etching process for the first connection sub-area and the second connection sub-area is that the first connection sub-area is first etched by a predetermined etching (chop), i.e. the portion of the stacked structure in the first connection sub-area is first etched by a predetermined number of layers, wherein one layer includes one stacked material unit, i.e. in one example, one layer includes a pair of stacked dielectric layers and sacrificial layers, and thereafter, the processes for etching the first connection sub-area and the second connection sub-area are similar.
For convenience of illustration, the second connection partition without the preset etching is described as an example below:
first, as shown in fig. 2, the second connection division is divided in the X direction, and the second connection division includes a third etching region 200a and a fourth etching region 200b which are sequentially divided in the X direction, and preferably, the third etching region 200a is adjacent to the fourth etching region 200b, for example, the second connection division may be divided in a direction extending from the X axis of the three-dimensional coordinate system. Further preferably, the lengths of the third etching region 200a and the fourth etching region 200b in the X direction are equal.
Next, referring to fig. 3, the third etching region 200a is etched such that the bottom surface of the third etching region 200a is lower than the bottom surface of the fourth etching region 200b by at least one level. Wherein the fact that the bottom surface of the third etching region 200a is lower than the bottom surface of the fourth etching region 200b by at least one level means that: based on this etching, the lowest surface (the step surface of the lowest step) of the stepped structure formed by the third etching region 200a is lower than the lowest surface (the step surface of the lowest step) of the stepped structure formed by the fourth etching region 200b by at least one level. Here, in this etching, the number of etching steps for the third etching region 200a is the number of etching steps for the third etching region 200a lower than the bottom surface of the fourth etching region 200 b. In addition, since a step structure needs to be formed subsequently, this etching is not the whole etching of the third etching region 200 a.
Continuing with fig. 4-6, portions of the stacked structure 200 in the third etching region 200a and the fourth etching region 200b are etched simultaneously to form a third step structure in the third etching region 200a and a fourth step structure in the fourth etching region 200b, the third step structure is gradually increased from the center to the outside, the fourth step structure is gradually increased from the center to the outside, the center here can be considered as the interface of the contact of the third etch zone with the fourth etch zone, so that each step surface forms a plurality of continuous second leading-out steps with different levels, the second leading-out steps with adjacent levels have the difference of S levels, S is an integer more than or equal to 1, and forming the third step structure and the fourth step structure after the etching of the step to obtain steps with required levels.
In a specific example etching process, as shown in fig. 3, the bottom surface of the third etching region 200a is shown to be lower than the bottom surface of the fourth etching region 200b by 2 levels. Wherein, the etching step comprises the following steps: forming a mask layer 300 with an opening on the second connection partition, wherein the opening divides the mask layer into a first mask 301 located on the third etching region 200a and a second mask 302 located on the fourth etching region 200b, and the opening exposes a preset distance d between the third etching region 200a and the edge of the fourth etching region 200b, wherein the opening defines a step surface of a bottom step of the stepped structure formed in the third etching region 200a, i.e., the bottom surface, and etching is performed on the second connection partition based on the mask layer 300, so that a first step a1 (bottom step) is formed in the third etching region 200a, wherein the etching depth is M levels, M is an integer greater than or equal to 1, and M is 2.
Next, in this specific example, as shown in fig. 4, trimming the second mask 302 to retract the second mask 302 from the side close to the first mask 301 to the direction away from the first mask 301 by the preset distance d, and etching the second connection partition based on the trimmed mask layer 300, wherein the etching depth is the M levels, where M is selected to be 2 levels, and is selected to be consistent with the depth of the first etching, so as to form a second step a2 in the fourth etching area, and the first step a1 is lowered by the M levels, it should be noted that, in the etching of the step shown in fig. 3, a first step a1 is formed, in this time, the first step a1 is simultaneously etched and lowered by the M levels, the actually exposed material layer is changed, but the opposite levels are not changed due to the synchronous etching, for convenience of description, the first step a1 is still used for description in the subsequent etching, and other steps are the same; then, as shown in fig. 5, trimming the first mask 301 to retract the first mask 301 from a side close to the second mask 302 to a direction away from the second mask 302 by the predetermined distance, and etching the second connection partition based on the trimmed mask layer 300 to the M levels, so as to form a third step A3 in the third etching region, and the first step a1 and the second step a2 are both lowered by the M levels; then, as shown in fig. 6, the above steps are repeated at least once to increase the number of steps, where fig. 6 shows that the second mask 302 is repeatedly trimmed once to form a fourth step a4, and of course, a greater number of steps may be formed subsequently to obtain a third step structure and a fourth step structure.
It can be seen that the bottommost surface of the third stair-step structure is M levels lower than the bottommost surface of the fourth stair-step structure, i.e., the etching depth of the first etching, in the above example, the etching depth after trimming the first mask 301 and the second mask 302 is also selected to be the M levels, and, of course, in other examples, the number of levels of the subsequent etch may be selected based on the actual circumstances, and further, fig. 6 shows that in order to obtain 4 levels of the second lead-out steps, the second lead-out steps of each adjacent level are different by 2 levels, which depends on the etching depth and can be selected according to actual requirements, in one example, the laminated structure of the second connection subarea is etched only in the X direction, the depth of each etching is selected to be consistent, and all the etching depths are M levels, and the height difference between each M level and the step of the adjacent level is consistent with S level selections.
In addition, referring to the above description of the etching process of the second connection sub-area and fig. 7-8, the etching of the first connection sub-area will be described, first, as shown in fig. 7, the first connection sub-area 400b and the adjacent stacked structure (i.e., the stacked structure 400a around the first connection sub-area) are shown, and then, as shown in fig. 8, the predetermined etching (chop) is performed on the first connection sub-area 400b, wherein the predetermined number of levels for performing the predetermined etching is selected according to actual conditions. Then, dividing the remaining part of the first connection subarea after the preset etching by analogy with the division of the etching area of the second connection subarea, wherein the remaining part of the first connection subarea after the preset etching comprises a first etching area and a second etching area which are sequentially divided along the X direction, and the remaining laminated structure of the first connection subarea can be directly called as the first connection subarea for convenience of description because the first connection subarea is etched, the part of the laminated structure positioned in the first etching area is etched, so that the bottom surface of the first etching area is lower than the bottom surface of the second etching area by at least one level, wherein one level comprises one laminated material unit, the parts of the laminated structure positioned in the first etching area and the second etching area are synchronously etched, and a first stepped structure positioned in the first etching area and a second stepped structure positioned in the second etching area are formed, the first step structure is gradually raised from the center to the outside, the second step structure is gradually raised from the center to the outside, so that each step surface forms a plurality of continuous first leading-out steps with different levels, the difference between the first leading-out steps with adjacent levels is S levels, and S is larger than or equal to 1. The etching of the first connection partition may refer to etching of the second connection partition, and as an example, the step of forming the first stepped structure and the second stepped structure includes:
a) forming a mask layer with an opening on the first connection partition, wherein the opening divides the mask layer into a first mask positioned on the first etching area and a second mask positioned on the second etching area, and the opening exposes a preset distance of the edge of the first etching area close to the second etching area;
b) etching the first connection subarea based on the mask layer so as to form a first step in the first etching area, wherein the etching depth is M levels, and M is an integer greater than or equal to 1;
c) trimming the second mask to enable the second mask to retract the preset distance from one side close to the first mask to the direction far away from the first mask, and etching the first connecting partition based on the trimmed mask layer, wherein the etching depth is M levels, so that a second step is formed in the second etching area, and the first step descends the M levels;
d) trimming the first mask to enable the first mask to retract to the preset distance from one side close to the second mask to the direction far away from the second mask, etching the first connecting partition based on the trimmed mask layer, wherein the etching depth is M levels, so that a third step is formed in the first etching area, and the first step and the second step both descend by the M levels;
e) repeating the steps c) to d) at least once to increase the number of steps.
Based on the etching of the stacked structure, a sum of the number of the second leading-out steps and the number of the first leading-out steps is equal to the number of the steps to be formed, that is, if 36 steps are required to be formed, 18 steps may be formed based on the first connection partition, 18 steps may be formed based on the second connection partition, that is, the first connection partition forms the 1 st step to the 18 th step, the second connection partition forms the 19 th step to the 36 th step, and the corresponding partition subjected to the preset etching forms a lower number of steps, or 32 steps may be formed based on the first connection partition, and 4 steps may be formed based on the second connection partition, which may specifically be set according to an actual setting. Through the scheme, the steps to be formed can be divided into at least two parts to be formed respectively, so that the steps can be flexibly arranged, the preparation process difficulty is reduced, the use of a mask plate is reduced, the continuous step structure is cut off, and the stress and material expansion are improved. In an example, the difference between the highest step in the first lead-out steps and the lowest step in the second lead-out steps is S levels, that is, the difference between any two adjacent levels of steps in the steps to be formed is equal, so that the steps distributed uniformly in height can be obtained, and the continuous and uniform integral steps can be obtained.
As an example, the connection area further includes a third connection partition to an nth connection partition, where N is an integer greater than three, where the portion of the stacked structure located between the third connection partition and the nth connection partition is subjected to preset etching of a preset number of levels, so as to obtain a plurality of continuous third leading-out steps of different levels to a plurality of continuous nth leading-out steps of different levels, where the preset number of levels of the preset etching of each connection partition is different from the preset number of levels of the preset etching of the first connection partition, and a sum of the number of levels of the first leading-out step to the nth leading-out step is equal to the number of levels of the step to be formed. That is to say, when the connection area is divided, the connection area includes three or more than three partitions, that is, the N partitions, where 1 partition is not subjected to the preset etching (chop), the other partitions are subjected to the preset etching, the number of the layers of the preset etching performed by each partition is different, the stacked structure below the connection area after the preset etching is etched according to the etching manner of the second connection partition, and according to the above scheme, at least three groups of stepped structures are formed in the connection area by forming at least three connection partitions, so as to obtain the required steps.
As an example, the sum of the number of steps of each group of lead-out steps and the number of preset levels of the preset etching of the corresponding connection partition is equal to the number of steps to be formed, the number of steps of the first lead-out step is equal to the number of steps of the nth lead-out step, and for each group of lead-out steps, the difference between the lowest step of one group of lead-out steps and the highest step of the group of lead-out steps is S levels, and the difference between the highest step of the other group of lead-out steps and the lowest step of the group of lead-out steps is S levels. In the example, the sum of the number of steps of each group of the leading-out steps and the number of preset levels of the preset etching of the corresponding connection partition is equal to the number of steps to be formed, that is, the number of levels chop of the group is the number of steps of leading-out steps formed by other groups, and based on the steps to be formed in the example, the groups form the steps with equal height difference, that is, the number of levels of difference between adjacent steps is the same, and 1 level is selected in the example.
As shown in fig. 9 to 12, the stacked structure 200 is further etched in the Y direction, so that a required step can be formed together based on the etching in the Y direction and the etching in the X direction, in an example, first, the connection partition that needs to be subjected to the preset etching is subjected to the preset etching (chop) in the X direction, then, the stacked structure 200 in the Y direction is etched, and then, the stacked structure of each connection partition is subjected to the synchronous etching similar to the second connection partition in the X direction to form a stepped structure, so as to obtain a step, and the etching in the Y direction is specifically described below with reference to the drawings:
first, the connecting region is divided into at least a first portion and a second portion along the X direction, and divided into a first auxiliary region 501 and a second auxiliary region 502 which are symmetrical along the Y direction, a portion of the first portion overlapping the first auxiliary area or the second auxiliary area constitutes the first connection partition, a portion of the second portion overlapping with the first auxiliary area or the second auxiliary area constitutes the second connection partition, and a portion opposed to the first connection section in the Y direction constitutes a first connection auxiliary area, and a portion opposed to the second connection section in the Y direction constitutes a second connection auxiliary area, after the pre-etching (chop) is performed on the first connection partition and before the etching in the X direction is performed on the first connection partition and the second connection partition, the method further includes the steps of:
and synchronously etching at least the parts of the laminated structure, which are located in the first auxiliary area 501 and the second auxiliary area 502 and are overlapped with the first part and the second part, along the Y direction to form a first auxiliary stepped structure located in the first auxiliary area and a second auxiliary stepped structure located in the second auxiliary area, wherein the first auxiliary stepped structure is gradually reduced from the center outwards, the second auxiliary stepped structure is gradually reduced from the center outwards, and the center can be an interface where the first auxiliary area 501 and the second auxiliary area 502 are in contact, and the step cuts off the continuity of the steps in the Y direction.
In an exemplary etching, the step of forming the first auxiliary step structure and the second auxiliary step structure includes:
first, as shown in fig. 9, a photoresist layer 500 is formed at least on the overlapping portions of the first auxiliary region 501 and the second auxiliary region 502 and the first portion and the second portion, and a predetermined auxiliary distance between the edges of the first auxiliary region 501 and the second auxiliary region 502 is exposed; then, K-level etching is performed on the stacked structure 200 based on the photoresist layer 500 to form a first auxiliary step C1 in the first auxiliary region 501 and a second auxiliary step B1 in the second auxiliary region 502, where K is an integer greater than or equal to 1;
as shown in fig. 10, trimming the photoresist layer 500 to make the photoresist layer 500 retract from two sides to the center along the Y direction by the predetermined auxiliary pitch, and etching the stacked structure 200 based on the trimmed photoresist layer 500 to form a third auxiliary step C2 in the first auxiliary region 501 and a fourth auxiliary step B2 in the second auxiliary region 502, wherein the first auxiliary step C1 and the second auxiliary step B2 both fall down by the K level;
in addition, the step h) can be repeated at least once, so that the number of the auxiliary steps is increased.
Referring to fig. 11, after removing the photoresist layer 500, a fifth assistant step C3 is formed in the first assistant region 501, and a sixth assistant step B3 is formed in the second assistant region 502, so as to form a structure having 6 steps along the Y direction. Fig. 9 to 11 show an example in which the first connection sub-region subjected to the preset etching (chop) is etched in the Y direction, and fig. 10 shows an example in which the second connection sub-region not subjected to the preset etching (chop) is etched in the Y direction, forming steps D1, D2, D3, E1, E2, and E3.
The invention adopts the combined process of the preset etching (chop) and the synchronous etching (trim and etch, the process of alternately trimming and etching the mask layers), reduces the process difficulty of device preparation and the number of mask plates, wherein, the difficulty is high when the process similar to the synchronous etching is simply carried out for etching to form the required steps, and the number of the mask plates (masks) required when the process similar to the preset etching is simply carried out for etching to form the required steps is more.
As an example, the first auxiliary step structure and the second auxiliary step structure have the same level, and the level is equal to the level of the bottom surface of the first etching region lower than the bottom surface of the second etching region, and the level of the bottom surface of the third etching region lower than the bottom surface of the fourth etching region.
Specifically, in this example, the stacked structure is etched in the X direction and the Y direction, where, as shown in fig. 13, a first step structure formed by a first connecting partition 601 is taken as an example, and the first auxiliary step structure is formed symmetrically in the Y direction, it can be seen that, in the Y direction, the number of steps of the first auxiliary step structure is 3, in this example, in the process of etching the first connecting partition 601 in the X direction, the first etching is performed for the first time so that the first etching region is lower than the second etching region by 3 steps, and then, when the first etching region and the second etching region are simultaneously etched to form the first step structure and the second step structure, the depth of each etching is 3 steps, so that a plurality of independent steps are obtained, and each step of the adjacent steps is one step apart from each other, that is, the number of steps to be formed in the Y direction is determined by performing the first etching such that the bottom surface of the first etching region is lower than the bottom surface of the second etching region.
As shown in fig. 13 to 14, an example is provided, in which 144 steps are required to be formed, wherein etching is performed by dividing the structure into three regions, that is, a first connection region 601, a second connection region 602, and a third connection region 603, wherein during etching, a predetermined etching is performed on the corresponding stacked structure above the first connection region 601 and the third connection region 603, 96 steps (chop 96pa s) are etched away at a position corresponding to the first connection region 601, 48 steps are finally formed in the first connection region 601, steps from 1 step to 48 step are formed, 48 steps (chop48 pa s) are etched away at a position corresponding to the third connection region 603, steps from 48 step to 49 step to 96 step are finally formed in the third connection region 603, and further, the predetermined etching is not performed on the second connection region 602, and steps from 48 step are formed in a subsequent process, forming steps from 97 th level to 144 th level; then, the first connecting subarea, the third connecting subarea and the second connecting subarea which are formed after etching are etched by adopting the embodiment of the invention, the etching is firstly carried out in the Y direction, three symmetrical steps are formed on each auxiliary subarea and sequentially decreased from the center to the outside, a mountain-shaped structure is formed, namely, 48 steps of each connecting subarea are divided into three rows for preparation; then, each connection division is etched in an X-square shape, wherein fig. 14 is a cross-sectional view of the innermost layer after the first connection division is etched in the X-direction, and the left side in the figure also shows a cross-sectional view of the first connection division at a symmetrical position in the Y-direction, and finally, a required number of steps are formed in each area. Referring to fig. 13 again, steps are formed at symmetrical positions and around each connection partition, and actually, the uppermost three-level step is formed, so that WL continuity and isolation of the filling oxide can be realized.
In an example, when two or more connection partitions are formed, the connectable partitions may be alternately arranged left and right in the Y direction, such as the arrangement in fig. 13, thereby facilitating the layout of the device structure.
Referring to fig. 16, in an example, the storage area includes a first storage partition 804 and a second storage partition 805, and the first storage partition 804, the connection area 800, and the second storage partition 805 are sequentially arranged. In this example, the connection region is provided between two portions of the memory region, so that the length of the word line can be shortened, the controllability of the word line is enhanced, and the delay time is reduced, and in this example, the first connection section 801, the second connection section 802, and the third connection section 803 are provided in the connection region to form a desired step in each connection section. In this example, the memory area is divided into two parts, which are respectively disposed at both sides of the connection area, so that the length of the word line can be shortened, the control capability of the word line is enhanced, and the delay time is reduced.
Referring to fig. 17, the connection area includes a first connection portion 901 and a second connection portion 902, and the first connection portion 901, the storage area 900 and the second connection portion 902 are sequentially disposed, where the first connection portion 901 at least includes the first connection partition 903, and the second connection portion 902 at least includes the second connection partition 904. In this example, the connection partition is divided into two parts, which are respectively disposed on two sides of the storage region 900, so that the length of the word line can be shortened, the control capability of the word line is enhanced, and the delay time is reduced.
According to the scheme, the steps to be formed are divided into at least two parts to be formed respectively, the connecting areas are arranged in the middle or on two sides of the storage area, flexible arrangement of the steps can be achieved, the manufacturing process difficulty is reduced, the length of the word line can be shortened, the control capability of the word line is enhanced, the time delay is reduced, compared with single-ended power-up, the step is transmitted to the other side of the storage area through WL, if the step is placed in the middle of the storage area or the step is divided into two parts to be arranged on two sides of the storage area, the word line can be shortened, the control capability is enhanced, and the time delay is reduced.
Example two:
as shown in fig. 15, another embodiment is provided, in which the connection area includes at least a first auxiliary area and a second auxiliary area along the Y direction, the first connection sub-area and the second connection sub-area are arranged in parallel along the X direction and have the same width along the Y direction, the first auxiliary area and the second auxiliary area are respectively arranged on both sides of the connection area along the Y direction, and the first auxiliary area and the second auxiliary area have the same height as the highest extraction step in the first connection sub-area and the second connection sub-area, and in an alternative example, the connection area includes a first connection sub-area 701, a second connection sub-area 702, and a third connection sub-area 703, in this example, the connection sub-areas are arranged in parallel along the X direction, and the position where the predetermined etching (chop) is performed is different from that in the first embodiment, and the other manufacturing process is referred to the first embodiment, in this example, the first auxiliary area and the second auxiliary area do not need to be etched to directly form the last step, and when the area in the frame line is subjected to the preset etching in the Y direction, the etching width of each step can be selected according to the actual requirement, in this example, the width of the 1 st step in the Y direction is wider and can be selected to be twice as wide as other steps, not limited to this, and fig. 5 shows the distribution of the steps obtained in this embodiment by obtaining the 144 steps in fig. 13.
Example three:
as shown in fig. 13 to 17 and referring to fig. 1 to 12, this embodiment provides a semiconductor structure, wherein the semiconductor structure is preferably prepared by any one of the preparation methods of the first embodiment and the second embodiment, and of course, may also be prepared by other methods known to those skilled in the art, and the description of the structure related to the semiconductor structure in this embodiment may refer to the description of the first embodiment and the second embodiment, which is not repeated herein, and the semiconductor structure includes:
a semiconductor substrate 100, wherein an X direction and a Y direction which are perpendicular to each other are defined in a plane in which the semiconductor substrate 100 is located, and a Z direction is defined in a direction perpendicular to the plane in which the semiconductor substrate 100 is located;
a stacked structure 200 including a plurality of stacked material units stacked in the Z direction, the stacked structure including a storage region and a connection region divided in the X direction, the connection region including at least a first connection partition and a second connection partition;
the laminated structure of the first connecting subarea is provided with a first stepped structure and a second stepped structure which are arranged along the Z direction, the first stepped structure is gradually raised from the center to the outside, the second stepped structure is gradually raised from the center to the outside, so that each stepped surface forms a plurality of continuous first leading-out steps with different levels, wherein the bottom surface of the first stepped structure is less than the bottom surface of the second stepped structure by at least one level, one level comprises one laminated material unit, the difference S between the first leading-out steps of adjacent levels is S, and S is an integer greater than or equal to 1;
the laminated structure of the second connecting subarea is provided with a third stepped structure and a fourth stepped structure which are arranged along the Z direction, the third stepped structure gradually rises from the center to the outside, the fourth stepped structure gradually rises from the center to the outside, so that each step surface forms a plurality of continuous second leading-out steps with different levels, and the difference between the second leading-out steps of adjacent levels is S levels, wherein the sum of the levels of the second leading-out steps and the levels of the first leading-out steps is equal to the level of the steps to be formed, and the difference between the highest level step of the first leading-out steps and the lowest level step of the second leading-out steps is S levels.
As an example, the connection area further includes a third connection partition to an nth connection partition, where N is an integer greater than three, where each connection partition correspondingly includes a plurality of consecutive third leading-out steps of different levels to a plurality of consecutive nth leading-out steps of different levels, where a sum of the levels of the first leading-out step to the nth leading-out step is equal to the level of the step to be formed, and for each group of leading-out steps, in other groups of leading-out steps, a lowest level step in one group of leading-out steps and a highest level step in the group of leading-out steps differ by the S levels, and a highest level step in another group of leading-out steps and a lowest level step in the group of leading-out steps differ by the S levels.
As an example, the number of stages of the first lead-out step to the number of stages of the nth lead-out step are all equal; the laminated material unit comprises a dielectric layer and a grid conducting layer which are laminated. In the description of the gate conductive layer, reference may be made to the description of the sacrificial layer in the first embodiment and the second embodiment, that is, the gate conductive layer is formed at the position of the sacrificial layer in the preparation process.
As shown in fig. 13 to 14, an example is provided, in which 144 steps are required to be formed, wherein etching is performed by dividing the structure into three regions, that is, a first connection region 601, a second connection region 602, and a third connection region 603, wherein during etching, a predetermined etching is performed on the corresponding stacked structure above the first connection region 601 and the third connection region 603, 96 steps (chop 96pa s) are etched away at a position corresponding to the first connection region 601, 48 steps are finally formed in the first connection region 601, steps from 1 step to 48 step are formed, 48 steps (chop48 pa s) are etched away at a position corresponding to the third connection region 603, steps from 48 step to 49 step to 96 step are finally formed in the third connection region 603, and further, the predetermined etching is not performed on the second connection region 602, and steps from 48 step are formed in a subsequent process, forming steps from 97 th level to 144 th level; then, the first connecting subarea, the third connecting subarea and the second connecting subarea which are formed after etching are etched by adopting the embodiment of the invention, the etching is firstly carried out in the Y direction, three symmetrical steps are formed on each auxiliary subarea and sequentially decreased from the center to the outside, a mountain-shaped structure is formed, namely, 48 steps of each connecting subarea are divided into three rows for preparation; then, each connection division is etched in an X-square shape, wherein fig. 14 is a cross-sectional view of the innermost layer after the first connection division is etched in the X-direction, and the left side in the figure also shows a cross-sectional view of the first connection division at a symmetrical position in the Y-direction, and finally, a required number of steps are formed in each area. Referring to fig. 13 again, steps are formed at symmetrical positions and around each connection partition, and actually, the uppermost three-level step is formed, so that WL continuity and isolation of the filling oxide can be realized.
In an example, when two or more connection partitions are formed, the connectable partitions may be alternately arranged left and right in the Y direction, such as the arrangement in fig. 13, thereby facilitating the layout of the device structure.
As shown in fig. 15, in an example, the connection area at least includes a first auxiliary area and a second auxiliary area along the Y direction, the first connection partition and the second connection partition are arranged in parallel along the X direction and have the same width along the Y direction, the first auxiliary area and the second auxiliary area are respectively arranged on two sides of the connection area along the Y direction, and the height of the first auxiliary area and the height of the second auxiliary area are equal to the height of the highest lead-out step in the first connection partition and the second connection partition.
In an optional example, the first connection sub-area 701, the second connection sub-area 702, and the third connection sub-area 703 are included, in this example, the connection sub-areas are arranged in parallel along the X direction, and a position where the preset etching (chop) is performed is different from that in the first embodiment, and the other manufacturing processes refer to the first embodiment, in this example, the first auxiliary area and the second auxiliary area directly form the last step without etching, and when the preset etching is performed on the area in the frame line in the Y direction, the etching width of each step may be selected according to actual requirements, in this example, the width of the 1 st step in the Y direction is wider and may be selected to be twice as that of the other steps, which is not limited to this, and fig. 5 shows a distribution of the steps obtained in this embodiment by obtaining the 144 steps in fig. 13.
As shown in fig. 16, the storage area includes a first storage partition 804 and a second storage partition 805, and the first storage partition 804, the connection area 800, and the second storage partition 805 are sequentially disposed. In this example, the connection region is provided between two portions of the memory region, so that the length of the word line can be shortened, the controllability of the word line is enhanced, and the delay time is reduced, and in this example, the first connection section 801, the second connection section 802, and the third connection section 803 are provided in the connection region to form a desired step in each connection section. In this example, the memory area is divided into two parts, which are respectively disposed at both sides of the connection area, so that the length of the word line can be shortened, the control capability of the word line is enhanced, and the delay time is reduced.
As shown in fig. 17, the connection area includes a first connection portion 901 and a second connection portion 902, and the first connection portion 901, the storage area 900 and the second connection portion 902 are sequentially disposed, where the first connection portion 901 includes at least the first connection partition 903, and the second connection portion 902 includes at least the second connection partition 904. In this example, the connection partition is divided into two parts, which are respectively disposed on two sides of the storage region 900, so that the length of the word line can be shortened, the control capability of the word line is enhanced, and the delay time is reduced.
As an example, the connection region is divided into at least a first portion and a second portion in the X direction, and is divided into a first auxiliary region and a second auxiliary region which are symmetrical in the Y direction, a portion of the first portion overlapping with the first auxiliary region or the second auxiliary region constitutes the first connection sub-region, a portion of the second portion overlapping with the first auxiliary region or the second auxiliary region constitutes the second connection sub-region, and a portion opposite to the first connection sub-region in the Y direction constitutes a first connection auxiliary region, and a portion opposite to the second connection sub-region in the Y direction constitutes a second connection auxiliary region, wherein:
the laminated structure of the first auxiliary area is formed with a first auxiliary stepped structure arranged along the Z direction, the laminated structure of the second auxiliary area is formed with a plurality of layers of second auxiliary stepped structures arranged along the Z direction, the first auxiliary stepped structure is gradually reduced from the center outwards, and the second auxiliary stepped structure is gradually reduced from the center outwards.
The invention also combines the etching in the X direction and the Y direction to realize the preparation of the required steps, cuts off the continuity of the steps in the Y direction, and also cuts off the continuity of the materials such as oxide and the like filled on the steps subsequently, thereby improving the stress and the expansion of the materials and improving the stability of the device.
As an example, the first auxiliary stair-step structure and the second auxiliary stair-step structure have the same number of levels, and the number of levels of the bottom surface of the first stair-step structure is equal to the number of levels of the bottom surface of the second stair-step structure, and the number of levels of the bottom surface of the third stair-step structure is equal to the number of levels of the bottom surface of the fourth stair-step structure; the step surfaces of adjacent levels in the steps to be formed have a difference of one level.
Example four:
the embodiment provides a method for manufacturing a three-dimensional memory, which includes a step of manufacturing a semiconductor structure by using the method for manufacturing a semiconductor structure according to any one of the first embodiment and the second embodiment, wherein a gate structure is formed in a storage region in the three-dimensional memory, and in a manufacturing process of the three-dimensional memory, a gate wiring layer is correspondingly formed at a position of a sacrificial layer in a stacked structure, so that a required number of steps are formed based on the gate wiring layer to electrically lead out a gate junction structure in the storage region.
In addition, the present invention also provides a three-dimensional memory structure, which includes the semiconductor structure according to any one of the embodiments, and is preferably prepared by using the method for preparing a three-dimensional memory provided in this embodiment, but may also be obtained by using other methods known in the art.
In summary, the semiconductor structure and the manufacturing method thereof, and the three-dimensional memory structure and the manufacturing method thereof of the present invention adopt a process combining the preset etching (chop) and the synchronous etching (trim and etch alternately process the mask layer), reduce the process difficulty of device manufacturing, reduce the number of mask plates, realize the manufacturing of steps in need by combining the etching in the X direction and the Y direction, cut off the continuity of the steps in the Y direction, and also cut off the continuity of the subsequent filling of materials such as oxides on the steps, thereby improving the stress and expansion of the materials, improving the stability of the device, dividing the steps to be formed into at least two parts to be respectively formed, arranging the connection region in the middle or both sides of the storage region, realizing the flexible arrangement of the steps, reducing the process difficulty of manufacturing, and shortening the length of the word line, the control capability of the word line is enhanced, and the time delay is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (20)

1. A method for fabricating a semiconductor structure, the method comprising:
providing a semiconductor substrate, defining an X direction and a Y direction which are vertical to each other in a plane where the semiconductor substrate is located, and defining a Z direction in a direction which is vertical to the plane where the semiconductor substrate is located;
forming a laminated structure on the semiconductor substrate, wherein the laminated structure comprises a plurality of laminated material units stacked along the Z direction, the laminated structure comprises a storage area and a connection area which are divided along the X direction, and the connection area at least comprises a first connection subarea and a second connection subarea;
performing preset etching of preset levels on the part of the laminated structure located in the first connection partition, wherein the laminated structure remaining in the first connection partition after etching comprises a first etching area and a second etching area which are sequentially divided along the X direction, the part of the laminated structure located in the first etching area is etched, so that the bottom surface of the first etching area is lower than the bottom surface of the second etching area by at least one level, one level comprises a laminated material unit, the parts of the laminated structure located in the first etching area and the second etching area are synchronously etched to form a first stepped structure located in the first etching area and a second stepped structure located in the second etching area, the first stepped structure is gradually raised from the center outwards, and the second stepped structure is gradually raised from the center outwards, so that each stepped surface forms a plurality of continuous first leading-out steps with different levels, the difference between the first leading-out steps of adjacent series is S levels, and S is more than or equal to 1;
the second connecting subarea comprises a third etching area and a fourth etching area which are sequentially divided along the X direction, the part of the laminated structure, which is positioned in the third etching area, is etched, so that the bottom surface of the third etching area is lower than the bottom surface of the fourth etching area by at least one level, the parts of the laminated structure, which are positioned in the third etching area and the fourth etching area, are synchronously etched, and a third step structure positioned in the third etching area and a fourth step structure positioned in the fourth etching area are formed, the third step structure is gradually increased from the center to the outside, the fourth step structure is gradually increased from the center to the outside, so that each step surface forms a plurality of continuous second leading-out steps with different levels, and the difference between the second leading-out steps of adjacent levels is S levels, and the sum of the number of the second leading-out steps and the number of the first leading-out steps is equal to the number of the steps to be formed.
2. The method for manufacturing a semiconductor structure according to claim 1, wherein the connection region further includes a third connection sub-region to an nth connection sub-region, N is an integer greater than three, wherein the portion of the stacked structure located between the third connection sub-region and the nth connection sub-region is subjected to predetermined etching of predetermined levels, so as to obtain a plurality of consecutive third leading-out steps of different levels to a plurality of consecutive nth leading-out steps of different levels, and the predetermined levels of the predetermined etching of the connection sub-regions are different from each other and different from the predetermined levels of the predetermined etching of the first connection sub-region, and the sum of the levels of the first leading-out steps to the nth leading-out steps is equal to the level of the step to be formed.
3. The method according to claim 2, wherein a sum of a number of steps of each group of the lead-out steps and a number of predetermined steps of a predetermined etching of the corresponding connection partition is equal to a number of steps to be formed, and a number of steps of the first lead-out step is equal to a number of steps of the nth lead-out step, and for each group of the lead-out steps, a lowest step of one group of the lead-out steps differs from a highest step of the group of the lead-out steps by the S steps, and a highest step of another group of the lead-out steps differs from a lowest step of the group of the lead-out steps by the S steps.
4. The method of claim 1, wherein the step of forming the first and second step-wise structures comprises:
a) forming a mask layer with an opening on the first connection partition, wherein the opening divides the mask layer into a first mask positioned on the first etching area and a second mask positioned on the second etching area, and the opening exposes a preset distance of the edge of the first etching area close to the second etching area;
b) etching the first connection subarea based on the mask layer so as to form a first step in the first etching area, wherein the etching depth is M levels, and M is an integer greater than or equal to 1;
c) trimming the second mask to enable the second mask to retract the preset distance from one side close to the first mask to the direction far away from the first mask, and etching the first connecting partition based on the trimmed mask layer, wherein the etching depth is M levels, so that a second step is formed in the second etching area, and the first step descends the M levels;
d) trimming the first mask to enable the first mask to retract to the preset distance from one side close to the second mask to the direction far away from the second mask, etching the first connecting partition based on the trimmed mask layer, wherein the etching depth is M levels, so that a third step is formed in the first etching area, and the first step and the second step both descend by the M levels;
e) repeating the steps c) to d) at least once to increase the number of steps.
5. The method of claim 1, wherein the storage area comprises a first storage partition and a second storage partition, and the first storage partition, the connection area, and the second storage partition are sequentially disposed.
6. The method of claim 1, wherein the connection region comprises a first portion and a second portion, and the first portion, the storage region and the second portion are sequentially disposed, wherein the first portion comprises at least the first connection partition and the second portion comprises at least the second connection partition.
7. The method of fabricating a semiconductor structure according to any one of claims 1 to 6, wherein the connecting region is divided into at least a first portion and a second portion along the X direction, and is divided into a first auxiliary region and a second auxiliary region which are symmetrical along the Y direction, a portion of the first portion overlapping the first auxiliary area or the second auxiliary area constitutes the first connection partition, a portion of the second portion overlapping with the first auxiliary area or the second auxiliary area constitutes the second connection partition, and a portion opposed to the first connection section in the Y direction constitutes a first connection auxiliary area, and a portion opposed to the second connection section in the Y direction constitutes a second connection auxiliary area, after the preset etching is performed on the first connection subarea and before the etching in the X direction is performed on the first connection subarea and the second connection subarea, the method further comprises the following steps:
and synchronously etching at least the overlapped parts of the laminated structure, which are positioned in the first auxiliary area and the second auxiliary area, and the first part and the second part along the Y direction to form a first auxiliary stepped structure positioned in the first auxiliary area and a second auxiliary stepped structure positioned in the second auxiliary area, wherein the first auxiliary stepped structure is gradually reduced from the center outwards, and the second auxiliary stepped structure is gradually reduced from the center outwards.
8. The method for manufacturing a semiconductor structure according to claim 7, wherein the first auxiliary step structure and the second auxiliary step structure are equal in number of levels, and are equal in both the number of levels at which the bottom surface of the first etching region is lower than the bottom surface of the second etching region and the number of levels at which the bottom surface of the third etching region is lower than the bottom surface of the fourth etching region; the laminated material unit comprises a laminated dielectric layer and a sacrificial layer.
9. The method of claim 7, wherein the step of forming the first auxiliary step structure and the second auxiliary step structure comprises:
f) forming a photoresist layer on at least the first auxiliary area and the second auxiliary area and the overlapped part of the first part and the second part, and exposing a preset auxiliary interval of the edges of the first auxiliary area and the second auxiliary area;
g) performing K-level etching on the laminated structure based on the photoresist layer to form a first auxiliary step in the first auxiliary area and a second auxiliary step in the second auxiliary area, wherein K is an integer greater than or equal to 1;
h) trimming the photoresist layer to enable the photoresist layer to respectively retract the preset auxiliary spacing from two sides to the center in the Y direction, and etching the laminated structure based on the trimmed photoresist layer to form a third auxiliary step in the first auxiliary area and a fourth auxiliary step in the second auxiliary area, wherein the first auxiliary step and the second auxiliary step both descend to the K level;
i) repeating the step h) at least once to increase the number of the auxiliary steps.
10. The method for manufacturing a semiconductor structure according to any one of claims 1 to 6, wherein the connection region includes at least a first auxiliary region and a second auxiliary region in the Y direction, the first connection partition and the second connection partition are arranged in parallel in the X direction and have the same width in the Y direction, the first auxiliary region and the second auxiliary region are respectively arranged on both sides of the connection region in the Y direction, and the height of the first auxiliary region and the height of the second auxiliary region are equal to the height of the highest extraction step in the first connection partition and the second connection partition.
11. A method for manufacturing a three-dimensional memory, comprising a step of manufacturing the semiconductor structure by using the method for manufacturing a semiconductor structure according to any one of claims 1 to 10.
12. A semiconductor structure, comprising:
the semiconductor device comprises a semiconductor substrate, a first substrate and a second substrate, wherein the plane of the semiconductor substrate is defined with an X direction and a Y direction which are vertical to each other, and the direction vertical to the plane of the semiconductor substrate is defined with a Z direction;
the laminated structure comprises a plurality of laminated material units stacked along the Z direction, the laminated structure comprises a storage area and a connection area which are divided along the X direction, and the connection area at least comprises a first connection subarea and a second connection subarea;
the laminated structure of the first connecting subarea is provided with a first stepped structure and a second stepped structure which are arranged along the Z direction, the first stepped structure is gradually raised from the center to the outside, the second stepped structure is gradually raised from the center to the outside, so that each stepped surface forms a plurality of continuous first leading-out steps with different levels, wherein the bottom surface of the first stepped structure is less than the bottom surface of the second stepped structure by at least one level, one level comprises one laminated material unit, the difference S between the first leading-out steps of adjacent levels is S, and S is an integer greater than or equal to 1;
the laminated structure of the second connecting subarea is provided with a third stepped structure and a fourth stepped structure which are arranged along the Z direction, the third stepped structure gradually rises from the center to the outside, the fourth stepped structure gradually rises from the center to the outside, so that each step surface forms a plurality of continuous second leading-out steps with different levels, the difference between the second leading-out steps of adjacent levels is S levels, wherein the sum of the levels of the second leading-out steps and the levels of the first leading-out steps is equal to the level of the step to be formed.
13. The semiconductor structure of claim 12, wherein the connection region further comprises a third connection partition to an nth connection partition, N being an integer greater than three, wherein each connection partition correspondingly comprises a number of consecutive third leading-out steps of different orders to a number of consecutive nth leading-out steps of different orders, wherein the sum of the orders of the first leading-out step to the nth leading-out step is equal to the order of the steps to be formed, and for each group of leading-out steps, among the other groups of leading-out steps, there is a lowest order step of one group of leading-out steps that differs from the highest order step of the one group of leading-out steps by the number of S levels, and there is a highest order step of the other group of leading-out steps that differs from the lowest order step of the one group of leading-out steps by the number of S levels.
14. The semiconductor structure of claim 13, wherein the first lead-out step is equal in number to the nth lead-out step; the laminated material unit comprises a dielectric layer and a grid conducting layer which are laminated.
15. The semiconductor structure of claim 12, wherein the memory area comprises a first memory partition and a second memory partition, and the first memory partition, the connection area, and the second memory partition are sequentially disposed.
16. The semiconductor structure of claim 12, wherein the connection region comprises a first portion and a second portion, and the first portion, the memory region, and the second portion are sequentially disposed, wherein the first portion comprises at least the first connection partition and the second portion comprises at least the second connection partition.
17. The semiconductor structure according to any one of claims 12 to 16, wherein the connection region is divided into at least a first portion and a second portion in the X direction, and is divided into a symmetrical first auxiliary region and a second auxiliary region in the Y direction, a portion of the first portion overlapping with the first auxiliary region or the second auxiliary region constitutes the first connection sub-region, a portion of the second portion overlapping with the first auxiliary region or the second auxiliary region constitutes the second connection sub-region, a portion of the second portion opposite to the first connection sub-region in the Y direction constitutes a first connection auxiliary region, and a portion of the second portion opposite to the second connection sub-region in the Y direction constitutes a second connection auxiliary region, wherein:
the laminated structure of the first auxiliary area is formed with a first auxiliary stepped structure arranged along the Z direction, the laminated structure of the second auxiliary area is formed with a plurality of layers of second auxiliary stepped structures arranged along the Z direction, the first auxiliary stepped structure is gradually reduced from the center outwards, and the second auxiliary stepped structure is gradually reduced from the center outwards.
18. The semiconductor structure of claim 17, wherein the first auxiliary ladder structure and the second auxiliary ladder structure are equal in number of levels, and are equal in number of levels lower than a bottom surface of the first ladder structure and lower than a bottom surface of the fourth ladder structure; the step surfaces of adjacent levels in the steps to be formed have a difference of one level.
19. The semiconductor structure according to any one of claims 12 to 16, wherein the connection region includes at least a first auxiliary region and a second auxiliary region in the Y direction, the first connection partition and the second connection partition are arranged in parallel in the X direction and have the same width in the Y direction, the first auxiliary region and the second auxiliary region are respectively arranged on both sides of the connection region in the Y direction, and the height of the first auxiliary region and the height of the second auxiliary region are equal to the height of the highest lead-out step in the first connection partition and the second connection partition.
20. A three-dimensional memory structure, comprising the semiconductor structure of any one of claims 12-19.
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