CN111155988A - Multi-frequency resistivity measuring device - Google Patents
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- E21B49/00—Testing the nature of borehole walls; Formation testing; Methods or apparatus for obtaining samples of soil or well fluids, specially adapted to earth drilling or wells
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Abstract
The invention discloses a multi-frequency resistivity measuring device, relates to the technical field of resistivity logging, and can realize simultaneous measurement of multiple frequencies under the condition of ensuring sufficient measurement accuracy of signals. The invention separates the waveform of various frequency signals by sampling and fitting the mixed waveform of multiple frequencies and combining digital DPSP operation, orthogonally separates the signal of single frequency, calculates the phase difference and amplitude ratio of each frequency signal, and finally obtains the resistivity information detected under different frequencies of the stratum. The invention improves the measuring efficiency and measuring timeliness of the instrument by a multi-frequency simultaneous measurement mode, and can reduce the system power consumption to a certain extent.
Description
Technical Field
The invention belongs to the technical field of resistivity logging, and particularly relates to a design of a multi-frequency resistivity measuring device.
Background
At present, with the development of resistivity logging technology, most of the logging field instrument systems are single-frequency time-sharing measurement, and detection of the stratum is realized by switching different frequencies. For example, the logging-while-drilling tool adopts 3 frequencies for measurement, which are 2MHz, 400KHz and 100KHz respectively, and different frequencies are alternately switched in the detection process to realize multi-frequency measurement. The logging instrument is provided with a plurality of transmitting antennae and receiving antennae, only one transmitting antenna is allowed to be in a transmitting state at any time, and the transmitting coils alternately transmit. If there are more than one transmitting frequency, the transmitting antenna needs to be switched in time-sharing mode while the multi-frequency time-sharing transmitting is adopted, and a long time is needed for completing a complete measuring period.
Therefore, the traditional multi-frequency time-sharing logging instrument has several disadvantages when in downhole measurement: (1) if the drilling speed is high, it is likely that the measurement at a certain frequency will not invert the change of the formation when the frequency is switched, because the measurement process is not continuous but intermittent for a certain transmitting channel at a certain frequency when the transmitting frequency and the transmitting channel are switched back and forth when the instrument is continuously drilling. Such as: after the 2MHz transmission signal of the T1 transmission channel is measured, the rest of the 2MHz transmission channels and the 400KHz and 100KHz signals of all the transmission channels are measured, and then the measurement of the 2MHz signal of the T1 transmission channel can be performed again. In the measurement process of other emission channels and emission frequencies, the drilling instrument is in continuous drilling and tends to have a certain displacement, so that the 2MHz measurement signal of the T1 channel is discontinuous for the detection of the stratum, and if the middle duration is too long, some measurement errors are caused, and the inversion and calculation amount of later data is increased. (2) Time-sharing measurement takes time, the frequency is more, each frequency needs to be transmitted alternately, time is wasted, measurement timeliness is poor, and effective power waste of time-sharing measurement is serious.
Disclosure of Invention
The invention aims to solve the problems of the traditional multi-frequency time-sharing logging instrument, and provides a multi-frequency resistivity measuring device.
The technical scheme of the invention is as follows: the utility model provides a multifrequency resistivity measuring device, including measuring and transmitting the control panel, power module, communication memory board and n receiving boards, it is connected with n receiving boards one-to-one through n LVDS communication interface respectively to measure and transmit the control panel, it is connected with the communication memory board through the RS485 interface to measure and transmit the control panel, power module's input is connected with ground center control system, its output respectively with measure and transmit the control panel, communication memory board and every receiving board are connected, communication memory board still is connected with ground center control system.
Furthermore, the measurement and emission control panel comprises an FPGA main controller, a DSP main controller, an emission and control circuit, a temperature sensor and a peripheral circuit; the DSP main controller is connected with the transmitting and controlling circuit and is used for controlling the transmitting and controlling circuit to generate transmitting signals with a plurality of frequencies; the DSP main controller is connected with the FPGA main controller through an internal bus and is used for carrying out DPSD digital phase-sensitive detection operation on the accumulated operation result output by the FPGA main controller to obtain resistivity data of each frequency signal; the DSP main controller is connected with the communication storage board through an RS485 interface and is used for sending the real-time measurement data transmitted by the receiving board and the final measurement result obtained by calculation to the communication storage board for packaging and storage; the FPGA main controller is respectively connected with the n receiving boards in a one-to-one correspondence mode through the n LVDS communication interfaces and is used for transmitting commands, reset signals, synchronous clocks and 48KHz sampling clocks to the receiving boards, receiving data sampled by the ADC of the receiving boards and carrying out accumulation operation; the temperature sensor is connected with the DSP main controller through the SPI interface and used for sensing, measuring and transmitting the temperature of the control panel and sending the temperature to the DSP main controller; and the peripheral circuit is respectively connected with the FPGA main controller and the DSP main controller.
Furthermore, the transmitting and controlling circuit comprises a plurality of first DDS digital frequency synthesizers, a first combiner, m transmitting channel control switch groups and m transmitting channels; each first DDS digital frequency synthesizer is connected with the DSP main controller and is used for generating transmitting signals with different frequencies under the control of the DSP main controller; the input end of the first combiner is connected with the output end of each first DDS digital frequency synthesizer and is used for integrating a plurality of paths of transmitting signals with different frequencies into a path of mixed signal to be output; each path of transmitting channel has the same structure and comprises a power amplifying circuit and a transmitting antenna which are sequentially connected, wherein the power amplifying circuit is used for carrying out power amplification on the mixed signal output by the first combiner, and the transmitting antenna is used for exciting an electromagnetic field according to the mixed signal after power amplification and radiating an electromagnetic wave signal outwards; the m-channel transmitting channel control switch groups are respectively connected with the DSP main controller, the output end of the first combiner and the input end of the power amplifying circuit in each transmitting channel, and are used for enabling a switch of a certain transmitting channel, connecting a +32V power supply to the power amplifying circuit of the channel, and connecting a transmitting signal to the input end of the power amplifying circuit, so that the transmitting channel is started to transmit.
Further, the number n of the receiving boards is even, and the number m of the transmitting channels is even.
Furthermore, each receiving board has the same structure and comprises an FPGA chip, a plurality of second DDS digital frequency synthesizers, a second combiner, a receiving antenna, a 2-level low noise amplifier, a frequency mixer, a band-pass filter, a program-controlled operational amplifier and a high-precision ADC; each second DDS digital frequency synthesizer is connected with the FPGA chip and is used for generating local oscillation signals with different frequencies under the control of the FPGA chip; the input end of the second combiner is connected with the output end of each second DDS digital frequency synthesizer and used for integrating the local oscillator signals with different frequencies into a mixed local oscillator signal for output; the receiving antenna is used for receiving echo signals of the electromagnetic wave signals transmitted by the measuring and transmitting control board after passing through the stratum; the 2-stage low-noise amplifier is connected with the receiving antenna and used for carrying out 2-stage low-noise amplification on the echo signal and outputting the amplified receiving signal; the input end of the frequency mixer is respectively connected with the output end of the second combiner and the output end of the 2-stage low-noise amplifier and is used for carrying out frequency mixing subtraction on the amplified received signal and the mixed local oscillator signal to obtain harmonic components with different frequency combinations; the input end of the band-pass filter is connected with the output end of the mixer and is used for carrying out band-pass filtering on harmonic components with different frequency combinations to obtain mixed intermediate-frequency signals; the input end of the program-controlled operational amplifier is connected with the output end of the band-pass filter and is used for carrying out program-controlled operational amplification processing on the mixed intermediate-frequency signals; the input end of the high-precision ADC is connected with the output end of the program-controlled operational amplifier and is used for carrying out analog-to-digital conversion and real-time sampling on the intermediate-frequency signal subjected to the program-controlled operational amplification treatment to obtain ADC sampling data; the FPGA chip is connected with the program-controlled operational amplifier and is used for adjusting the amplification factor of the program-controlled operational amplifier; the FPGA chip is also connected with the high-precision ADC and the FPGA main controller through the LVDS communication interface and is used for transmitting the ADC sampling data output by the high-precision ADC to the FPGA main controller through the LVDS communication interface for accumulation operation.
Further, the number of the first DDS digital frequency synthesizers is the same as that of the second DDS digital frequency synthesizers.
Further, the amplification factor of the previous stage of the 2-stage low noise amplifier is 40 times, and the amplification factor of the next stage is 5 times.
Further, the communication storage board comprises a DSP slave controller, a Flash large-capacity storage chip set, an RS485 module and a clock RTC module; the DSP slave controller is connected with the DSP master controller through an RS485 interface and is used for receiving real-time measurement data and a final measurement result; the Flash large-capacity storage chip set is connected with the DSP slave controller and used for storing the received real-time measurement data and the final measurement result; the RS485 module is respectively connected with the DSP slave controller and the ground central control system and is used for receiving various control instructions from the ground central control system and executing related operations; the clock RTC module is connected with the DSP slave controller and used for providing an internal clock for the whole measuring device and providing a time reference for data storage each time.
Further, the power supply module is used for providing an adaptive power supply for the whole measuring device, the input of the power supply module is +32V, and the output of the power supply module comprises +3.3V, +5VD, + 5VA, +1.5V and + 1.8V.
The invention has the beneficial effects that:
(1) the invention realizes the simultaneous measurement of multiple frequencies during logging, only needs to add a plurality of DDS digital frequency synthesizers and related combiner circuits on a hardware circuit, and can upgrade the prior single-frequency time-sharing measurement into the simultaneous measurement of multiple frequencies without changing circuits at other places.
(2) The invention effectively solves the problem that the existing logging technology only can realize single-frequency time-sharing emission, thereby having poor timeliness, and has more excellent efficiency, energy conservation and consumption reduction.
(3) The invention solves the problem that the existing logging technology needs to switch back and forth for frequency control in multi-frequency measurement, each DDS digital frequency synthesizer only takes charge of one frequency, so that the operation is only carried out once by electrifying and initializing, the subsequent measurement process is only to switch the control switch group alternately, when the measurement device is in a dormant state or in a low-power-consumption standby state, the DDS digital frequency synthesizer is dormant, therefore, each DDS digital frequency synthesizer only needs to be configured once when an instrument is electrified, and the DDS digital frequency synthesizer does not need to be continuously subjected to various frequency word operation control, so that the operation is simpler and more efficient.
Drawings
Fig. 1 is a block diagram of a multi-frequency resistivity measurement apparatus according to an embodiment of the present invention.
Fig. 2 is a block diagram of a transmitting and controlling circuit according to an embodiment of the present invention.
Fig. 3 is a block diagram of a receiving board according to an embodiment of the present invention.
Fig. 4 is a structural diagram of a transmitting and receiving coil according to an embodiment of the present invention.
Fig. 5 is a flowchart of a multi-frequency resistivity measurement method according to a second embodiment of the present invention.
Fig. 6 is a waveform diagram of a 3-frequency transmitting signal according to a second embodiment of the present invention.
Fig. 7 is a waveform diagram of a mixed signal after synthesis of a 3-frequency transmitting signal according to a second embodiment of the present invention.
Fig. 8 is a waveform diagram of a mixed signal after synthesizing a 3-frequency if signal according to the second embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It is to be understood that the embodiments shown and described in the drawings are merely exemplary and are intended to illustrate the principles and spirit of the invention, not to limit the scope of the invention.
The first embodiment is as follows:
the embodiment of the invention provides a multi-frequency resistivity measuring device, which comprises a measuring and transmitting control board, a power supply module, a communication storage board and n receiving boards, wherein the measuring and transmitting control board is respectively connected with the n receiving boards in a one-to-one correspondence mode through n LVDS communication interfaces, the measuring and transmitting control board is connected with the communication storage board through an RS485 interface, the input end of the power supply module is connected with a ground central control system, the output end of the power supply module is respectively connected with the measuring and transmitting control board, the communication storage board and each receiving board, and the communication storage board is also connected with the ground central control system.
The measurement and emission control panel comprises an FPGA main controller, a DSP main controller, an emission and control circuit, a temperature sensor and a peripheral circuit.
The DSP main controller is connected with the transmitting and controlling circuit and is used for controlling the transmitting and controlling circuit to generate transmitting signals with a plurality of frequencies; the DSP main controller is connected with the FPGA main controller through an internal bus and is used for carrying out DPSD digital phase-sensitive detection operation on the accumulated operation result output by the FPGA main controller to obtain resistivity data of each frequency signal; the DSP main controller is connected with the communication storage board through an RS485 interface and is used for sending the real-time measurement data transmitted by the receiving board and the final measurement result obtained through calculation to the communication storage board for packaging and storage.
In the embodiment of the invention, the DSP main controller preferably selects a DSP28377PTP high temperature resistant model, the processor is a TI high-performance TMS320C28x series 32-bit floating point DSP dual-core processor, the main frequency is up to 200MHz, and the DSP main controller has strong digital signal processing and DPSD operation capabilities. The DSP main controller controls the output of a plurality of first DDS digital frequency synthesizers, and can independently adjust the frequency and amplitude of the output signal of each first DDS digital frequency synthesizer.
The FPGA main controller is respectively connected with the n receiving boards in a one-to-one correspondence mode through the n LVDS communication interfaces and used for transmitting commands, reset signals, synchronous clocks and 48KHz sampling clocks to the receiving boards, the fact that the channels of the receiving boards receive and process electromagnetic wave signals of the stratum at the same time is guaranteed, time sequence synchronization is achieved, and data sampled by the ADCs of the receiving boards are received and accumulated.
The temperature sensor is connected with the DSP main controller through the SPI interface, is used for sensing the temperature of the measurement and emission control panel and sending the temperature to the DSP main controller, and is stored on the communication storage board together with the measurement data I, and is used for temperature correction of data on the ground in the later period.
And the peripheral circuit is respectively connected with the FPGA main controller and the DSP main controller. In the embodiment of the invention, the peripheral circuit comprises a power supply filtering and decoupling capacitor, a clock crystal oscillator, a watchdog reset circuit and the like.
As shown in fig. 2, the transmitting and controlling circuit includes a plurality of first DDS digital frequency synthesizers, a first combiner, m transmitting channel control switch sets, and m transmitting channels.
Each first DDS digital frequency synthesizer is connected with the DSP main controller and is used for generating transmitting signals with different frequencies under the control of the DSP main controller. In the embodiment of the invention, the first DDS digital frequency synthesizer is preferably a DDS-AD9852 type, and the frequency of the transmitting signal comprises 2MHz, 400KHz and 100 KHz.
The input end of the first combiner is connected with the output end of each first DDS digital frequency synthesizer, and the first combiner is used for integrating the multiple paths of transmitting signals with different frequencies into one path of mixed signal to be output, and the input is not influenced by the output.
Each path of transmitting channel has the same structure and comprises a power amplifying circuit and a transmitting antenna which are sequentially connected, wherein the power amplifying circuit is used for carrying out power amplification on the mixed signal output by the first combiner, and the transmitting antenna is used for exciting an electromagnetic field and radiating an electromagnetic wave signal outwards according to the mixed signal after power amplification.
The m-channel transmitting channel control switch groups are respectively connected with the DSP main controller, the output end of the first combiner and the input end of the power amplifying circuit in each transmitting channel, and are used for enabling a switch of a certain transmitting channel, connecting a +32V power supply to the power amplifying circuit of the channel, and connecting a transmitting signal to the input end of the power amplifying circuit, so that the transmitting channel is started to transmit.
In the embodiment of the invention, only one transmitting channel is in a transmitting working state at any time, and other transmitting channels are closed, so that the transmitting channels alternately transmit, and the possibility of simultaneous transmission of multiple channels is avoided.
As shown in fig. 3, each receiving board has the same structure and includes an FPGA chip, a plurality of second DDS digital frequency synthesizers, a second combiner, a receiving antenna, a 2-stage low noise amplifier, a mixer, a band pass filter, a programmable operational amplifier, and a high precision ADC.
And each second DDS digital frequency synthesizer is connected with the FPGA chip and is used for generating local oscillation signals with different frequencies under the control of the FPGA chip. In the embodiment of the invention, the second DDS digital frequency synthesizer is preferably of DDS-AD9837 type, the chip of the type is a serial data interface, the requirement on an IO port is less, and the frequency and the phase of an output signal can be set at will.
The input end of the second combiner is connected with the output end of each second DDS digital frequency synthesizer, and the second combiner is used for integrating the plurality of local oscillator signals with different frequencies into one mixed local oscillator signal to be output.
The receiving antenna is used for receiving echo signals of the electromagnetic wave signals transmitted by the measuring and transmitting control board after passing through the stratum.
The 2-stage low-noise amplifier is connected with the receiving antenna and used for carrying out 2-stage low-noise amplification on the echo signal and outputting the amplified receiving signal.
The input end of the mixer is respectively connected with the output end of the second combiner and the output end of the 2-stage low-noise amplifier, and is used for carrying out frequency mixing subtraction on the amplified received signal and the mixed local oscillator signal to obtain harmonic components with different frequency combinations.
The input end of the band-pass filter is connected with the output end of the mixer and used for carrying out band-pass filtering on the harmonic components with different frequency combinations to obtain mixed intermediate-frequency signals.
The input end of the program control operational amplifier is connected with the output end of the band-pass filter and used for carrying out program control operational amplification processing on the mixed intermediate-frequency signals.
The input end of the high-precision ADC is connected with the output end of the program-controlled operational amplifier and used for carrying out analog-to-digital conversion and real-time sampling on the intermediate-frequency signal subjected to the program-controlled operational amplification treatment to obtain ADC sampling data.
The FPGA chip is connected with the program-controlled operational amplifier and is used for adjusting the amplification factor of the program-controlled operational amplifier; the FPGA chip is also connected with the high-precision ADC and the FPGA main controller through the LVDS communication interface and is used for transmitting the ADC sampling data output by the high-precision ADC to the FPGA main controller through the LVDS communication interface for accumulation operation. In the embodiment of the invention, the FPGA chip preferably adopts the FPGA of high-reliability ACTEL company, and the series of controllers have high-temperature resistance.
In the embodiment of the present invention, the number n of the receiving boards is an even number, and the number m of the transmitting channels is an even number, which may be dual transmission and dual reception, or 4 transmission and 4 reception or 4 transmission and dual reception, and may be increased or decreased according to the actual situation, and a structure of 4 transmission and 4 reception is preferred in the embodiment of the present invention, as shown in fig. 4.
In the embodiment of the present invention, the number of the first DDS digital frequency synthesizers is the same as that of the second DDS digital frequency synthesizers, and is equal to the number of the transmission frequencies, that is, how many transmission signals with different frequencies are generated by the first DDS digital frequency synthesizers, and the second DDS digital frequency synthesizers generate local oscillation signals with different frequencies corresponding to the number of the transmission signals. The local oscillator signal is used for performing frequency mixing processing with the received signal, and the local oscillator signal differs from the transmitted signal by a frequency of a fixed magnitude, such as: if the transmitting signal is 2MHz, the local oscillation signal corresponding to the transmitting signal should be 1.992MHz, and 8KHz intermediate frequency signals are output after frequency mixing; similarly, if the transmission signal is 400KHz, the local oscillation signal corresponding to the transmission signal should be 394KHz, and the intermediate frequency signal of 6KHz is output after frequency mixing. Similarly, if the transmission signal is 100KHz, the local oscillation signal corresponding to the transmission signal should be 96KHz, and after frequency mixing, an intermediate frequency signal of 4KHz is output.
In the embodiment of the invention, the amplification factor of the front stage of the 2-stage low noise amplifier is 40 times, and the amplification factor of the rear stage is 5 times.
As shown in fig. 1, the communication storage board includes a DSP slave controller, a Flash mass storage chipset, an RS485 module, and a clock RTC module. The DSP slave controller is connected with the DSP master controller through an RS485 interface and used for receiving real-time measurement data and a final measurement result.
And the Flash large-capacity storage chip set is connected with the DSP slave controller and is used for storing the received real-time measurement data and the final measurement result. And the RS485 module is respectively connected with the DSP slave controller and the ground central control system, and is used for receiving various control instructions from the ground central control system and executing related operations.
The clock RTC module is connected with the DSP slave controller and used for providing an internal clock for the whole measuring device and providing a time reference for data storage each time.
In the embodiment of the invention, the power supply module is used for providing an adaptive power supply for the whole measuring device, the input of the power supply module is +32V, and the output of the power supply module comprises +3.3V, +5VD, + 5VA, +1.5V and + 1.8V.
The working principle and process of the multi-frequency resistivity measuring device provided by the embodiment of the invention will be described in detail with reference to fig. 1 to 4:
the measurement and emission control board is communicated with the communication storage board through an RS485 bus to receive a command of the communication storage board, when a measurement starting command is received, the measurement and emission control board controls the first DDS digital frequency synthesizers to enable the first DDS digital frequency synthesizers to output sine wave emission signals with certain fixed frequency and amplitude, and the plurality of first DDS digital frequency synthesizers output sine wave emission signals with different frequencies and amplitudes and are integrated into a mixed emission signal through the first combiner. The first combiner can also amplify the integrated signal, and the amplification factor is generally 1-3 times. Because the measuring device is provided with 4 transmitting antennas, only one transmitting channel is allowed to be in a transmitting state at any time, 4 transmitting channel control switch groups are needed to respectively control the power supply of the 4 power transmitting channels and the input of signals, and the transmitting is alternately started in turn. Firstly, a T1 channel is started to transmit, a 32V power supply is connected into a power amplifying circuit, a mixed transmitting signal is also output to the input side of the power amplifying circuit, the mixed transmitting signal is output to a transmitting coil T1 after two-stage amplification, and an electromagnetic field is excited by the coil and electromagnetic waves are radiated outwards; after the T1 emission is completed, the switch of the T1 channel is closed, then the T2 channel is opened for emission, and the measurement period is completed when the last T4 emission and detection are completed, at this time, the input of the 32V main power supply is closed, and all the emission channel signal inputs are also closed. And after the received data is subjected to the DPSD processing and uploaded and stored, the DSP main controller is in a standby state, continues to wait for receiving a measurement starting instruction and then executes the next measurement period.
The receiving board mainly comprises an FPGA chip and a signal receiving conditioning acquisition circuit, a receiving antenna receives electromagnetic echo signals from the stratum and generates induced electromotive force on a coil, the frequency characteristics of the signals are consistent with those of transmitted signals, but the signal amplitude is weak and is usually micro-volt or tens of nano-volts, so that low-noise amplification processing needs to be carried out on the signals, front and rear 2-stage low-noise amplification is adopted, the amplification factor of the front stage is about 40 times, the amplification factor of the rear stage is 5 times, and the total low-noise amplification of the 2 stages is 200 times. Because the transmitting signal is composed of a plurality of frequency components and the span of the frequency components is large, in the embodiment of the invention, in order to convert the transmitting signal into a plurality of intermediate frequency signals for convenient detection, the receiving board needs to output a plurality of same local oscillation signals. The FPGA chip controls a plurality of second DDS digital frequency synthesizers to output local oscillation signals with the frequency close to the frequency of the transmitted signal, the local oscillation signals are integrated into a mixed local oscillation signal through a second combiner, then the mixed local oscillation signal and the received signal are output to a mixer together, waveform components of various frequencies are obtained after subtraction is carried out on the mixer, at the moment, clutter signals of high frequency and low frequency are filtered out together through a band-pass filter, and then only a plurality of intermediate frequency signals are left, such as signals of 4KHz, 6KHz and 8 KHz. And then, carrying out program-controlled operation amplification on the intermediate frequency mixed signals, setting and adjusting the amplification factor according to the actual situation through a program, and finally transmitting the amplified signals to the input end of the high-precision ADC for analog-to-digital conversion by the ADC.
After starting measurement, when a certain transmitting channel starts transmission, 4 receiving plates start receiving, analog-to-digital conversion and sampling simultaneously. The FPGA chip on the receiving board is connected with the FPGA main controller on the measuring and transmitting control board through the LVDS communication interface to receive the synchronous clock, the sampling clock and the reset signal, so that the actions of the 4 receiving boards can be basically ensured to be in a consistent state, the synchronization on the measuring time sequence is ensured, and meanwhile, the LVDS communication interface can be used as communication to transmit commands or upload sampling data. The FPGA chips on the 4 receiving boards control the high-precision ADC to sample the conditioned and amplified intermediate-frequency mixed signal at a sampling frequency of 48KHz, and transmit the data to the FPGA main controller of the measuring and transmitting control board through the LVSDS communication interface in real time, and the data are accumulated in the FPGA main controller and are transmitted back to the DSP main controller through an internal data bus to be further subjected to DPSD digital phase-sensitive detection operation.
The DSP main controller has strong digital signal processing and DPSD computing capability, converts data into SIN and COS, calculates the real part and imaginary part of each frequency signal, calculates the phase and amplitude of each frequency signal, combines the symmetric compensation principle of a transmitting channel, finally obtains the phase difference and amplitude ratio data of each frequency signal, and further obtains the resistivity information detected under different frequencies of the stratum. After the whole-period measurement is completed, the DSP main controller packs and sends the whole measurement data including the original data, the intermediate data and the final result data to the communication storage board through the internal RS485 bus, and the communication storage board stores all the data in the Flash large-capacity storage chip set for later data integral reading and ground data analysis and inversion.
In order to make the technical solution of the present invention clearer and more complete, the detailed description will be given to the measuring method corresponding to the multi-frequency resistivity measuring apparatus provided in the first embodiment of the two pairs of embodiments, and the purpose is to further explain the working principle and process of the multi-frequency resistivity measuring apparatus provided in the first embodiment.
Example two:
a multi-frequency resistivity measurement method, as shown in FIG. 5, includes the following steps S1-S13:
and S1, powering on the multi-frequency resistivity measuring device, and performing initialization and self-checking.
And S2, enabling the multi-frequency resistivity measuring device to stand by and waiting for receiving the instruction.
S3, judging whether the received command is a start measurement command, if yes, entering step S4, otherwise, executing relevant operation according to the command requirement, and returning to step S2.
In the embodiment of the invention, the related operations comprise instrument state query, memory data reading, Flash formatting and parameter configuration.
And S4, enabling a plurality of first DDS digital frequency synthesizers to generate transmitting signals with different frequencies through the DSP main controller on the measuring and transmitting control board, and integrating the plurality of paths of transmitting signals with different frequencies into a path of mixed signal through the first combiner.
In the embodiment of the present invention, the transmission signal includes sine wave signals with three frequencies of 2MHz, 400KHz and 100KHz, as shown in fig. 6. The waveform of the mixed signal obtained by integrating the three transmission signals with different frequencies by the first combiner is shown in fig. 7.
S5, enabling the m-channel transmitting channel control switch group to control the T through the DSP main controlleriThe +32V power supply of the transmitting channel is switched on, and the mixed signal is switched in to TiInput terminal of power amplifying circuit of transmitting channel, let TiThe transmitting channel is in a transmitting state; wherein the initial value of the count value i is 1.
And S6, generating parameters and instructions in the FPGA main controller, and sending the parameters and instructions to the FPGA chips of the n receiving boards through the n LVDS communication interfaces.
And S7, enabling a plurality of second DDS digital frequency synthesizers to generate local oscillation signals with the frequency similar to the frequency of the transmitting signals of each frequency through the FPGA chip, and simultaneously starting the receiving antenna to receive echo signals of the transmitting signals after passing through the stratum.
And S8, obtaining ADC sampling data in the receiving board according to the echo signals and the local oscillator signals, and transmitting the ADC sampling data back to the FPGA main controller for accumulation processing in real time through the LVDS communication interface.
The step S8 includes the following substeps S81-S87:
s81, 2-stage low noise amplification is performed on the received echo signal by the 2-stage low noise amplifier, and the amplified received signal is output.
In the embodiment of the invention, the amplification factor of the previous stage of 2-stage low-noise amplification is 40 times, and the amplification factor of the next stage is 5 times.
And S82, integrating the local oscillator signals with different frequencies into a mixed local oscillator signal through a second combiner.
And S83, inputting the amplified received signal and the mixed local oscillator signal into a mixer for frequency mixing subtraction to obtain harmonic components with different frequency combinations.
And S84, performing band-pass filtering on the harmonic components with different frequency combinations through a band-pass filter to obtain a mixed intermediate frequency signal.
In the embodiment of the present invention, the mixed intermediate frequency signal includes three frequencies of 4KHz, 6KHz and 8KHz, and the waveform of the mixed signal synthesized by the three frequencies is as shown in fig. 8.
And S85, performing program control operation amplification processing on the mixed intermediate frequency signal through a program control operation amplifier.
And S86, performing analog-to-digital conversion and real-time sampling on the intermediate-frequency signal subjected to the program control operation amplification processing through the high-precision ADC to obtain ADC sampling data.
And S87, transmitting the ADC sampling data back to the FPGA main controller for accumulation processing in real time through the LVDS communication interface.
S9, after the superposition period is measured, the FPGA main controller informs the receiving boards to stop receiving and sampling, and the DSP main controller closes TiAnd transmitting signals of the channel and inputting a power supply.
And S10, performing DPSD digital phase-sensitive detection operation on the accumulated data of the FPGA main controller through the DSP main controller to obtain the original phase and amplitude of each frequency signal.
S11, judging whether the count value i is equal to m, if yes, finishing the emission and measurement of all emission channels, and entering step S12, otherwise adding 1 to the count value i, and returning to step S5.
And S12, calculating phase difference and amplitude ratio data of each symmetrical channel by the DSP main controller according to the original phase and amplitude of each frequency signal by adopting a transmitting and receiving antenna symmetry compensation principle, further obtaining resistivity information detected under different frequencies of the stratum, and packaging the resistivity information as a final measurement result together with the original measurement data and the intermediate data to be sent to the communication storage board.
And S13, storing the received measurement data in a Flash large-capacity storage chipset by the communication storage board for later reading and ground data analysis and inversion, completing a measurement period, and returning to the step S2 to continue waiting for receiving instructions.
In the embodiment of the invention, the number n of the receiving plates is an even number, the number m of the transmitting channels is an even number, and the specific number can be increased or decreased according to the actual situation.
In the embodiment of the invention, the number of the first DDS digital frequency synthesizers is the same as that of the second DDS digital frequency synthesizers, and is equal to that of the transmission frequencies.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (9)
1. The utility model provides a multifrequency resistivity measuring device, its characterized in that, is including measuring and transmission control panel, power module, communication memory board and n receiver boards, it is connected with n receiver boards one-to-one respectively to measure and transmit the control panel through n LVDS communication interface, it is connected with the communication memory board through the RS485 interface to measure and transmit the control panel, power module's input is connected with ground center control system, and its output is connected with measuring and transmission control panel, communication memory board and every receiver board respectively, the communication memory board still is connected with ground center control system.
2. The multi-frequency resistivity measurement device of claim 1 wherein the measurement and transmission control board comprises an FPGA master controller, a DSP master controller, transmission and control circuitry, temperature sensors and peripheral circuitry;
the DSP main controller is connected with the transmitting and controlling circuit and is used for controlling the transmitting and controlling circuit to generate transmitting signals with a plurality of frequencies; the DSP main controller is connected with the FPGA main controller through an internal bus and is used for carrying out DPSD digital phase-sensitive detection operation on the accumulated operation result output by the FPGA main controller to obtain resistivity data of each frequency signal; the DSP main controller is connected with the communication storage board through an RS485 interface and is used for sending the real-time measurement data transmitted by the receiving board and the final measurement result obtained by calculation to the communication storage board for packaging and storage;
the FPGA main controller is respectively connected with the n receiving boards in a one-to-one correspondence mode through the n LVDS communication interfaces and is used for transmitting commands, reset signals, synchronous clocks and 48KHz sampling clocks to the receiving boards, receiving data sampled by the ADC of the receiving boards and performing accumulation operation;
the temperature sensor is connected with the DSP main controller through the SPI interface and used for sensing, measuring and transmitting the temperature of the control panel and sending the temperature to the DSP main controller;
and the peripheral circuit is respectively connected with the FPGA main controller and the DSP main controller.
3. The multi-frequency resistivity measurement device of claim 2, wherein the transmit and control circuitry comprises a plurality of first DDS digital frequency synthesizers, a first combiner, m transmit channel control switch sets, and m transmit channels;
each first DDS digital frequency synthesizer is connected with the DSP main controller and is used for generating transmitting signals with different frequencies under the control of the DSP main controller;
the input end of the first combiner is connected with the output end of each first DDS digital frequency synthesizer and is used for integrating a plurality of paths of transmitting signals with different frequencies into a path of mixed signal to be output;
each path of the transmitting channel has the same structure and comprises a power amplifying circuit and a transmitting antenna which are sequentially connected, wherein the power amplifying circuit is used for carrying out power amplification on the mixed signal output by the first combiner, and the transmitting antenna is used for exciting an electromagnetic field and radiating an electromagnetic wave signal outwards according to the mixed signal after power amplification;
the m-channel transmitting channel control switch groups are respectively connected with the DSP main controller, the output end of the first combiner and the input end of the power amplifying circuit in each transmitting channel, and are used for enabling a switch of a certain transmitting channel, connecting a +32V power supply to the power amplifying circuit of the channel, and connecting a transmitting signal to the input end of the power amplifying circuit, so that the transmitting channel is started to transmit.
4. The multi-frequency resistivity measurement device of any one of claims 1-3, wherein the number n of receiving plates is an even number and the number m of transmitting channels is an even number.
5. The multi-frequency resistivity measurement device of claim 3, wherein each of the receiving boards has the same structure and comprises an FPGA chip, a plurality of second DDS digital frequency synthesizers, a second combiner, a receiving antenna, a 2-stage low noise amplifier, a mixer, a band-pass filter, a programmable operational amplifier and a high-precision ADC;
each second DDS digital frequency synthesizer is connected with the FPGA chip and is used for generating local oscillation signals with different frequencies under the control of the FPGA chip;
the input end of the second combiner is connected with the output end of each second DDS digital frequency synthesizer and used for integrating multiple paths of local oscillation signals with different frequencies into one path of mixed local oscillation signal to be output;
the receiving antenna is used for receiving echo signals of the electromagnetic wave signals transmitted by the measuring and transmitting control board after passing through the stratum;
the 2-stage low-noise amplifier is connected with the receiving antenna and used for carrying out 2-stage low-noise amplification on the echo signal and outputting the amplified receiving signal;
the input end of the frequency mixer is respectively connected with the output end of the second combiner and the output end of the 2-stage low-noise amplifier and is used for carrying out frequency mixing subtraction on the amplified received signal and the mixed local oscillator signal to obtain harmonic components with different frequency combinations;
the input end of the band-pass filter is connected with the output end of the frequency mixer and is used for carrying out band-pass filtering on harmonic components with different frequency combinations to obtain mixed intermediate-frequency signals;
the input end of the program-controlled operational amplifier is connected with the output end of the band-pass filter and is used for carrying out program-controlled operational amplification processing on the mixed intermediate-frequency signals;
the input end of the high-precision ADC is connected with the output end of the program-controlled operational amplifier and is used for carrying out analog-to-digital conversion and real-time sampling on the intermediate-frequency signal subjected to the program-controlled operational amplification treatment to obtain ADC sampling data;
the FPGA chip is connected with the program-controlled operational amplifier and is used for adjusting the amplification factor of the program-controlled operational amplifier; the FPGA chip is also connected with the high-precision ADC and the FPGA main controller through the LVDS communication interface and is used for transmitting ADC sampling data output by the high-precision ADC to the FPGA main controller through the LVDS communication interface to carry out accumulation operation.
6. The multi-frequency resistivity measurement device of claim 5 wherein the first and second DDS digital frequency synthesizers are equal in number.
7. The multi-frequency resistivity measurement device of claim 5 wherein the 2-stage low noise amplifier has a previous stage amplification factor of 40 and a subsequent stage amplification factor of 5.
8. The multi-frequency resistivity measurement device of claim 2, wherein the communication storage board comprises a DSP slave controller, a Flash mass storage chipset, an RS485 module, and a clock RTC module;
the DSP slave controller is connected with the DSP master controller through an RS485 interface and is used for receiving real-time measurement data and a final measurement result;
the Flash large-capacity storage chip set is connected with the DSP slave controller and used for storing the received real-time measurement data and the final measurement result;
the RS485 module is respectively connected with the DSP slave controller and the ground central control system and is used for receiving various control instructions from the ground central control system and executing related operations;
the clock RTC module is connected with the DSP slave controller and used for providing an internal clock for the whole measuring device and providing a time reference for data storage each time.
9. The multi-frequency resistivity measurement device of claim 1 wherein the power module is configured to provide an adaptive power supply for the entire measurement device with an input of +32V and an output of +3.3V, +5VD, + 5VA, +1.5V, and + 1.8V.
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