CN111147057A - Serial communication system formed by frequency converter and independent control circuit - Google Patents
Serial communication system formed by frequency converter and independent control circuit Download PDFInfo
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Abstract
The invention discloses a serial communication system formed by a frequency converter and an independent control circuit, which comprises a control interface, a frequency conversion control circuit unit, a programmable controller unit, a non-protocol control frequency conversion auxiliary unit, a motor regulation and control circuit unit and a communication network unit, wherein the control interface is connected with the programmable controller unit; the frequency conversion control circuit unit ensures the stability and diversity of frequency conversion control by dividing the frequency conversion control circuit into a non-protocol data transmission module, a parallel data transmission module and a network data transmission module; the high-power microwave communication solves the smoothness of information transmission under the condition of emergency communication, and the noise interference in the motor control process is eliminated by the aid of a sensor noise modeling mode. The invention realizes the realization of multi-channel frequency conversion by an independent upper controller, simultaneously ensures the stability and the data reliability of data transmission by assisting the mode of realizing emergency communication and noise modeling by high-power microwaves, and strengthens the multi-channel parallel capability of the independent controller.
Description
This patent is the divisional application, and the information of former application is as follows, the name: a serial communication system formed by a frequency converter and an independent control circuit has the following application numbers: 2019101481995, filing date: 2019-2-28.
Technical Field
The invention relates to a signal frequency conversion technology, in particular to a serial communication system formed by a frequency converter and an independent control circuit.
Background
With the continuous rising of industrial field control technology and control level, the control of motor signals is realized through a frequency converter, so that the technical level of enriching the signal transmission complexity of a communication network is also continuously promoted. This mode of serial communication via direct connection of the transducer to the controller has become increasingly popular.
However, due to the high complexity of communication means and communication contents, the current independent frequency conversion mode cannot meet the signal construction of a mature communication network. At present, the mainstream solution used in the market is to perform secondary processing on signals by using control circuits of different operation modes aiming at the same frequency conversion mode, so as to complete complex communication. This approach has a high degree of information data transfer, but with the attendant complexity of controller circuit design and high circuit maintenance costs.
In order to maximize the economic benefit, the generation mode of the frequency conversion signal can be improved, and a plurality of different frequency conversion modes can be uniformly managed and controlled by using independent controller circuits. The accidental communication channel blockage caused by the mode change and the redundant noise interference caused by independent control can be solved by a method of algorithm control and establishing an instant signal auxiliary transmission channel.
Accordingly, the related art is continuously being researched and enriched.
Disclosure of Invention
The purpose of the invention is as follows: a serial communication system composed of a frequency converter and an independent control circuit is provided to solve the above problems.
The technical scheme is as follows: a serial communication system formed by a frequency converter and an independent control circuit comprises a control interface, a frequency conversion control circuit unit, a programmable controller unit, a non-protocol control frequency conversion auxiliary unit, a motor regulation and control circuit unit and a communication network unit;
the interface is controlled to realize human-computer data interaction, and the design of a system operation interface is finished through simplified key indication;
the frequency conversion control circuit unit comprises a three-way frequency conversion master control circuit, and the operation mode of an internal frequency conversion module is changed according to different current indications received by the input port, so that three kinds of frequency conversion signal control which can be performed in parallel are completed, and a motor is further controlled to complete different regulation and control instructions;
the programmable controller unit takes an independent control circuit as an operation center of the whole device, and completes the operation instructions of different communication units in a cooperative way by transmitting different current instructions to the variable frequency control circuit unit;
the non-protocol control frequency conversion auxiliary unit is used as an initial module set by the device to assist the operation of frequency conversion, can finish the basic regulation and control of frequency conversion signals, exists in a default mode of the device, and automatically operates when no external current signal is changed;
the motor regulating and controlling circuit unit receives the control of the frequency conversion signal and completes the motor designation command;
the communication network unit is used for uniformly receiving the motor signals and the variable frequency control signals, performing noise removal work on the two paths of signals in a sensor noise modeling mode, and meanwhile, realizing the use of emergency communication in a high-power microwave mode, and realizing the data accuracy of the independent control circuit to the maximum extent;
the three-way frequency conversion master control circuit is characterized by comprising a non-protocol data transmission module, a parallel data transmission module and a network data transmission module;
the non-protocol data transmission module comprises an integrated chip U1, a rectifier U2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, an inductor L1, an inductor L2, an inductor L3, a diode D1, a diode D2, a triode Q1 and a triode Q2, wherein a first pin of the rectifier U2 is connected with a voltage signal Vin, a second pin of the rectifier U2 is connected with a ninth pin of the integrated chip U1, a third pin of the rectifier U2 is grounded, a sixteenth pin of the integrated chip U1 is connected with one end of the resistor R1, a fifteenth pin of the integrated chip U1 is connected with one end of the resistor R1, a thirteenth pin of the integrated chip U72 is connected with one end of the resistor R1, and the other end of the resistor R1 is connected with the other end of the resistor R1, The other ends of the resistors R3 are all grounded, the eleventh pin of the integrated chip U1 is connected with a current signal I12, the fourth pin of the integrated chip U1 is connected with a current signal I75, the third pin of the integrated chip U1 is connected with a current signal I150, the seventeenth pin of the integrated chip U1 is connected with one end of the resistor R4, the other end of the resistor R4 is connected with one end of the capacitor C1, one end of the resistor R5 and one end of the capacitor C2, the other end of the capacitor C2 is grounded, the other end of the resistor R5 is connected with the other end of the capacitor C1 and the second pin of the integrated chip U1, the eighteenth pin of the integrated chip U1 is connected with one end of the inductor L1, the other end of the inductor L1 is connected with one end of the capacitor C3, the other end of the capacitor C3 is connected with the emitter of the transistor Q1, a collector of the transistor Q1 is connected to a cathode of the diode D1, an anode of the diode D1 is grounded, a base of the transistor Q1 is connected to one end of the inductor L2 and one end of the resistor R6, respectively, the other end of the inductor L2 is connected to the first pin of the ic U1, the fifth pin of the ic U1 is connected to one end of the resistor R8, the other end of the resistor R8 is grounded, the other end of the resistor R6 is connected to the twentieth pin of the ic U1, the sixth pin of the ic U1 is connected to an anode of the diode D2, a cathode of the diode D2 is connected to the seventh pin of the ic U1 and the current signal Iout1, the eighth pin of the ic U1 is connected to one end of the inductor L3, and the other end of the inductor L3 is connected to an emitter of the transistor Q2, a base of the triode Q2 is connected to a nineteenth pin of the ic U1, a collector of the triode Q2 is connected to one end of the capacitor C4 and one end of the capacitor C5, respectively, the other end of the capacitor C4 is connected to one end of the resistor R7, the other end of the resistor R7 is connected to a tenth pin of the ic U1, the other end of the capacitor C5 is connected to one end of the resistor R9, the other end of the resistor R9 is connected to a twelfth pin of the ic U1, and a fourteenth pin of the ic U1 is connected to the voltage signal U6.2;
the parallel data transmission module comprises a transformer TR1, an operational amplifier U3, an operational amplifier U4, an adjustable resistor VR1, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, an inductor L10, a diode D10 and a triode Q10, wherein a third pin of the operational amplifier U10 is respectively connected with one end of the resistor R10, one end of the resistor R10 and a current signal I10, the other end of the resistor R10 is adjustably connected with one end of the resistor VR 10, and the other end of the adjustable resistor VR 10 is respectively connected with an anode of the diode R10 and a positive pole of the diode R10, a cathode of the diode D4 is connected to a cathode of the diode D5 and one end of the resistor R12, a cathode of the resistor R12 is connected to a first pin of the transformer TR1, a second pin of the transformer TR1 is connected to one end of the capacitor C8 and a current signal Iout1, a second pin of the capacitor C8 is connected to a second end of the resistor R14, a sixth pin of the operational amplifier U3 and one end of the capacitor C9, a fourth pin of the operational amplifier U3 and a seventh pin of the operational amplifier U3 are both open-circuited, a second pin of the operational amplifier U3 is connected to one end of the resistor R17, a second end of the resistor R17 is connected to one end of the inductor L6, a second end of the inductor L6 is connected to one end of the inductor L7 and an anode of the diode D8, and a cathode of the diode D8 is connected to a cathode of the other end of the capacitor C9, One end of the capacitor C10 and one end of the resistor R15 are connected, the other end of the inductor L7 is connected to one end of the resistor R19, the other end of the resistor R19 is grounded to the anode of the diode D6, the cathode of the diode D6 is connected to the second pin of the operational amplifier U4, the other end of the capacitor C10 is connected to one end of the resistor R18, the other end of the resistor R18 is connected to the third pin of the operational amplifier U4, the other end of the resistor R15 is connected to the sixth pin of the operational amplifier U4 and one end of the resistor R20, the fourth pin of the operational amplifier U4 and the seventh pin of the operational amplifier U4 are both open-circuited, the other end of the resistor R20 is connected to the current signal Iout2, the third pin of the transformer TR1 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to one end of the capacitor C6, The negative electrode of the diode D3 is connected, the other end of the capacitor C6 is grounded, the positive electrode of the diode D3 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to one end of the capacitor C7 and the collector of the triode Q3, the emitter of the triode Q3 is grounded, the base of the triode Q3 is connected to one end of the inductor L4, the other end of the inductor L4 is connected to the other end of the capacitor C7 and one end of the inductor L5, and the other end of the inductor L5 is connected to the fourth pin of the transformer TR 1;
the network data transmission module comprises a transformer TR2, an integrated chip U5, an operational amplifier U5, an adjustable resistor VR2, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor R28, a resistor R29, a resistor R30, a resistor R31, a resistor R32, a capacitor C32, an inductor L32, a diode D32, a triode Q32, an MOS tube Q32 and an MOS tube Q32, wherein one end of the resistor R32 is connected with a current signal I32, the other end of the resistor R32 is connected with a third pin of the operational amplifier U32, a fourth pin of the operational amplifier U32 is connected with a sixth pin of the operational amplifier U32, and a fourth pin of the operational amplifier U32 are connected with a sixth pin of the operational amplifier U32, and a fourth pin of the operational amplifier U36, A current signal Iout3 is connected, the second pin of the operational amplifier U6 is connected to one end of the resistor R31 and the D-pole of the MOS transistor Q5, the other end of the resistor R31 is connected to one end of the capacitor C16 and one end of the resistor R32, the other end of the capacitor C16 is grounded, the other end of the resistor R32 is connected to one end of the adjustable resistor VR2, the other end of the adjustable resistor VR2 is connected to one end of the resistor R29 and one end of the resistor R34, the other end of the resistor R29 is connected to the first pin of the transformer TR2, the other end of the resistor R34 is connected to one end of the inductor L11 and one end of the inductor L10, the other end of the inductor L10 is connected to the second pin of the transformer TR2, the other end of the inductor L11 is connected to the eighth pin of the integrated chip U5, and the third pin of the transformer TR2 is connected to one end of the capacitor C11, the other end of the capacitor C11 is connected to one end of the capacitor C12 and one end of the resistor R21, the other end of the resistor R21 is connected to the base of the transistor Q4, the collector of the transistor Q4 is connected to one end of the resistor R25, the other end of the resistor R25 is connected to the G-pole of the MOS transistor Q5, one end of the resistor R26 is connected to the S-pole of the MOS transistor Q5, the other end of the resistor R26 is connected to the G-pole of the MOS transistor Q6, the S-pole of the MOS transistor Q6 is connected to one end of the capacitor C14 and one end of the capacitor C15, the other end of the capacitor C14 is connected to one end of the resistor R27 and one end of the resistor R28, the other end of the resistor R27 is connected to the fifteenth pin of the integrated chip U5, the other end of the resistor R28 is connected to the tenth pin of the integrated chip U637, and one end of the capacitor C15 is connected to the L8, the other end of the inductor L8 is connected to a fourteenth pin of the ic U5, the emitter of the triode Q4 is connected to the cathode of the diode D7 and the third pin of the ic U5, respectively, the anode of the diode D7 is connected to one end of the resistor R23, the other end of the resistor R23 is connected to the fourth pin of the transformer TR2, the other end of the capacitor C12 is connected to one end of the resistor R22, the other end of the resistor R22 is connected to the second pin of the ic U5 and one end of the resistor R24, the other end of the resistor R24 is connected to one end of the capacitor C13 and one end of the inductor L9, the other end of the capacitor C13 is grounded, the other end of the inductor L9 is connected to the fifth pin of the transformer TR2, the first pin of the ic U5 is connected to the current signal Iout1, and the sixteenth pin of the ic 5 is connected to the current signal Iout2, a ninth pin of the integrated chip U5 is connected with a current signal Iout3, a fifth pin of the integrated chip U5 is grounded, a fourth pin of the integrated chip U5 is connected with a voltage signal VSS, a thirteenth pin of the integrated chip U5 is connected with a voltage signal VDD, a sixth pin of the integrated chip U5 is connected with the current signal Iout, and a seventh pin of the integrated chip U5 and an eleventh pin of the integrated chip U5 are both open circuits.
According to one aspect of the invention, the integrated chip U1 is AD693, and is connected to the non-protocol-controlled frequency conversion auxiliary unit through a current input terminal, so as to implement three-way frequency conversion of the frequency conversion signal in a default state.
According to one aspect of the invention, the transformer TR1 is a four-pin transformer, and is controlled by the current signal Iout1 and the variable resistance control override branch circuit to complete parallel data transmission, so as to realize two-way parallel frequency conversion signal control.
According to one aspect of the present invention, the transformer TR2 is a two-input three-output transformer, and is controlled by a twelve-way variable frequency signal through a three-output cross connection and a single current branch in parallel.
According to one aspect of the invention, the MOS transistor Q5 and the MOS transistor Q6 form a source electrode series structure, and are connected with a current amplification port of the operational amplifier U6, so that stable output of the twelve paths of variable frequency signals is achieved.
According to one aspect of the invention, the integrated chip U5 is of the type ADG1211, and under the control of the voltage signal VDD and the voltage signal VSS, the total control of output signals of three frequency conversion modes is completed, and the switching of the frequency conversion modes can be completed through simple command current.
A communication method realized by high-power microwaves directly uses the high-power microwaves to transmit communication data when a conventional communication channel is blocked and a frequency conversion signal is in disorder, so that communication blockage caused by insufficient communication propagation modes is avoided, and the method specifically comprises the following steps:
and 3, feeding the restored variable frequency signal into the variable frequency control circuit unit to perform feedback detection of the signal, and comparing the result of the secondarily output variable frequency signal with the result of the initial variable frequency signal to complete the construction and self-detection of the communication system.
And 4, completing the recovery of the communication signal.
According to an aspect of the present invention, the mutual self-checking process in step 12 may adjust the self-checking accuracy by changing the bit number confirmation criterion, and the highest accuracy mode is a standard according to which the four-bit signal is self-checked.
A sensor noise modeling method is used for modeling aiming at four noise signals which are easy to appear in the receiving and sending processes of variable frequency signals, and a noise elimination method is completed according to an empirical formula, and comprises the following specific steps:
and 3, eliminating the noise of the received frequency conversion signals with higher strength by using a noise reduction formula.
According to one aspect of the invention, the empirical formula is summarized under the condition of reference error accumulation, and specifically includes the comprehensive calculation of a state vector and a covariance matrix.
Has the advantages that: the invention can solve the complex flow that the multi-channel controller needs to respectively control the frequency conversion signals in the prior art, can directly complete the replacement of different frequency conversion modes through the independent control circuit by arranging the frequency conversion signal control circuits which are parallel, network and non-protocol transmission, and can further solve the problems of disordered frequency conversion mode switching and large noise interference caused by the total control of the independent controller due to the establishment of the high-power microwave and noise modes.
Drawings
FIG. 1 is a block diagram of an implementation of the present invention.
FIG. 2 is a schematic diagram of a three-way variable frequency master control circuit of the present invention.
Fig. 2(a) is a non-protocol data transmission module of the three-way frequency conversion master control circuit of the invention.
FIG. 2(b) is a parallel data transmission module of the three-way frequency conversion master control circuit of the present invention.
Fig. 2(c) is a network data transmission module of the three-way frequency conversion master control circuit of the invention.
Fig. 3 is a schematic diagram of frequency-converted signal modulation of high-power microwaves in accordance with the present invention.
FIG. 4 is a modeling diagram of the sensor noise pattern of the present invention.
Detailed Description
As shown in fig. 1, in this embodiment, a serial communication system formed by a frequency converter and an independent control circuit includes a control interface, a frequency conversion control circuit unit, a programmable controller unit, a non-protocol control frequency conversion auxiliary unit, a motor regulation circuit unit, and a communication network unit;
the interface is controlled to realize human-computer data interaction, and the design of a system operation interface is finished through simplified key indication;
the frequency conversion control circuit unit comprises a three-way frequency conversion master control circuit, and the operation mode of an internal frequency conversion module is changed according to different current indications received by the input port, so that three kinds of frequency conversion signal control which can be performed in parallel are completed, and a motor is further controlled to complete different regulation and control instructions;
the programmable controller unit takes an independent control circuit as an operation center of the whole device, and completes the operation instructions of different communication units in a cooperative way by transmitting different current instructions to the variable frequency control circuit unit;
the non-protocol control frequency conversion auxiliary unit is used as an initial module set by the device to assist the operation of frequency conversion, can finish the basic regulation and control of frequency conversion signals, exists in a default mode of the device, and automatically operates when no external current signal is changed;
the motor regulating and controlling circuit unit receives the control of the frequency conversion signal and completes the motor designation command;
the communication network unit is used for uniformly receiving the motor signals and the variable frequency control signals, performing noise removal work on the two paths of signals in a sensor noise modeling mode, and meanwhile, realizing the use of emergency communication in a high-power microwave mode, and realizing the data accuracy of the independent control circuit to the maximum extent;
as shown in fig. 2, the three-way frequency conversion master control circuit is characterized by comprising a non-protocol data transmission module, a parallel data transmission module and a network data transmission module;
as shown in fig. 2(a), the non-protocol data transmission module includes an integrated chip U1, a rectifier U1, a resistor R1, a capacitor C1, an inductor L1, a diode D1, a transistor Q1, and a transistor Q1, where a first pin of the rectifier U1 is connected to a voltage signal Vin, a second pin of the rectifier U1 is connected to a ninth pin of the integrated chip U1, a third pin of the rectifier U1 is connected to ground, a sixteenth pin of the integrated chip U1 is connected to one end of the resistor R1, a fifteenth pin of the integrated chip U1 is connected to one end of the resistor R1, and a thirteenth pin of the integrated chip 1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the other end of the resistor R2 and the other end of the resistor R3, the eleventh pin of the integrated chip U1 is connected to a current signal I12, the fourth pin of the integrated chip U1 is connected to a current signal I75, the third pin of the integrated chip U1 is connected to a current signal I150, the seventeenth pin of the integrated chip U1 is connected to one end of the resistor R4, the other end of the resistor R4 is connected to one end of the capacitor C1, one end of the resistor R5 and one end of the capacitor C2, the other end of the capacitor C2 is connected to ground, the other end of the resistor R5 is connected to the other end of the capacitor C1 and the second pin of the integrated chip U1, the eighteenth pin of the integrated chip U1 is connected to one end of the inductor L1, the other end of the inductor L1 is connected to one end of the capacitor C3, the other end of the capacitor C3 is connected to an emitter of the transistor Q1, a collector of the transistor Q1 is connected to a cathode of the diode D1, an anode of the diode D1 is grounded, a base of the transistor Q1 is connected to one end of the inductor L2 and one end of the resistor R6, the other end of the inductor L2 is connected to the first pin of the ic U1, the fifth pin of the ic U1 is connected to one end of the resistor R8, the other end of the resistor R8 is grounded, the other end of the resistor R6 is connected to the twentieth pin of the ic U1, the sixth pin of the ic U1 is connected to an anode of the diode D2, a cathode of the diode D2 is connected to the seventh pin of the ic U1 and the current signal Iout1, the eighth pin of the ic U1 is connected to one end of the inductor L3, the other end of the inductor L3 is connected to an emitter of the transistor Q2, a base of the transistor Q2 is connected to a nineteenth pin of the integrated chip U1, a collector of the transistor Q2 is connected to one end of the capacitor C4 and one end of the capacitor C5, the other end of the capacitor C4 is connected to one end of the resistor R7, the other end of the resistor R7 is connected to a tenth pin of the integrated chip U1, the other end of the capacitor C5 is connected to one end of the resistor R9, the other end of the resistor R9 is connected to a twelfth pin of the integrated chip U1, and a fourteenth pin of the integrated chip U1 is connected to a voltage signal U6.2;
as shown in fig. 2(b), the parallel data transmission module includes a transformer TR1, an operational amplifier U3, an operational amplifier U4, an adjustable resistor VR1, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, an inductor L4, an inductor L5, a diode D5, and a triode Q5, a third pin of the operational amplifier U5 is respectively connected to one end of the resistor R5, and one end of the adjustable resistor VR 5, and the other end of the adjustable resistor R5 is respectively connected to one end of the positive pole of the positive resistor R5, and the positive pole of the adjustable resistor VR 5, and the positive pole of the diode R5, and the positive pole of the adjustable resistor R5 are, The anode of the diode D5 is connected, the cathode of the diode D4 is connected to the cathode of the diode D5 and one end of the resistor R12, the other end of the resistor R12 is connected to the first pin of the transformer TR1, the second pin of the transformer TR1 is connected to one end of the capacitor C8 and the current signal Iout1, the other end of the capacitor C8 is connected to the other end of the resistor R14, the sixth pin of the operational amplifier U3 and one end of the capacitor C9, the fourth pin of the operational amplifier U3 and the seventh pin of the operational amplifier U3 are both open-circuited, the second pin of the operational amplifier U3 is connected to one end of the resistor R17, the other end of the resistor R17 is connected to one end of the inductor L6, and the other end of the inductor L6 is connected to one end of the inductor L7 and the anode of the diode D8, a cathode of the diode D8 is connected to the other end of the capacitor C9, one end of the capacitor C10, and one end of the resistor R15, respectively, the other end of the inductor L7 is connected to one end of the resistor R19, the other end of the resistor R19 and an anode of the diode D6 are both grounded, a cathode of the diode D6 is connected to the second pin of the operational amplifier U4, the other end of the capacitor C10 is connected to one end of the resistor R18, the other end of the resistor R18 is connected to the third pin of the operational amplifier U4, the other end of the resistor R15 is connected to the sixth pin of the operational amplifier U4 and one end of the resistor R20, the fourth pin of the operational amplifier U4 and the seventh pin of the operational amplifier U4 are both open-circuited, the other end of the resistor R20 is connected to the current signal Iout2, the third pin of the transformer TR1 is connected to one end of the resistor R10, the other end of the resistor R10 is connected to one end of the capacitor C6 and the negative electrode of the diode D3, the other end of the capacitor C6 is grounded, the positive electrode of the diode D3 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to one end of the capacitor C7 and the collector of the transistor Q3, the emitter of the transistor Q3 is grounded, the base of the transistor Q3 is connected to one end of the inductor L4, the other end of the inductor L4 is connected to the other end of the capacitor C7 and one end of the inductor L5, and the other end of the inductor L5 is connected to the fourth pin of the transformer TR 1;
as shown in fig. 2(C), the network data transmission module includes a transformer TR2, an integrated chip U5, an operational amplifier U5, an adjustable resistor VR2, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor R28, a resistor R29, a resistor R30, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a capacitor C11, a capacitor C12, an inductor L12, a diode D12, a triode Q12, a MOS Q12, and a MOS Q12, wherein one end of the resistor R12 is connected to the current signal I12, the other end of the resistor R12 is connected to a third pin of the operational amplifier U12, and a seventh pin of the operational amplifier U12 is connected to the seventh pin of the operational amplifier U12, the other end of the resistor R30 is connected to the D-pole of the MOS transistor Q6 and the current signal Iout3, the second pin of the operational amplifier U6 is connected to one end of the resistor R31 and the D-pole of the MOS transistor Q5, the other end of the resistor R31 is connected to one end of the capacitor C16 and one end of the resistor R32, the other end of the capacitor C16 is grounded, the other end of the resistor R32 is connected to one end of the adjustable resistor VR2, the other end of the adjustable resistor VR2 is connected to one end of the resistor R29 and one end of the resistor R34, the other end of the resistor R29 is connected to the first pin of the transformer TR2, the other end of the resistor R34 is connected to one end of the inductor L11 and one end of the inductor L10, the other end of the inductor L10 is connected to the second pin of the transformer TR2, and the other end of the inductor L11 is connected to the eighth pin 5 of the integrated chip, a third pin of the transformer TR2 is connected to one end of the capacitor C11, the other end of the capacitor C11 is connected to one end of the capacitor C12 and one end of the resistor R21, the other end of the resistor R21 is connected to a base of the transistor Q4, a collector of the transistor Q4 is connected to one end of the resistor R25, the other end of the resistor R25 is connected to a G-pole of the MOS transistor Q5, one end of the resistor R26 is connected to an S-pole of the MOS transistor Q5, the other end of the resistor R26 is connected to a G-pole of the MOS transistor Q6, an S-pole of the MOS transistor Q6 is connected to one end of the capacitor C14 and one end of the capacitor C15, the other end of the capacitor C14 is connected to one end of the resistor R27 and one end of the resistor R28, the other end of the resistor R27 is connected to a fifteenth pin of the integrated chip U5, and the other end of the resistor R28 is connected to a tenth pin of the integrated chip U5, one end of the capacitor C15 is connected to one end of the inductor L8, the other end of the inductor L8 is connected to the fourteenth pin of the ic U5, the emitter of the triode Q4 is connected to the cathode of the diode D7 and the third pin of the ic U5, the anode of the diode D7 is connected to one end of the resistor R23, the other end of the resistor R23 is connected to the fourth pin of the transformer TR2, the other end of the capacitor C12 is connected to one end of the resistor R22, the other end of the resistor R22 is connected to the second pin of the ic U5 and one end of the resistor R24, the other end of the resistor R24 is connected to one end of the capacitor C13 and one end of the inductor L9, the other end of the capacitor C13 is grounded, the other end of the inductor L9 is connected to the fifth pin of the transformer TR2, and the first pin of the ic 5 is connected to the signal Iout1, a sixteenth pin of the integrated chip U5 is connected to a current signal Iout2, a ninth pin of the integrated chip U5 is connected to the current signal Iout3, a fifth pin of the integrated chip U5 is grounded, a fourth pin of the integrated chip U5 is connected to a voltage signal VSS, a thirteenth pin of the integrated chip U5 is connected to the voltage signal VDD, a sixth pin of the integrated chip U5 is connected to the current signal Iout, and a seventh pin of the integrated chip U5 and an eleventh pin of the integrated chip U5 are both open circuits.
In a further embodiment, the integrated chip U1 is of type AD693, and is connected to the non-protocol-controlled frequency conversion auxiliary unit through a current input terminal, so as to implement three-way frequency conversion of the frequency conversion signal in a default state.
In a further embodiment, the current signal I12, the current signal I75 and the current signal I150 are respectively connected with the current input port of the integrated chip U1, so that the chip operates with stable current support; the resistor R1 is respectively connected with the resistor R2 and the resistor R3 in parallel to finish the equipartition input of current, and the equipartition input is used as a first frequency conversion branch circuit; the resistor R4, the resistor R5, the capacitor C1 and the capacitor C2 form a second frequency conversion branch, wherein the resistor R5 and the capacitor C1 are connected in parallel to complete an interruptible series branch, so that charge accumulation is improved for frequency conversion signals; the triode Q2, the capacitor C4, the capacitor C5, the resistor R9 and the inductor L3 form a third frequency conversion branch, when current is output from the tenth pin of the integrated chip U1, the current respectively passes through the parallel capacitor branch formed by the capacitor C4 and the capacitor C5 and then reaches the collector of the triode Q2, and the current is output by the emitter of the triode Q2.
In a further embodiment, the transformer TR1 is a four-pin transformer, and the two-way parallel frequency conversion signal control is realized by completing the transmission of parallel data under the control of the current signal Iout1 and the variable resistance control override branch.
In a further embodiment, the diode D4 and the diode D5 form a parallel circuit and are respectively connected in series with the resistor R13 and the resistor R12 to complete the transformation of the input voltage; the current signal Iout is connected with a second pin of the transformer TR1 to complete stable current basic setting; under the regulation of the variable resistor VR1, the transmission terminal of the transformer TR1 can transmit two different variable frequency voltage signals.
In a further embodiment, the transformer TR2 is a two-input three-output transformer, and is controlled by a twelve-way frequency conversion signal through a three-output cross-connect and a single current branch in parallel.
In a further embodiment, the capacitor C11 and the resistor R21 are connected in series and then connected to the base of the transistor Q4 to complete a primary frequency-variable signal output, and two secondary frequency-variable signal outputs are respectively completed at the emitter of the transistor Q4 and the collector of the transistor Q4; the collector of the triode Q4 is connected with the resistor R25 in series and then connected with the G pole of the MOS transistor Q5, and the output of two paths of three-level variable frequency signals is completed through the S pole of the MOS transistor Q5 and the D pole of the MOS transistor Q5.
In a further embodiment, the network data transmission modules all adopt a cross tree-shaped frequency conversion output mode, and complete output of twelve paths of frequency conversion signals in a cascading manner.
In a further embodiment, the MOS transistor Q5 and the MOS transistor Q6 form a source series structure, and are connected to the current amplification port of the operational amplifier U6, so as to complete stable output of the twelve paths of variable frequency signals.
In a further embodiment, the integrated chip U5 is of the type ADG1211, and the total control of the output signals of the three frequency conversion modes is completed under the control of the voltage signal VDD and the voltage signal VSS, so that the switching of the frequency conversion modes can be completed by a simple command current.
The invention relates to a communication method realized by high-power microwaves, which only uses a single controller, can cause the switching disorder of a frequency conversion mode due to the error accumulation of a frequency conversion circuit, further causes the blockage of a conventional communication channel, and needs to directly use the high-power microwaves to transmit communication data, thereby avoiding the communication blockage caused by insufficient communication propagation mode, and the specific steps are as follows:
and 3, feeding the restored variable frequency signal into the variable frequency control circuit unit to perform feedback detection of the signal, and comparing the result of the secondarily output variable frequency signal with the result of the initial variable frequency signal to complete the construction and self-detection of the communication system.
And 4, completing the recovery of the communication signal.
In a further embodiment, the mutual self-checking process in step 12 may adjust the self-checking accuracy by changing the bit number confirmation criterion, and the highest accuracy mode is a standard for self-checking four-bit signals.
In a further embodiment, as shown in FIG. 3, the signal D2 is a display mode of the signal D1 after signal modulation, which can significantly reduce the period of the signal, thereby highly decomposing the signal pulse and enhancing the accuracy of data recording.
A sensor noise modeling method is used for modeling aiming at four noise signals which are easy to appear in the receiving and sending processes of variable frequency signals, so that the phenomenon of redundant noise signal interference caused by the use of an independent controller is eliminated, and a noise elimination method is completed according to an empirical formula, and comprises the following specific steps:
and 3, eliminating the noise of the received frequency conversion signals with higher strength by using a noise reduction formula.
In a further embodiment, as shown in fig. 4, the empirical formulas are summarized under the condition of reference error accumulation, specifically including the comprehensive calculation of the state vector and the covariance matrix; statistical classes of sensor noise include white gaussian noise, error noise caused by unexpected objects, noise caused by undetected objects, and random unexpected noise.
In summary, the present invention has the following advantages: the switching of three frequency conversion signal modes can be completed by only using one independent controller, so that the complex circuit design required by a plurality of controller ports is greatly reduced; the three independent frequency conversion modes can be independently completed through different circuit units, the interference degree is low, and the completion degree is high; interference signals caused by the use of the independent controller are analyzed and removed in a high-power microwave communication and noise modeling mode, so that the completeness and the feasibility of the whole design are higher.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. The invention is not described in detail in order to avoid unnecessary repetition.
Claims (7)
1. A serial communication system formed by a frequency converter and an independent control circuit comprises a control interface, a frequency conversion control circuit unit, a programmable controller unit, a non-protocol control frequency conversion auxiliary unit, a motor regulation and control circuit unit and a communication network unit;
the interface is controlled to realize human-computer data interaction, and the design of a system operation interface is finished through simplified key indication;
the frequency conversion control circuit unit comprises a three-way frequency conversion master control circuit, and the operation mode of an internal frequency conversion module is changed according to different current indications received by the input port, so that three kinds of frequency conversion signal control which can be performed in parallel are completed, and a motor is further controlled to complete different regulation and control instructions;
the programmable controller unit takes an independent control circuit as an operation center of the whole device, and completes the operation instructions of different communication units in a cooperative way by transmitting different current instructions to the variable frequency control circuit unit;
the non-protocol control frequency conversion auxiliary unit is used as an initial module set by the device to assist the operation of frequency conversion, can finish the basic regulation and control of frequency conversion signals, exists in a default mode of the device, and automatically operates when no external current signal is changed;
the motor regulating and controlling circuit unit receives the control of the frequency conversion signal and completes the motor designation command;
the communication network unit is used for uniformly receiving the motor signals and the variable frequency control signals, performing noise removal work on the two paths of signals in a sensor noise modeling mode, and meanwhile, realizing the use of emergency communication in a high-power microwave mode, and realizing the data accuracy of the independent control circuit to the maximum extent;
the three-way frequency conversion master control circuit is characterized by comprising a non-protocol data transmission module, a parallel data transmission module and a network data transmission module;
the non-protocol data transmission module comprises an integrated chip U1, a rectifier U2, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, an inductor L1, an inductor L2, an inductor L3, a diode D1, a diode D2, a triode Q1 and a triode Q2, wherein a first pin of the rectifier U2 is connected with a voltage signal Vin, a second pin of the rectifier U2 is connected with a ninth pin of the integrated chip U1, a third pin of the rectifier U2 is grounded, a sixteenth pin of the integrated chip U1 is connected with one end of the resistor R1, a fifteenth pin of the integrated chip U1 is connected with one end of the resistor R1, a thirteenth pin of the integrated chip U72 is connected with one end of the resistor R1, and the other end of the resistor R1 is connected with the other end of the resistor R1, The other ends of the resistors R3 are all grounded, the eleventh pin of the integrated chip U1 is connected with a current signal I12, the fourth pin of the integrated chip U1 is connected with a current signal I75, the third pin of the integrated chip U1 is connected with a current signal I150, the seventeenth pin of the integrated chip U1 is connected with one end of the resistor R4, the other end of the resistor R4 is connected with one end of the capacitor C1, one end of the resistor R5 and one end of the capacitor C2, the other end of the capacitor C2 is grounded, the other end of the resistor R5 is connected with the other end of the capacitor C1 and the second pin of the integrated chip U1, the eighteenth pin of the integrated chip U1 is connected with one end of the inductor L1, the other end of the inductor L1 is connected with one end of the capacitor C3, the other end of the capacitor C3 is connected with the emitter of the transistor Q1, a collector of the transistor Q1 is connected to a cathode of the diode D1, an anode of the diode D1 is grounded, a base of the transistor Q1 is connected to one end of the inductor L2 and one end of the resistor R6, respectively, the other end of the inductor L2 is connected to the first pin of the ic U1, the fifth pin of the ic U1 is connected to one end of the resistor R8, the other end of the resistor R8 is grounded, the other end of the resistor R6 is connected to the twentieth pin of the ic U1, the sixth pin of the ic U1 is connected to an anode of the diode D2, a cathode of the diode D2 is connected to the seventh pin of the ic U1 and the current signal Iout1, the eighth pin of the ic U1 is connected to one end of the inductor L3, and the other end of the inductor L3 is connected to an emitter of the transistor Q2, a base of the triode Q2 is connected to a nineteenth pin of the ic U1, a collector of the triode Q2 is connected to one end of the capacitor C4 and one end of the capacitor C5, respectively, the other end of the capacitor C4 is connected to one end of the resistor R7, the other end of the resistor R7 is connected to a tenth pin of the ic U1, the other end of the capacitor C5 is connected to one end of the resistor R9, the other end of the resistor R9 is connected to a twelfth pin of the ic U1, and a fourteenth pin of the ic U1 is connected to the voltage signal U6.2;
the parallel data transmission module comprises a transformer TR1, an operational amplifier U3, an operational amplifier U4, an adjustable resistor VR1, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a capacitor C10, an inductor L10, a diode D10 and a triode Q10, wherein a third pin of the operational amplifier U10 is respectively connected with one end of the resistor R10, one end of the resistor R10 and a current signal I10, the other end of the resistor R10 is adjustably connected with one end of the resistor VR 10, and the other end of the adjustable resistor VR 10 is respectively connected with an anode of the diode R10 and a positive pole of the diode R10, a cathode of the diode D4 is connected to a cathode of the diode D5 and one end of the resistor R12, a cathode of the resistor R12 is connected to a first pin of the transformer TR1, a second pin of the transformer TR1 is connected to one end of the capacitor C8 and a current signal Iout1, a second pin of the capacitor C8 is connected to a second end of the resistor R14, a sixth pin of the operational amplifier U3 and one end of the capacitor C9, a fourth pin of the operational amplifier U3 and a seventh pin of the operational amplifier U3 are both open-circuited, a second pin of the operational amplifier U3 is connected to one end of the resistor R17, a second end of the resistor R17 is connected to one end of the inductor L6, a second end of the inductor L6 is connected to one end of the inductor L7 and an anode of the diode D8, and a cathode of the diode D8 is connected to a cathode of the other end of the capacitor C9, One end of the capacitor C10 and one end of the resistor R15 are connected, the other end of the inductor L7 is connected to one end of the resistor R19, the other end of the resistor R19 is grounded to the anode of the diode D6, the cathode of the diode D6 is connected to the second pin of the operational amplifier U4, the other end of the capacitor C10 is connected to one end of the resistor R18, the other end of the resistor R18 is connected to the third pin of the operational amplifier U4, the other end of the resistor R15 is connected to the sixth pin of the operational amplifier U4 and one end of the resistor R20, the fourth pin of the operational amplifier U4 and the seventh pin of the operational amplifier U4 are both open-circuited, the other end of the resistor R20 is connected to the current signal Iout2, the third pin of the transformer TR1 is connected to one end of the resistor R10, and the other end of the resistor R10 is connected to one end of the capacitor C6, The negative electrode of the diode D3 is connected, the other end of the capacitor C6 is grounded, the positive electrode of the diode D3 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to one end of the capacitor C7 and the collector of the triode Q3, the emitter of the triode Q3 is grounded, the base of the triode Q3 is connected to one end of the inductor L4, the other end of the inductor L4 is connected to the other end of the capacitor C7 and one end of the inductor L5, and the other end of the inductor L5 is connected to the fourth pin of the transformer TR 1;
the network data transmission module comprises a transformer TR2, an integrated chip U5, an operational amplifier U5, an adjustable resistor VR2, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a resistor R26, a resistor R27, a resistor R28, a resistor R29, a resistor R30, a resistor R31, a resistor R32, a capacitor C32, an inductor L32, a diode D32, a triode Q32, an MOS tube Q32 and an MOS tube Q32, wherein one end of the resistor R32 is connected with a current signal I32, the other end of the resistor R32 is connected with a third pin of the operational amplifier U32, a fourth pin of the operational amplifier U32 is connected with a sixth pin of the operational amplifier U32, and a fourth pin of the operational amplifier U32 are connected with a sixth pin of the operational amplifier U32, and a fourth pin of the operational amplifier U36, A current signal Iout3 is connected, the second pin of the operational amplifier U6 is connected to one end of the resistor R31 and the D-pole of the MOS transistor Q5, the other end of the resistor R31 is connected to one end of the capacitor C16 and one end of the resistor R32, the other end of the capacitor C16 is grounded, the other end of the resistor R32 is connected to one end of the adjustable resistor VR2, the other end of the adjustable resistor VR2 is connected to one end of the resistor R29 and one end of the resistor R34, the other end of the resistor R29 is connected to the first pin of the transformer TR2, the other end of the resistor R34 is connected to one end of the inductor L11 and one end of the inductor L10, the other end of the inductor L10 is connected to the second pin of the transformer TR2, the other end of the inductor L11 is connected to the eighth pin of the integrated chip U5, and the third pin of the transformer TR2 is connected to one end of the capacitor C11, the other end of the capacitor C11 is connected to one end of the capacitor C12 and one end of the resistor R21, the other end of the resistor R21 is connected to the base of the transistor Q4, the collector of the transistor Q4 is connected to one end of the resistor R25, the other end of the resistor R25 is connected to the G-pole of the MOS transistor Q5, one end of the resistor R26 is connected to the S-pole of the MOS transistor Q5, the other end of the resistor R26 is connected to the G-pole of the MOS transistor Q6, the S-pole of the MOS transistor Q6 is connected to one end of the capacitor C14 and one end of the capacitor C15, the other end of the capacitor C14 is connected to one end of the resistor R27 and one end of the resistor R28, the other end of the resistor R27 is connected to the fifteenth pin of the integrated chip U5, the other end of the resistor R28 is connected to the tenth pin of the integrated chip U637, and one end of the capacitor C15 is connected to the L8, the other end of the inductor L8 is connected to a fourteenth pin of the ic U5, the emitter of the triode Q4 is connected to the cathode of the diode D7 and the third pin of the ic U5, respectively, the anode of the diode D7 is connected to one end of the resistor R23, the other end of the resistor R23 is connected to the fourth pin of the transformer TR2, the other end of the capacitor C12 is connected to one end of the resistor R22, the other end of the resistor R22 is connected to the second pin of the ic U5 and one end of the resistor R24, the other end of the resistor R24 is connected to one end of the capacitor C13 and one end of the inductor L9, the other end of the capacitor C13 is grounded, the other end of the inductor L9 is connected to the fifth pin of the transformer TR2, the first pin of the ic U5 is connected to the current signal Iout1, and the sixteenth pin of the ic 5 is connected to the current signal Iout2, a ninth pin of the integrated chip U5 is connected with a current signal Iout3, a fifth pin of the integrated chip U5 is grounded, a fourth pin of the integrated chip U5 is connected with a voltage signal VSS, a thirteenth pin of the integrated chip U5 is connected with a voltage signal VDD, a sixth pin of the integrated chip U5 is connected with the current signal Iout, and a seventh pin of the integrated chip U5 and an eleventh pin of the integrated chip U5 are both open circuits;
the integrated chip U1 is AD693 in type, and is connected with the non-protocol control frequency conversion auxiliary unit through a current input end, so that three-way frequency conversion of a frequency conversion signal is realized in a default state;
the transformer TR1 is a four-pin transformer, and is used for completing the transmission of parallel data under the control of the current signal Iout1 and a variable resistor control override branch circuit, so that the control of a two-way parallel variable frequency signal is realized;
the transformer TR2 is a two-input three-output transformer, and realizes the control of a one-to-twelve-path frequency conversion signal by three-path output cross connection and single current branch circuit in parallel.
2. The serial communication system of claim 1, wherein the MOS transistor Q5 and the MOS transistor Q6 form a source series structure, and are connected to the current amplification port of the operational amplifier U6, so as to achieve stable output of the twelve-way frequency conversion signal.
3. The serial communication system of claim 1, wherein the integrated chip U5 is an ADG1211, and the integrated chip U5 can control the output signals of three frequency conversion modes under the control of a voltage signal VDD and a voltage signal VSS, and can switch the frequency conversion modes by a simple command current.
4. The communication method realized by the high-power microwaves is characterized in that when a conventional communication channel is blocked and a frequency conversion signal is in disorder, the high-power microwaves are directly used for communication data transmission, so that communication blockage caused by insufficient communication propagation modes is avoided, and the method specifically comprises the following steps:
step 1, modulating the received variable frequency signal by using pulse width;
step 11, establishing frequency conversion signal learning templates which are four-bit signals 0000, 0001 and 0010. cndot. 1111 respectively; six-bit signals 000000, 000001, 000010 · 11111111; eight-bit signals 00000000, 00000001, 00000010 · 11111111;
step 12, receiving the frequency conversion output signal, converting the frequency conversion output signal into a binary digital signal, and detecting the signals of the three unit modes so as to complete the mutual self-checking process of the three modes;
step 13, performing signal modulation on the detected variable-frequency output signal by using a pulse width signal;
step 2, decomposing a modulation signal by using a strong electromagnetic pulse, completing a signal display mode of converting a low period into a high period, finally determining an error signal of a variable frequency signal, taking the error signal as a head position, intercepting a minimum unit signal segment, and comparing and identifying the segment in a variable frequency signal learning template;
step 3, feeding the restored variable frequency signal into the variable frequency control circuit unit for signal feedback detection, and comparing the result of the secondarily output variable frequency signal with the result of the initial variable frequency signal to complete the construction and self-detection of the communication system;
and 4, completing the recovery of the communication signal.
5. The high power microwave communication method according to claim 4, wherein the mutual self-checking process in step 12 can adjust the self-checking accuracy by changing the bit number confirmation standard, and the highest accuracy mode is a standard according to which the four-bit signal is self-checked.
6. A sensor noise modeling method is characterized in that four noise signals which are easy to appear in the receiving and sending processes of variable frequency signals are modeled, and a noise elimination method is completed according to an empirical formula, and the method comprises the following specific steps:
step 1, establishing four different basic noise models;
step 2, according to an empirical formula, integrating the four noise modes by using a maximum expectation method to complete a final noise reduction formula;
and 3, eliminating the noise of the received frequency conversion signals with higher strength by using a noise reduction formula.
7. The method according to claim 4, wherein the empirical formula is summarized under the condition of reference error accumulation, and specifically includes a comprehensive calculation of a state vector and a covariance matrix.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010021199.1A CN111147057A (en) | 2019-02-28 | 2019-02-28 | Serial communication system formed by frequency converter and independent control circuit |
Applications Claiming Priority (2)
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| CN201910148199.5A CN109921765B (en) | 2019-02-28 | 2019-02-28 | Serial communication system formed by frequency converter and independent control circuit |
| CN202010021199.1A CN111147057A (en) | 2019-02-28 | 2019-02-28 | Serial communication system formed by frequency converter and independent control circuit |
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| CN202001348U (en) * | 2011-02-28 | 2011-10-05 | 宁波风机有限公司 | Frequency conversion control system of fan |
| FR2982111B1 (en) * | 2011-10-27 | 2014-07-25 | Cabasse | ACOUSTIC SPEAKER COMPRISING A COAXIAL SPEAKER WITH CONTROLLED AND VARIABLE DIRECTIVITY. |
| CN202814931U (en) * | 2012-09-22 | 2013-03-20 | 华南理工大学 | Self-adaption ultrasonic rail fault detection device based on frequency spectrum cognition |
| CN103607162B (en) * | 2013-12-11 | 2016-04-13 | 济南诺辉节能技术开发有限公司 | The online switching device shifter of frequency conversion power frequency |
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| CN109921765A (en) | 2019-06-21 |
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