CN111143135A - Test system - Google Patents

Test system Download PDF

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Publication number
CN111143135A
CN111143135A CN201811297918.1A CN201811297918A CN111143135A CN 111143135 A CN111143135 A CN 111143135A CN 201811297918 A CN201811297918 A CN 201811297918A CN 111143135 A CN111143135 A CN 111143135A
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CN
China
Prior art keywords
test
testing
motherboard
result
mainboard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811297918.1A
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Chinese (zh)
Inventor
张桂山
易春阳
刘彬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Giga Byte Technology Co Ltd
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Giga Byte Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Giga Byte Technology Co Ltd filed Critical Giga Byte Technology Co Ltd
Priority to CN201811297918.1A priority Critical patent/CN111143135A/en
Publication of CN111143135A publication Critical patent/CN111143135A/en
Pending legal-status Critical Current

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/22Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00Network arrangements or protocols for supporting network services or applications
    • H04L67/01Protocols
    • H04L67/06Protocols specially adapted for file transfer, e.g. file transfer protocol [FTP]
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2101/00Indexing scheme associated with group H04L61/00
    • H04L2101/60Types of network addresses
    • H04L2101/618Details of network addresses
    • H04L2101/622Layer-2 addresses, e.g. medium access control [MAC] addresses

Abstract

A test system for testing a motherboard includes a test fixture, a test board, a network device, and a storage medium. The test fixture provides a central processing unit and a memory module to be inserted in the mainboard. The storage medium is electrically connected with the mainboard, stores the operating system, the test program and the control program, and executes the following steps: accessing the MAC address of the mainboard by the operating system; executing a control program, driving the test board to send an analog signal to the mainboard to execute a first test flow, and generating a first test result by the test program after the control program is completed; and the operating system executes the test program, performs a second test process on the mainboard, and generates a second test result after the test process is completed. The operation system sends the first test result and the second test result respectively associated with the MAC address through the network equipment.

Description

Test system
Technical Field
The invention relates to the field of computers, in particular to a test system for a mainboard.
Background
In order to ensure the shipment quality of the motherboard, related tests, commonly known as burn-in, are usually performed before shipment. In the existing burn-in test, a person manually executes related test programs one by one according to various proposed test steps, and tests item by item. And the Pass/Fail determination is done manually by the operator on a term-by-term basis.
Under such test conditions, the execution of each program and the determination of the test result are all manually performed, and therefore, the operator needs to wait at the test site all the time to check the progress of the test. The whole working hours are longer and the burden is heavy. It is naturally easy to miss the erroneous measurement or erroneous judgment.
Disclosure of Invention
In view of the above, in order to solve the problems in the prior art, a testing system is provided for automatically testing a motherboard. The test system comprises a test fixture, a test board, a network device, and a storage medium. The test fixture supplies power to the mainboard and provides the central processing unit and the memory module to be inserted in the mainboard. The test board is electrically connected to the motherboard. The network equipment is electrically connected to the mainboard. The storage medium is electrically connected to the mainboard, the network equipment and the test board, stores the operating system, the test program and the control program, and is loaded and executed by the mainboard with the inserted central processing unit and the memory module to execute the following steps:
a Media Access Control (MAC) address for accessing a motherboard by an operating system; executing a control program, driving the test board to send a plurality of analog signals to the mainboard to execute a first test flow, when the first test flow is completed, generating a first test result by the test program, and sending the MAC address related to the first test result out by the operating system through the network equipment; and the operating system executes the test program, performs a second test process on the mainboard, generates a second test result after the test process is completed, and sends the MAC address related to the second test result out through the network equipment.
In some embodiments, the test system further includes a remote server, which receives and stores the MAC address, the first test result, and the second test result, and generates the test form according to the test result. Further, in some embodiments, the test system further comprises a database, and the remote server accesses the comparison table of the database and accesses the serial number of the motherboard corresponding to the MAC address.
Further, in some embodiments, the remote server generates the test forms in batches according to the serial number of the motherboard.
Further, in some embodiments, the first test result and the second test result have error information, and the remote server generates the error analysis table in batch according to the serial number of the motherboard, the error information of the first test result and the error information of the second test result. Furthermore, when the first test result or the second test result has error information, the remote server returns feedback information to the operating system, and the operating system performs the first test process or the second test process again according to the feedback information.
In some embodiments, the first test flow includes a voltage switch test, a switch test step, a restart test, and a Scratch To RAM (STR) test.
In some embodiments, the second test flow includes a movie playback test step, a 3D effect test step, an audio test step, a processor function test step, and a Run Time (RTC) test.
In some embodiments, the network device is a network switch.
In some embodiments, the storage medium is a USB flash drive, a hard disk drive, or an optical disk drive with an optical disk.
To sum up, the software and hardware of the test system can be erected, the test can be automatically executed and the test result can be generated through the control program and the test program stored in the storage medium, and the test result can be uploaded through the network equipment. Therefore, an operator can test a plurality of motherboards simultaneously, and the working efficiency is greatly improved. Meanwhile, the operator can monitor without being on site all the time, so that human resources are released, all test items can be ensured to be executed really due to the fact that factors such as artificial missing test and mistest of the operator are reduced, artificial misjudgment is reduced, and the reliability of the test is improved.
The detailed features and advantages of the present invention are described in detail in the following embodiments, which are sufficient for anyone skilled in the art to understand the technical contents of the present invention and to implement the present invention, and the objectives and advantages related to the present invention can be easily understood by anyone skilled in the art according to the disclosure of the present specification, the claims and the attached drawings.
Drawings
FIG. 1 is a schematic diagram of the elements of a test system.
FIG. 2 is a schematic diagram of a portion of a storage medium.
FIG. 3 is a flow chart of a testing method of the test system.
FIG. 4 is a partial block diagram of another embodiment of a test system.
Description of reference numerals:
1 test system 10 test fixture
11 central processor 13 memory module
20 test board 30 network equipment
40 storage medium 41 operation system
43 control program 45 test program
50 remote server 55 database
500 motherboard 510 input/output module
Test method of S1 test system
S10 mounting the test fixture, test board, network device, motherboard and storage medium
S20 Media Access Control (MAC) address of access mainboard
Executing the control program to drive the test board to send out analog signal to the motherboard for executing the first test
S31
Step (ii) of
S33 generates a first test result
S35 sending out the MAC address associated with the first test result
S41 executing the test program to perform a second test procedure on the motherboard
S43 generating a second test result
S45 sending the MAC position associated with the second test result
S50 generating a test form
Detailed Description
FIG. 1 is a schematic diagram of the elements of a test system. FIG. 2 is a schematic diagram of a portion of a storage medium. FIG. 3 is a flow chart of the operation of the test system. As shown in fig. 1 and fig. 2, the testing system 1 is used for testing the motherboard 500, and mainly for testing the Burn-in (Burn-in) of the motherboard 500 before the factory shipment. The test system 1 includes a test fixture 10, a test board 20, a network device 30 and a storage medium 40. The test fixture 10 may be a platform for mounting the motherboard 500, and supplies power to the motherboard 500, and provides at least one Central Processing Unit (CPU)11 and a memory module 13 to be plugged on the motherboard 500 for testing. The test board 20 is electrically connected to the motherboard 500. The network device 30 is electrically connected to the motherboard 500. The storage medium 40 is electrically connected to the motherboard 500, the network device 30 and the test board 20. The test board 20, the network device 30, and the storage medium 40 can be connected to an input/output (I/O) module 510 of the motherboard 50, but this is only an example and not a limitation.
As shown in fig. 2, the storage medium 40 stores an operating system 41, a control program 43 and a test program 45. The operating system 41, the control program 43 and the test program 45 in the storage medium 40 are loaded and executed via the motherboard 500 with the CPU11 and the memory module 13. The storage medium 40 is a USB flash drive, a hard disk drive, or an optical disk drive having an optical disk on which an operating system 41, a control program 43, and a test program 45 are stored.
FIG. 3 is a flow chart of a testing method of the test system. As shown in fig. 3, the test method S1 of the test system includes step S10, step S20, step S31, step S33, step S35, step S41, step S43, and step S45. Referring to fig. 1 and 2, in step S10, the test fixture 10, the test board 20, the network device 30, the storage medium 40, and the motherboard 500 are mounted. In step S20, the operating system 41 accesses the Media Access Control (MAC) address of the motherboard 500.
Next, in step S31, the operating system 41 executes the control program 43 to send driving signals to drive the test board 20 to send a plurality of analog signals to the motherboard 500 to execute the first test procedure. In step S33, after the first testing process is completed, the testing program generates a first testing result. Next, in step S35, the operating system 41 sends the first test result associated with the MAC address through the network device 30.
In step S41, the operating system 41 executes the test program 45 to perform a second test procedure on the motherboard 500. In step S43, after completing the second testing process, the testing program 45 generates a second testing result. Next, in step S45, the operating system 41 sends the MAC address associated with the second test result through the network device 30. In this flow, although there is a sequential relationship between steps S10, S20, S31, S33 and S35, or between steps S41, S43 and S45, there is no sequential relationship between the two sets of steps S31, S33 to S35, S41 and S43 to S45. In other words, the test method S1 of the test system may first perform step S31, step S33 to step S35, or may first perform step S41, step S43 to step S45. However, the tests may interfere with each other, so that it is impossible to perform the steps S31, S33 to S35, S41, S43 to S45 at the same time.
Referring again to fig. 1 to 3, the test system 1 further includes a remote server 50. The remote server 50 receives and stores the MAC address, the first test result, and the second test result. The testing method S1 further includes step S50. The remote server 50 generates a test form according to the test result. It is also possible to store the MAC address, the first test result and the second test result in a local computer.
FIG. 4 is a partial block diagram of another embodiment of a test system. As shown in fig. 4, the network device 30 is a network switch, so that the remote server 50 can correspond to a plurality of motherboards 500 to be tested, and thus, the MAC address is more important, and the first test result and the second test result generated by testing different motherboards 500 can be distinguished to avoid confusion of the test results.
Referring again to fig. 1, the test system 1 further includes a database 55, and the database 55 may store a comparison table of MAC addresses and motherboard serial numbers. The remote server 50 accesses the comparison table of the database 55 to access the motherboard serial number corresponding to the MAC address. Thus, the remote server 50 can associate the first test result and the second test result with the host version number. However, the above is merely exemplary and not intended to be limiting. The serial number of the motherboard can also be manually input during testing. Since the manufacturing of the motherboard 500 usually has a lot number, if the first test result and the second test result have error information, the serial number of the motherboard can be compared to determine whether the motherboard 500 of the whole lot number has a defect in manufacturing. Here, the remote server 50 may generate test forms in batches according to the serial number of the motherboard.
In addition, when the first test result and the second test result have error information, the remote server 50 generates an error analysis table in batch according to the serial number of the motherboard, the error information of the first test result and the second test result. Therefore, the errors of the motherboards 500 of the whole batch number can be analyzed and compared, and whether the defects exist in the manufacturing process can be judged.
Furthermore, the operator or any person participating in the test can be connected to the remote server 50 through the network, so that the test condition of the whole test process and whether an abnormal condition occurs can be monitored in real time. Therefore, the operator can achieve the technical effect of real-time monitoring without being present at any time.
Further, referring to fig. 2 again, since there is a problem of a crash of the process during the possible test, when the first test result or the second test result has error information, the remote server 50 returns feedback information to the operating system 41 through the network device 30, and the operating system performs the first test process or the second test process again according to the feedback information. Thus, a test is performed again to confirm whether the error message is from the program or the motherboard 500.
Referring to fig. 3 again, the first test flow refers to a test flow that requires software and hardware to test the motherboard 500 in cooperation. The first test process includes a voltage switch test, a switch test step, a restart test, and a temporary to RAM (STR) test, and the first test process may be one or more of the test steps described above. The foregoing is by way of example only and is not intended as limiting. The test items in the first test flow are executed by the operating system 41 to execute the control program 43, so as to drive the test board 20 to generate an analog signal, for example, an analog signal simulating a push switch is sent out, so as to determine whether the related functions of the motherboard 500 are normal, and generate a first test result according to each test item.
For example, in the first test flow, the test board 20 may send out a plurality of analog signals to perform a voltage switch test, a switch test procedure, and a restart test, and record the result of each test in the operating system 41, obtain a test value through calculation, compare the test value with a set value, and determine an error (fail) if the test value is lower than the set value. In addition, if The OS 41 generates an Error window (Error window found), a computer restart (The computer restart), an OS test Error (OS test Error), and a CPU load time out (CPU load time out) during testing, The whole test item is also determined to be an Error (fail), and The related Error information is recorded and transmitted to The remote server 50 through The network device 30.
In addition, when The control/test software error (BurnIn test Failed) generated by The operating system 41, failing to enter The S3 mode (Failed to transmit mode), idle test error (Failed), test computer restart (The computers), Video check time out (Video check time out), and idle start failure (Failed) are also determined as errors (fail) when The control/test software error (BurnIn test Failed) generated by The operating system 41 is received, and The related error information is recorded and transmitted to The remote server 50 through The network device 30.
The second test process is a function test process of a related chip mounted on the motherboard 500, and the second test process includes a movie playback test step, a 3D effect test step, an audio test step, a processor function test step, and a Run Time (RTC) test, and the second test process may be one or more of the above test steps.
Here, in the video playback test step and the audio test step of the second test flow, the test program 45 may execute the related video data pre-stored in the operating system 41, and determine whether the related functions are normal through playback, text recognition, image capture, and comparison. For another example, for the Real Time Clock (RTC) test, the system Time of the terminal is compared with the system Time of the server, if the difference exceeds a predetermined value, for example, three minutes, it is determined as an error, and the related error information is recorded and transmitted to the remote server 50 through the network device 30. During The CPU functional test, if The os 41 generates a test computer restart (The computer restarts), a CPU load timeout (CPU load timeout), a CPU utilization rate smaller than a threshold (CPU utilization is below The upper limit), or an Abnormal shutdown (Abnormal shutdown of normal) during The test. It is determined as an error, and the related error information is recorded and transmitted to the remote server 50 through the network device 30.
In addition, for The 3D effect testing step, if The operating system 41 generates a dead frame (time out), a frame exit (benchmark canceled), an error in running (counted error while running), a Video not running (Video not running), a Video check time out (Video check time out), a Test computer restart (The computer restart), or a C & C Test error report (C & C Test XX fail), The operating system is also determined to be an error, and records The related error information and transmits The error information to The remote server 50 through The network device 30. However, the above determination of various tests is merely an example and not intended to be limiting, and actually various error messages or various error determinations can be loaded in the control program or the test program according to the requirement.
In summary, the test system 1 can automatically execute the test procedure and generate the test result through the hardware configuration and the program in the storage medium 40, and upload the test result through the network device 30. Thus, an operator can simultaneously execute the test of a plurality of motherboards 500, and the working efficiency is greatly improved. In addition, the operator can monitor without being on site all the time, human resources are released, all test items can be ensured to be executed really due to the fact that the factors of artificial missing test and mistest of the operator are reduced, artificial misjudgment is reduced, and the reliability of the test is improved.
Although the present invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit of the invention, and therefore, the scope of the invention is to be determined by the appended claims.

Claims (10)

1. A test system for testing a motherboard includes:
the testing jig supplies power to the mainboard and provides at least one central processing unit and a memory module to be inserted in the mainboard;
a test board electrically connected to the motherboard;
a network device electrically connected to the motherboard; and
a storage medium, electrically connected to the motherboard, the network device and the test board, for storing an operating system, a test program and a control program, and being loaded and executed by the motherboard inserted with the central processing unit and the memory module:
accessing an MAC address of the motherboard by the operating system;
executing the control program, driving the test board to send out a plurality of analog signals to the mainboard to execute a first test flow, when the first test flow is completed, generating a first test result by the test program, and sending out the first test result by the operating system by correlating the first test result with the MAC address through the network equipment; and
the operation system executes the test program, performs a second test process on the mainboard, generates a second test result after the test program is completed, and sends the second test result associated with the MAC address through the network equipment.
2. The testing system of claim 1, further comprising a remote server, the remote server receiving and storing the MAC address, the first test result and the second test result, and generating a test form according to the test result.
3. The test system of claim 2 further comprising a database, said remote server accessing a comparison table of said database, accessing a motherboard serial number corresponding to said MAC address.
4. The testing system as claimed in claim 3, wherein the remote server generates the test form in batches according to the serial number of the motherboard.
5. The testing system as claimed in claim 3, wherein when the first and second testing results have error information, the remote server generates an error analysis table in batch for the serial number of the motherboard, the error information of the first and second testing results.
6. The testing system as claimed in claim 5, wherein the remote server returns a feedback message to the operating system when the first testing result or the second testing result has an error message, and the operating system performs the first testing process or the second testing process again according to the feedback message.
7. The test system of claim 1, wherein the first test flow comprises at least one of a voltage switch test, a switch test step, a reboot test, and a scratch-to-memory test.
8. The testing system of claim 7, wherein the second testing process comprises at least one of a movie playback testing step, a 3D effects testing step, an audio testing step, a processor function testing step, and a runtime testing step.
9. The test system of claim 1, wherein the network device is a network switch.
10. The testing system of claim 1, wherein the storage medium is a USB flash drive, a hard disk drive, or an optical disk drive with an optical disk.
CN201811297918.1A 2018-11-02 2018-11-02 Test system Pending CN111143135A (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010039486A1 (en) * 2000-05-02 2001-11-08 Asahi Kogaku Kogyo Kabushiki Kaisha Circuit board and system for testing the same
TW200407702A (en) * 2002-11-12 2004-05-16 Via Tech Inc Automatic motherboard testing system and method
CN1690976A (en) * 2004-04-24 2005-11-02 鸿富锦精密工业(深圳)有限公司 Automatic test system and method for mainboard
CN101471977A (en) * 2007-12-25 2009-07-01 上海晨兴电子科技有限公司 Keyboard test system and test method for intelligent mobile phone
CN104679618A (en) * 2013-11-27 2015-06-03 鸿富锦精密工业(深圳)有限公司 Test result integration system and method
CN105652183A (en) * 2015-12-30 2016-06-08 惠州市德赛西威汽车电子股份有限公司 Vehicle-mounted system PCB mainboard automated testing method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010039486A1 (en) * 2000-05-02 2001-11-08 Asahi Kogaku Kogyo Kabushiki Kaisha Circuit board and system for testing the same
TW200407702A (en) * 2002-11-12 2004-05-16 Via Tech Inc Automatic motherboard testing system and method
CN1690976A (en) * 2004-04-24 2005-11-02 鸿富锦精密工业(深圳)有限公司 Automatic test system and method for mainboard
CN101471977A (en) * 2007-12-25 2009-07-01 上海晨兴电子科技有限公司 Keyboard test system and test method for intelligent mobile phone
CN104679618A (en) * 2013-11-27 2015-06-03 鸿富锦精密工业(深圳)有限公司 Test result integration system and method
CN105652183A (en) * 2015-12-30 2016-06-08 惠州市德赛西威汽车电子股份有限公司 Vehicle-mounted system PCB mainboard automated testing method

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