CN111133669B

CN111133669B - Hybrid multilevel inverter

Info

Publication number: CN111133669B
Application number: CN201880062098.XA
Authority: CN
Inventors: 傅电波; 王朝辉; 石磊
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Digital Power Technologies Co Ltd
Priority date: 2017-09-25
Filing date: 2018-09-19
Publication date: 2021-10-15
Anticipated expiration: 2038-09-19
Also published as: AU2018336731A1; US20200007050A1; EP3676946B1; US11489456B2; AU2018336731B2; US20210143751A1; AU2018336731B9; WO2019060401A1; CN111133669A; EP3676946A1; US10903758B2

Abstract

One method comprises the following steps: during a first half-cycle, using a first switch as an always-on switch, turning on a second switch before turning on a third switch, and turning off the third switch before turning off the second switch, wherein the first switch and the second switch are connected in series and also connected in parallel with the third switch between a first terminal of a power supply and a filter; and during a second half-cycle, using a fourth switch as an always-on switch, turning on a fifth switch before turning on the sixth switch, and turning off the sixth switch before turning off the fifth switch, wherein the fourth switch and the fifth switch are connected in series and further connected in parallel with the sixth switch between the second terminal of the power supply and the filter.

Description

Hybrid multilevel inverter

Cross Reference to Related Applications

The present invention claims prior application priority to united states provisional application No. 62/562,565 entitled "hybrid multilevel inverter" filed 2017, 9, 25, month and 25, the contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to a hybrid multilevel inverter, and in particular embodiments, to a hybrid three-level inverter for solar applications.

Background

Renewable energy sources include solar, wind, tidal, and the like. The solar energy conversion system may include a plurality of solar panels connected in series or parallel. The output of the solar panel may generate a variable dc voltage depending on a number of factors such as time of day, location, and sun-tracking ability. To regulate the output of the solar panel, the output of the solar panel may be coupled to a dc/dc converter to achieve a regulated output voltage at the output of the dc/dc converter. In addition, the solar panel may be connected to the backup battery system by a battery charging control device. During the day, the backup battery is charged by the output of the solar panel. The backup battery provides power to a load coupled to the solar panel when utility power fails or the solar panel is an off-grid power system.

Because most applications can be designed to operate on 120 volt ac power, solar inverters are employed to convert the variable dc output of the photovoltaic module to 120 volt ac power. Multiple multi-level inverter topologies can be employed to achieve high power and high efficiency conversion from solar energy to utility power. In particular, high power ac output may be achieved by using a series of power semiconductor switches to convert a plurality of low voltage dc sources into a high power ac output by combining the stepped voltage waveforms.

Depending on the topology differences, multilevel inverters can be divided into three categories, namely diode-clamped multilevel inverters, flying capacitor multilevel inverters and cascaded H-bridge multilevel inverters. In addition, the multilevel inverter may employ different Pulse Width Modulation (PWM) techniques, such as Sinusoidal PWM (SPWM), selective harmonic cancellation PWM, space vector modulation, and the like. Multilevel inverters are a common power topology for high and medium power applications such as utility interfaces for renewable power sources, flexible ac transmission systems, medium voltage motor drive systems, and the like.

Disclosure of Invention

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present disclosure, which provide a hybrid three-level inverter with lower on-resistance and lower switching losses.

According to an embodiment, an inverter includes a first switch and a second switch connected in series between a first terminal and a second terminal of an input power source. The inverter includes a filter connected to a common node of the first switch and the second switch. The inverter further includes: a plurality of low voltage switches connected between the filter and ground; and a flying capacitor connected in series with two of the plurality of low voltage switches. The flying capacitor is used to reduce voltage stress on the plurality of low voltage switches.

According to another embodiment, a method comprises: during a first half of a cycle of the inverter, a first switch is used to function as an always-on switch, a second switch is turned on before a third switch is turned on, and the third switch is turned off before the second switch is turned off. The method further comprises the following steps: during a second half of the cycle of the inverter, using a fourth switch as an always-on switch, turning on a fifth switch before turning on the sixth switch, and turning off the sixth switch before turning off the fifth switch.

According to yet another embodiment, a system includes a first input capacitor and a second input capacitor connected in series across two terminals of an input power source. The system also includes an inversion unit coupled to the input power source. The inverting unit includes an upper portion and a lower portion connected in series, and a flying capacitor between the upper portion and the lower portion. The flying capacitor is used for reducing voltage stress on the inverter unit. The system further includes a filter connected to a common node of the upper and lower portions of the inversion unit.

An advantage of an embodiment of the present disclosure is a hybrid three-level inverter that provides lower on-resistance and lower switching losses in order to improve the efficiency, reliability, and cost of the hybrid three-level inverter.

The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and advantages of the disclosure will be described hereinafter which form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic diagram of a hybrid three-level inverter according to various embodiments of the present disclosure;

fig. 2 is various control signals and inverter output waveforms of the hybrid three-level inverter shown in fig. 1, in accordance with various embodiments of the present disclosure;

fig. 3 is gate control signals for the second and third switches of the hybrid three-level inverter shown in fig. 1, according to various embodiments of the present disclosure;

fig. 4 is gate control signals for a fifth switch and a sixth switch of the hybrid three-level inverter shown in fig. 1, according to various embodiments of the present disclosure; and is

Fig. 5 is a flow diagram of a method for controlling the hybrid three-level inverter shown in fig. 1, according to various embodiments of the present disclosure.

Corresponding reference numerals and symbols in the various drawings generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

Detailed Description

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated that many of the applicable inventive concepts provided by the present disclosure may be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.

The present disclosure will be described with respect to a preferred embodiment in a particular environment, namely, a three-level inverter. However, the present disclosure may also be applied to a variety of multi-level inverters, including five-level inverters, seven-level inverters, nine-level inverters, and the like. The embodiments will be described in detail below with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of a hybrid three-level inverter according to various embodiments of the present disclosure. The hybrid three-level inverter 100 is coupled between an input direct current (dc) power source PV1 and a load RL, as shown in fig. 1. The input dc power source PV1 may be a solar panel array. Alternatively, the input dc power source PV1 may be an energy storage device, such as a rechargeable battery, fuel cell, or the like. The output voltage of the input power PV1 is equal to E as shown in fig. 1.

As shown in fig. 1, a hybrid three-level inverter 100 includes an input dc-link 102, a first conductive path 104, a second conductive path 106, an inverting unit 108, and an output inductor-capacitor (L-C) filter 110. As shown in fig. 1, a first conductive path 104 and a second conductive path 106 are coupled between the input dc link 102 and the inverting unit 108. An output L-C filter 110 is coupled between the inverting unit 108 and the load RL. More specifically, output L-C filter 110 has an input connected to node Va and an output connected to node Vo, as shown in FIG. 1.

The input dc-link 102 comprises two input capacitors, namely a first capacitor C1 and a second capacitor C2, connected in series between two output terminals of the input dc power source PV 1. In some embodiments, the first capacitor C1 and the second capacitor C2 have the same capacitance. Thus, the voltage applied to the input dc-link 102 is divided evenly across each capacitor. More specifically, the first capacitor C1 has an output voltage E/2 referenced to the common node of capacitors C1 and C2. Likewise, the second capacitor C2 has an output voltage-E/2 referenced to the common node of capacitors C1 and C2. According to some embodiments, the common node of capacitors C1 and C2 is grounded. Throughout the description, the common node of capacitors C1 and C2 may alternatively be referred to as the neutral point of hybrid three-level inverter 100.

It should be noted that although fig. 1 is a hybrid three-level inverter 100 having two input capacitors (e.g., first capacitor C1 and second capacitor C2), hybrid three-level inverter 100 may accommodate any number of input capacitors. The number of input capacitors illustrated herein is limited only for purposes of clearly illustrating the inventive aspects of the various embodiments. The present disclosure is not limited to any particular number of input capacitors. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, additional capacitors may be employed to achieve an output staircase waveform with additional voltage levels.

As shown in fig. 1, inverter unit 108 includes an upper portion 118, a lower portion 128, and a flying capacitor C3. The upper portion 118 and the lower portion 128 are connected in series across two terminals of an input dc power source PV 1. Flying capacitor C3 is placed between upper portion 118 and lower portion 128. The upper portion 118 of the inverting unit 108 includes a first switch Q1, a second switch Q2, and a third switch Q3. The lower portion 128 of the inverting unit 108 includes a fourth switch Q4, a fifth switch Q5, and a sixth switch Q6. Node Va is a common node of the upper portion 118 and the lower portion 128.

As shown in fig. 1, a first switch Q1 and a second switch Q2 are connected in series and also connected in parallel with a third switch Q3. A fourth switch Q4 and a fifth switch Q5 are connected in series and also connected in parallel with a sixth switch Q6. A flying capacitor C3 is connected between the common node of the first switch Q1 and the second switch Q2 and the common node of the fourth switch Q4 and the fifth switch Q5. Further, a common node of the third switch Q3 and the sixth switch Q6 is connected to a common node of the second switch Q2 and the fifth switch Q5.

In operation, the second switch Q2 and the fifth switch Q5 are controlled by a pair of control signals that are complementary to each other. By controlling the on and off states of the switches Q1-Q8, the node Va can have three different voltage levels. The three voltage levels at node Va include E/2, 0, and-E/2. After passing through the output L-C filter 110, the voltage waveform at node Va becomes a sine wave at node Vo.

In operation, the first switch Q1 is used to function as an always-on switch during the first half of the cycle of the hybrid three-level inverter 100. The second switch Q2 and the fifth switch Q5 are controlled by two complementary signals. The control signal for the third switch Q3 is similar to the control signal applied to the second switch Q2, except that two delays have been added to the control signal applied to the third switch Q3. A first delay is added between the turn-on of the second switch Q2 and the turn-on of the third switch Q3. A second delay is added between the turning off of the third switch Q3 and the turning off of the second switch Q2. In some embodiments, the first delay is about two microseconds. The second delay is about two microseconds.

In some embodiments, the fourth switch Q4 is used to function as an always-on switch during the second half of the period of the hybrid three-level inverter. The second switch Q2 and the fifth switch Q5 are controlled by two complementary signals. In addition, during the second half, the fifth switch Q5 is turned on before the sixth switch Q6 is turned on. The sixth switch Q6 is turned off before the fifth switch Q5 is turned off. A third delay is added between the turn-on of the fifth switch Q5 and the turn-on of the sixth switch Q6. A fourth delay is added between the turn-off of the sixth switch Q6 and the turn-off of the fifth switch Q5. In some embodiments, the third delay is about two microseconds. The fourth delay is about two microseconds. Detailed control of the upper portion 118 and the lower portion 128 of the inverter unit 108 will be described below with respect to fig. 2.

This delay time provided above is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, depending on different design needs and applications, the delay time may be changed accordingly.

One advantageous feature of having the third switch Q3 and the sixth switch Q6 is that the two switches provide an additional conductive path between the input power source and the load RL. The additional conductive path helps to reduce the on-resistance of hybrid three-level inverter 100, thereby reducing power losses and improving efficiency.

The flying capacitor C3 acts as a clamping capacitor. Specifically, flying capacitor C3 acts to clamp the voltage across fifth switch Q5 and sixth switch Q6 to a level substantially equal to E/2, thereby reducing the voltage stress on fifth switch Q5 and sixth switch Q6.

A first conductive path 104 is connected between a common node of the first switch Q1 and the second switch Q2 and a common node of the first input capacitor C1 and the second input capacitor C2. A second conductive path 106 is connected between a common node of the fourth switch Q4 and the fifth switch Q5 and a common node of the first input capacitor C1 and the second input capacitor C2.

In some embodiments, the first conductive path 104 and the second conductive path 106 act as freewheeling paths between the inverting unit 108 and ground. Specifically, during the first half of the cycle of the hybrid three-level inverter 100, the switches of the second conductive path 106 are used as always-on switches, and the switches of the first conductive path 104 are used as always-off switches. On the other hand, during the second half of the cycle of the hybrid three-level inverter 100, the switches of the first conductive path 104 are used as always-on switches, and the switches of the second conductive path 106 are used as always-off switches.

As shown in fig. 1, the first conductive path 104 includes a seventh switch Q7. In some embodiments, the seventh switch Q7 is implemented as an IGBT. The seventh switch Q7 has a collector connected to the common node of the first switch Q1 and the second switch Q2, and an emitter connected to the common node of the first input capacitor C1 and the second input capacitor C2.

The second conductive path 106 includes an eighth switch Q8. In some embodiments, the eighth switch Q8 is implemented as an IGBT. As shown in fig. 1, the eighth switch Q8 has a collector connected to a common node of the first and second input capacitors C1 and C2, and an emitter connected to a common node of the fourth and fifth switches Q4 and Q5.

It should also be noted that although fig. 1 shows each conductive path being formed of a diode and an IGBT connected in an anti-parallel arrangement, one of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the conductive paths shown in fig. 1 may be formed by bidirectional switches.

The output L-C filter 110 includes an inductor Lo and a capacitor Co. As shown in fig. 1, the input of the output L-C filter 110 is connected to a common node of the upper portion 118 and the lower portion 128 of the inverting unit 108. The output of the output L-C filter 110 is connected to a load RL. As shown in fig. 1, the output of the output L-C filter 110 is the common node of the inductor Lo and the capacitor Co.

According to an embodiment, the switches shown in fig. 1 (e.g., switches Q1-Q8) may be implemented as IGBT devices. Alternatively, the switching element may be any controllable switch, such as a metal oxide semiconductor field-effect transistor (MOSFET) device, an Integrated Gate Commutated Thyristor (IGCT) device, a gate turn-off thyristor (GTO) device, a Silicon Controlled Rectifier (SCR) device, a junction gate field-effect transistor (JFET) device, a MOS Controlled Thyristor (MCT) device, and so on.

It should be noted that the body diodes of the switches Q1-Q8 may be used to provide a freewheeling channel when the switches Q1-Q8 are implemented by MOSFET devices. On the other hand, when the switches Q1-Q8 are implemented by IGBT devices, a separate freewheeling diode is required to connect in parallel with its corresponding switch.

As shown in fig. 1, diodes D1, D2, D3, D4, D5, D6, D7, and D8 are required to provide a reverse conduction path for hybrid three-level inverter 100. In other words, diodes D1-D8 are anti-parallel diodes. In some embodiments, diodes D1-D8 are co-packaged with their respective IGBT devices. In an alternative embodiment, diodes D1-D8 are placed external to their respective IGBT devices. The operating scheme of the switches Q1-Q8 will be described below with respect to fig. 2-4.

In some embodiments, the voltage rating of the first switch Q1, the second switch Q2, the fourth switch Q4, the fifth switch Q5, the seventh switch Q7, and the eighth switch Q8 is about 650V for a 1000V application (e.g., the output voltage of the input power supply is about 1000V). The third switch Q3 and the sixth switch Q6 are rated for about 1200V.

It should be noted that the above nominal voltages are merely examples. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the voltage rating of the third switch Q3 may be in the range of about 1000V to about 1500V, depending on different applications and design needs.

The gates of the switches Q1-Q8 are controlled by the controller 115, as shown in FIG. 1. The controller 115 may detect the voltage across the output of the hybrid three-level inverter 100. Based on the detected voltages, the controller 115 generates gate driving signals to control on/off of the second and fifth switches Q2 and Q5. Alternatively, based on a control signal from a system manager (not shown), the controller 115 generates a gate driving signal to control on/off of the second and fifth switches Q2 and Q5. A detailed operating principle of the controller 115 will be described below with respect to fig. 2.

It should also be noted that although fig. 1 shows the controller to generate gate signals for the hybrid three-level inverter 100, one skilled in the art will recognize that there may be many alternatives for implementing the functions of the controller 115. For example, the controller 115 may be replaced with discrete components. Further, there may be a dedicated driver or a plurality of dedicated drivers coupled between the controller 115 and the switches Q1-Q8.

Fig. 2 is various control signals and inverter output waveforms for the hybrid three-level inverter shown in fig. 1, according to various embodiments of the present disclosure. The horizontal axis of fig. 2 represents time intervals. There may be six vertical axes. A first vertical axis Y1 represents the voltage at node Vo of fig. 1. The second vertical axis Y2 represents gate driving signals of the first switch Q1 and the eighth switch Q8. A third vertical axis Y3 represents gate driving signals of the fourth and seventh switches Q4 and Q7. A fourth vertical axis Y4 represents the gate drive signals of the second and fifth switches Q2, Q5. A fifth vertical axis Y5 represents the gate drive signal for the third switch Q3. The sixth vertical axis Y6 represents the gate drive signal of the sixth switch Q6.

As shown in fig. 2, the waveform Vo is a sinusoidal waveform. Referring back to fig. 1, at node Va, the waveform is a three-level waveform, similar to the sinusoidal waveform shown in fig. 2. An output L-C filter 110 placed between node Va and node Vo reduces the harmonic content of the three-level waveform and generates the sinusoidal waveform shown in fig. 2.

The sinusoidal waveform shown in fig. 2 illustrates one cycle of the hybrid three-level inverter 100. In some embodiments, the output voltage of hybrid three-level inverter 100 oscillates at a rate of 60 full round-trip cycles per second. In an alternative embodiment, the output voltage of hybrid three-level inverter 100 oscillates at a rate of 50 full round-trip cycles per second.

During the first half of the cycle, the first switch Q1 and the eighth switch Q8 are used to act as always-on switches, as indicated by the gate drive signals of the first switch Q1 and the eighth switch Q8. The fourth switch Q4 and the seventh switch Q7 are used to function as always-off switches, as indicated by the gate drive signals of the fourth switch Q4 and the seventh switch Q7 shown in fig. 2.

During the second half of the cycle, the fourth and seventh switches Q4, Q7 are used to act as always-on switches, as indicated by the gate drive signals of the fourth and seventh switches Q4, Q7. The first switch Q1 and the eighth switch Q8 are used to function as always-off switches, as indicated by the gate drive signals of the first switch Q1 and the eighth switch Q8 shown in fig. 2.

During the first and second halves of the cycle, the second and fifth switches Q2, Q5 are controlled by a pair of control signals that are complementary to each other. Referring back to fig. 1, the controller 115 serves to control the second switch Q2 and the fifth switch Q5 to be turned on and off. Depending on the different applications and the variety of detected operating parameters, the controller 115 may adjust the operation of the second and fifth switches Q2, Q5 accordingly.

During the first half, the third switch Q3 is controlled by a first Pulse Width Modulation (PWM) signal generated by the controller 115 shown in fig. 1. During the second half, the third switch Q3 is used to function as an always-off switch, as indicated by the gate drive signal of the third switch Q3.

During the first half, the third switch Q3 is turned on after the second switch Q2 has been turned on. The third switch Q3 is turned off before the second switch Q2 has been turned off. Detailed timing control of the second switch Q2 and the third switch Q3 will be described below with respect to fig. 3.

During the first half, the sixth switch Q6 is used to act as an always off switch, as indicated by the gate drive signal of the sixth switch Q6. During the second half, the sixth switch Q6 is controlled by a second PWM signal generated by the controller 115.

During the second half, the sixth switch Q6 is turned on after the fifth switch Q5 has been turned on. The sixth switch Q6 is turned off before the fifth switch Q5 has been turned off. Detailed timing control of the fifth switch Q5 and the sixth switch Q6 will be described below with respect to fig. 4.

Fig. 3 is gate control signals for the second and third switches of the hybrid three-level inverter shown in fig. 1, according to various embodiments of the present disclosure. The horizontal axis of fig. 3 represents time intervals. There may be two vertical axes. The first vertical axis Y1 represents the gate drive signal of the second switch Q2. A second vertical axis Y2 represents the gate drive signal of the third switch Q3.

Fig. 3 illustrates in detail the gate control signals of the second switch Q2 and the third switch Q3 between the dotted lines a-a' shown in fig. 2. As shown in fig. 3, the second switch Q2 is turned on at t 1. After the first delay, the third switch Q3 is turned on at t 2. The first delay has a predetermined value. In some embodiments, the first delay is about two microseconds. The third switch Q3 is turned off at t 3. After the second delay, the second switch Q2 is turned off at t 4. The second delay has a predetermined value. In some embodiments, the second delay is about two microseconds.

Fig. 4 is gate control signals for a fifth switch and a sixth switch of the hybrid three-level inverter shown in fig. 1, according to various embodiments of the present disclosure. The horizontal axis of fig. 4 represents time intervals. There may be two vertical axes. The first vertical axis Y1 represents a gate driving signal of the fifth switch Q5. The second vertical axis Y2 represents the gate drive signal of the sixth switch Q6.

Fig. 4 illustrates the gate control signals of the fifth switch Q5 and the sixth switch Q6 between the dotted lines B-B' shown in fig. 2 in detail. As shown in fig. 4, the fifth switch Q5 is turned on at t 1. After the first delay, the sixth switch Q6 is turned on at t 2. The first delay has a predetermined value. In some embodiments, the first delay is about two microseconds. The sixth switch Q6 is turned off at t 3. After the second delay, the fifth switch Q5 is turned off at t 4. The second delay has a predetermined value. In some embodiments, the second delay is about two microseconds.

Fig. 5 is a flow diagram of a method for controlling the hybrid three-level inverter shown in fig. 1, according to various embodiments of the present disclosure. This flow diagram shown in fig. 5 is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps illustrated in fig. 5 may be added, removed, replaced, rearranged, and repeated.

At step 502, during a first half of the cycle of the hybrid three-level inverter 100 shown in fig. 1, a first switch Q1 is used to function as an always-on switch during the first half, and a second switch Q2 is turned on in response to a gate drive signal from the controller 115, where the second switch Q2 is connected in series with the first switch Q1 between the input source and the output filter.

At step 504, after a first delay, the third switch Q3 is turned on, with the third switch Q3 in parallel with the first switch Q1 and the second switch Q2, as shown in fig. 1. The second switch Q2 is turned on before the third switch Q3 is turned on. The first delay is a predetermined value. The first delay may vary depending on different applications and design needs.

At step 506, the third switch Q3 is turned off before the second switch Q2 is turned off. At step 508, after a second delay, the second switch Q2 is turned off. The second delay is a predetermined value. The second delay may vary depending on different applications and design needs.

At step 512, during a second half of the cycle of the hybrid three-level inverter 100 shown in fig. 1, a fourth switch Q4 is used to function as an always-on switch during the second half, and a fifth switch Q5 is turned on in response to a gate drive signal from the controller 115, wherein the fifth switch Q5 and the fourth switch Q4 are connected in series between the input source and the output filter.

At step 514, after the third delay, a sixth switch Q6 is turned on, with the sixth switch Q6 in parallel with the fourth switch Q4 and the fifth switch Q5. The fifth switch Q5 is turned on before the sixth switch Q6 is turned on. The third delay is a predetermined value. The third delay may vary depending on different applications and design needs.

At step 516, the sixth switch Q6 is turned off before the fifth switch Q5 is turned off. At step 518, after a fourth delay, the fifth switch Q5 is turned off. The fourth delay is a predetermined value. The fourth delay may vary depending on different applications and design needs.

Although embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. An inverter, comprising:

a plurality of low voltage switches including a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch, the third switch and the sixth switch connected in series between a first terminal and a second terminal of an input power source; a filter connected to a common node of the third switch and the sixth switch;

the plurality of low voltage switches are connected between the filter and ground; and

a flying capacitor connected in series with two of the plurality of low voltage switches, wherein the flying capacitor is to reduce voltage stress on the plurality of low voltage switches,

the plurality of low voltage switches: said first and fourth switches connected in series with said flying capacitor and further coupled between said first and second terminals of said input power source, wherein said first and second switches are connected in series and then connected in parallel with said third switch between the first terminal of the input power source and the input of said filter;

said second switch and said fifth switch being connected in series between a common node of said first switch and said flying capacitor and a common node of said fourth switch and said flying capacitor, wherein said common node of said third switch and said sixth switch is connected to a common node of said second switch and said fifth switch, wherein said fourth switch and said fifth switch are connected in series and are also connected in parallel with said sixth switch between a second terminal of said input power supply and said input of said filter;

a seventh switch connected between the common node of the first switch and the flying capacitor and a common node of a first capacitor and a second capacitor, wherein the first capacitor and the second capacitor are connected in series between the first terminal and the second terminal of the input power source; and

an eighth switch connected between said common node of said fourth switch and said flying capacitor and said common node of said first capacitor and said second capacitor;

during a first half of a cycle of the inverter, using the first switch to function as an always-on switch, turning the second switch on before turning the third switch on, and turning the third switch off before turning the second switch off; and

during a second half of the cycle of the inverter, using the fourth switch as an always-on switch, turning the fifth switch on before turning the sixth switch on, and turning the sixth switch off before turning the fifth switch off.

2. The inverter according to claim 1, characterized in that:

the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, and the eighth switch are Insulated Gate Bipolar Transistor (IGBT) devices.

3. The inverter according to claim 1 or 2, characterized in that:

the output voltage of the input power supply is about 1000V;

the rated voltage of the first switch, the second switch, the fourth switch, the fifth switch, the seventh switch, and the eighth switch is about 650V; and is

The rated voltage of the third switch and the sixth switch is about 1200V.

4. The inverter according to claim 1, characterized in that:

the common node of the first and second capacitors is grounded.

5. The inverter according to claim 1 or 4, characterized in that:

the seventh switch is a first IGBT device, wherein an emitter of the first IGBT device is grounded and a collector of the first IGBT device is connected to the common node of the first switch and the flying capacitor.

6. The inverter according to claim 1 or 4, characterized in that:

the eighth switch is a second IGBT device with its collector grounded and its emitter connected to the common node of the fourth switch and the flying capacitor.

7. The inverter according to claim 1, characterized in that:

the input power source is a solar panel array.

8. The inverter according to claim 1 or 4, characterized in that:

the voltage across both terminals of the first capacitor is equal to half of the output voltage of the input power supply.

9. An inverter control method, characterized by comprising:

providing an inverter comprising:

a first switch, a capacitor, and a fourth switch connected in series between a first terminal and a second terminal of an input power source;

a first capacitor and a second capacitor connected in series between the first terminal and the second terminal of the input power source;

a seventh switch connected between a common node of the first switch and the capacitor and a common node of the first capacitor and the second capacitor;

an eighth switch connected between a common node of the fourth switch and the capacitor and the common node of the first capacitor and the second capacitor;

a second switch and a fifth switch connected in series between the common node of the first switch and the capacitor and the common node of the fourth switch and the capacitor; and

a third switch and a sixth switch connected in series between the first terminal and the second terminal of the input power source, wherein a common node of the third switch and the sixth switch is connected to a common node of the second switch and the fifth switch;

wherein the first switch and the second switch are connected in series and then connected in parallel with the third switch between a first terminal of an input power source and an input of a filter, and the fourth switch and the fifth switch are connected in series and also connected in parallel with the sixth switch between a second terminal of the input power source and the input of the filter;

10. The method of claim 9, comprising:

supplying control signals to the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the seventh switch, and the eighth switch, wherein the control signals are for causing three voltage potentials to be generated at the input of the filter.

11. The method of claim 10, further comprising:

using the eighth switch as an always-on switch during the first half of the cycle of the inverter; and

using the seventh switch as an always-on switch during the second half of the cycle of the inverter.

12. The method of claim 9, further comprising:

turning on the third switch after turning on the second switch and a first delay during the first half of the cycle; and

after turning off the third switch and a second delay, turning off the second switch.

13. The method of claim 9, further comprising:

turning on the sixth switch during the second half of the cycle after turning on the fifth switch and a third delay; and

turning off the fifth switch after turning off the sixth switch and a fourth delay.

14. An inverter system, comprising:

a first input capacitor and a second input capacitor connected in series across two terminals of an input power source;

an inverting unit coupled to the input power source, the inverting unit comprising an upper portion and a lower portion connected in series, and a flying capacitor between the upper portion and the lower portion, wherein the flying capacitor is used to reduce voltage stress on the inverting unit; and

a filter connected to a common node of the upper part and the lower part of the inverting unit,

the inversion unit further comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch:

the first switch, the flying capacitor and the fourth switch are connected in series between a first terminal and a second terminal of the input power source;

said first and fourth switches connected in series with said flying capacitor and further coupled between said first and second terminals of said input power source, wherein said first and second switches are connected in series and then connected in parallel with said third switch between the first terminal of the input power source and the input of said filter;

said second switch and said fifth switch connected in series between a common node of said third switch and said flying capacitor and a common node of said fourth switch and said flying capacitor, wherein said common node of said third switch and said sixth switch is connected to a common node of said second switch and said fifth switch, wherein said fourth switch and said fifth switch are connected in series and are also connected in parallel with said sixth switch between a second terminal of said input power supply and said input of said filter;

15. The system of claim 14, wherein:

the first switch and the second switch are connected in series and are also connected in parallel with a third switch;

the fourth switch and the fifth switch are connected in series and are also connected in parallel with a sixth switch;

said flying capacitor being connected between a common node of said first and second switches and a common node of said fourth and fifth switches;

a first conductive path is connected between the common node of the first and second switches and the common node of the first and second input capacitors; and is

A second conductive path is connected between the common node of the fourth and fifth switches and the common node of the first and second input capacitors.

16. The system of claim 15, wherein:

the first conductive path is formed by a first IGBT having a collector connected to the common node of the first and second switches and an emitter connected to the common node of the first and second input capacitors; and is

The second conductive path is formed by a second IGBT having a collector connected to the common node of the first and second input capacitors, and an emitter connected to the common node of the fourth and fifth switches.

17. The system of claim 15, wherein:

at least one of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch includes an IGBT and a diode connected in parallel.