CN111128950A - Power module packaging structure and packaging method thereof - Google Patents
Power module packaging structure and packaging method thereof Download PDFInfo
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- CN111128950A CN111128950A CN201911420634.1A CN201911420634A CN111128950A CN 111128950 A CN111128950 A CN 111128950A CN 201911420634 A CN201911420634 A CN 201911420634A CN 111128950 A CN111128950 A CN 111128950A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81194—Lateral distribution of the bump connectors
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Abstract
The invention provides a power module packaging structure and a packaging method thereof. The packaging structure utilizes the circuit board to replace the traditional bonding wire, thereby reducing the stray inductance of a loop; meanwhile, a laminated circuit structure is formed by the circuit board, the module functional unit and the lining plate, so that stray inductance of the power module can be further reduced. The packaging method provided by the invention only needs to connect the components such as the circuit board, the lining board, the module functional unit and the like, and the mutual connection positions of the components are fixed, so that the power module can be quickly assembled; meanwhile, the surface-to-surface contact connection is adopted to replace the point contact connection of the bonding wire, so that the temperature distribution is better, and the reliability of the power module is higher.
Description
Technical Field
The invention relates to the technical field of semiconductor power module devices, in particular to a power module packaging structure and a packaging method thereof.
Background
The chip and the liner interconnection of the conventional power module require a large number of bonding wires, and the bonding wire structure generates a certain parasitic inductance. In the process of switching on and switching off the power module, the current is changed sharply, and a larger current change rate di/dt is generated. The parasitic inductance and the current change rate di/dt act together to generate the inductor voltage Vo, and the relationship between the parasitic inductance and the current change rate di/dt is: vo is Ls di/dt, wherein Ls represents stray inductance of the switching loop, and parasitic inductance generated by the bonding wire is an important component of the stray inductance. Voltage spikes are generated by superposition of the inductance voltage Vo and the bus voltage, on one hand, the voltage spikes can cause increase of switching loss of the device, increase of the rising rate of the junction temperature of the chip is accelerated, and the device can fail due to over-temperature; on the other hand, if the voltage spike exceeds the maximum voltage that the device can withstand, it will cause the device to break down, which also results in power module failure. Reducing the stray inductance Ls in the loop is therefore one of the key points in the module design.
The wide bandgap semiconductor device has a faster switching speed, and the problem caused by the stray inductance is more serious, and the space for reducing the inductance of the power module with the conventional bonding wire structure is smaller, so that a power module packaging structure and a process method capable of obviously reducing the stray inductance of the power module are needed to be provided.
Disclosure of Invention
In view of the above problems in the prior art, the present application provides a power module package structure and a package method thereof, in which a circuit board is used to replace a bonding wire, so that stray inductance can be effectively reduced.
The power module packaging structure comprises a lining plate, wherein a module function unit is arranged on the lining plate, a circuit board covers the upper surface of the module function unit, and the circuit board is used for bonding the lining plate and the module function unit.
In one embodiment, the module functional unit includes at least one chip module, the module functional unit includes a chip module, the chip module includes a first chip, a second chip, a first metal conductive block, a second metal conductive block, a third metal conductive block, and a fourth metal conductive block, the first chip is disposed on an upper surface of the third metal conductive block, the second chip is disposed on an upper surface of the fourth metal conductive block, and upper surfaces of the first chip, the second chip, the first metal conductive block, and the second metal conductive block are located on the same horizontal plane.
In one embodiment, a plurality of the first chips are disposed in parallel on the third metal conductive block, and a plurality of the second chips are disposed in parallel on the fourth metal conductive block.
In one embodiment, a first metal layer, a second metal layer and a third metal layer are sequentially disposed on the upper surface of the lining plate, the third metal conductive block and the first metal conductive block are disposed on the first metal layer in parallel, the first metal conductive block is located on one side close to the second metal layer, the fourth metal conductive block is disposed on the second metal layer, and the second metal conductive block is disposed on the third metal layer.
In one embodiment, the circuit board comprises a circuit board insulating layer, and a fourth metal layer, a fifth metal layer and a sixth metal layer which are sequentially arranged on the lower surface of the circuit board insulating layer, wherein the fourth metal layer is in surface contact with the source electrode of the first chip, the fifth metal layer is in surface contact with the first metal conductive block and the source electrode of the second chip simultaneously, and the sixth metal layer is in surface contact with the second metal conductive block;
the circuit board further comprises a seventh metal layer arranged on the upper surface of the circuit board insulating layer, and two ends of the seventh metal layer are respectively connected with the fourth metal layer and the sixth metal layer through a first through hole group and a second through hole group which are arranged on the circuit board insulating layer.
In one embodiment, a fourteenth metal layer and a fifteenth metal layer are further disposed on a lower surface of the circuit board insulating layer, the fourteenth metal layer and the fifteenth metal layer are in contact with the source electrode of the first chip and the source electrode of the second chip respectively, and the fourteenth metal layer and the fourth metal layer, and the fifteenth metal layer and the fifth metal layer are all spaced from each other.
And a twelfth metal layer and a thirteenth metal layer are arranged on the upper surface of the circuit board insulating layer, and the twelfth metal layer and the thirteenth metal layer are respectively connected with the fourteenth metal layer and the fifteenth metal layer through a fifth through hole group and a sixth through hole group which are arranged on the circuit board insulating layer.
In one embodiment, an eighth metal layer and a ninth metal layer are further disposed on the lower surface of the insulating layer of the circuit board, and the eighth metal layer and the ninth metal layer are respectively in contact with the gate electrode of the first chip and the gate electrode of the second chip;
and a tenth metal layer and an eleventh metal layer are arranged on the upper surface of the circuit board insulating layer, and the tenth metal layer and the eleventh metal layer are respectively connected with the eighth metal layer and the ninth metal layer through a third through hole group and a fourth through hole group which are arranged on the circuit board insulating layer.
In one embodiment, the second metal layer and the third metal layer are connected to an external positive power terminal and an external negative power terminal, respectively.
In one embodiment, the first to fifteenth metal layers are copper layers, aluminum layers or other metal surface plating layers suitable for semiconductor chip connection.
In one embodiment, the first metal conductive block, the second metal conductive block, the third metal conductive block and the fourth metal conductive block are made of one of molybdenum-copper alloy, aluminum-based silicon carbide and copper.
In one embodiment, the material of the lining plate is alumina ceramic or aluminum nitride ceramic or silicon nitride ceramic.
The invention also provides a packaging method of the power module packaging structure, which comprises the following steps:
fixedly connecting a first metal conductive block, a second metal conductive block, a third metal conductive block and a fourth metal conductive block on the corresponding metal layers on the upper surface of the lining plate;
fixedly connecting gate electrode regions and source electrode regions on the upper surfaces of the first chip and the second chip with metal layers corresponding to the lower surface of the circuit board;
fixedly connecting the upper surfaces of the first metal conductive block and the second metal conductive block with the metal layers corresponding to the lower surface of the circuit board, and fixedly connecting the drain regions at the bottoms of the first chip and the second chip with the upper surfaces of the third metal conductive block and the fourth metal conductive block respectively;
and installing a pipe shell on the periphery of the lining plate, and injecting insulating silica gel into a space enclosed by the pipe shell and the lining plate.
In one embodiment, the method further comprises fixedly connecting the positive power terminal and the negative power terminal to the metal layer corresponding to the substrate before the mounting of the package, and fixedly connecting other auxiliary terminals to the metal layer corresponding to the upper surface of the circuit board.
In one embodiment, the means for fixedly connecting is sintering or welding.
The features mentioned above can be combined in various suitable ways or replaced by equivalent features as long as the object of the invention is achieved.
Compared with the prior art, the power module packaging structure and the packaging method thereof provided by the invention at least have the following beneficial effects:
1. the packaging structure of the invention adopts the circuit board to replace the traditional bonding wire to form a module current loop, thus forming a plane packaging structure, greatly reducing stray inductance in the loop, reducing overshoot voltage, increasing safe working area, improving reliability and lightening switch oscillation. Meanwhile, due to the elimination of the bonding wire, the volume of the whole module is smaller, the structure is more compact, and the power density of the whole power module is improved.
2. The packaging structure of the invention adopts the circuit board, the lining board and the power module unit to form a current loop, wherein, the main current is input into the module function unit from the lining board and flows towards one direction, then enters the circuit board to flow reversely, finally enters the lining board again and is output, and then the main current between the input end and the output end of the power module achieves the effect of a laminated circuit structure, thereby further reducing the stray inductance of the power module.
3. The module functional unit of the packaging structure adopts the conductive metal block to form a current loop and support the chip, the conductive metal block and the circuit board are in surface-to-surface contact, compared with the point-shaped connection of the traditional bonding wire, the surface-to-surface contact connection can ensure that the temperature on the surface of the chip is uniformly distributed and the hot spot is eliminated, the reliability of the chip in long-term use is improved, meanwhile, the surface area of the metal conductive block is large, the effect of accelerating heat transfer can be achieved, and part of heat generated by the power module is transferred to the radiator and is radiated out.
4. The extraction of the gate electrode of the power chip in the packaging structure is realized through the circuit board, and compared with the traditional extraction through a bonding lead, the extraction mode of the gate electrode is simpler, the stray inductance is low, the opening speed is high, the opening loss is low, and the reliability is higher.
5. The packaging method only needs to connect the components such as the circuit board, the lining board, the module functional unit and the like, and the mutual connection positions of the components are fixed, so that the power module can be quickly assembled; meanwhile, the surface-to-surface contact connection is adopted to replace the point contact connection of the bonding wire, so that the temperature distribution and the connection strength are better, and the reliability of the power module is higher.
Drawings
The invention will be described in more detail hereinafter on the basis of embodiments and with reference to the accompanying drawings. Wherein:
fig. 1 shows an isometric view of the overall structure of the package structure of the present invention;
fig. 2 shows a plan view of the overall structure of the package structure of the present invention (arrows indicate main current directions);
FIG. 3 is a schematic diagram showing the layout of the module functional units on the substrate in the package structure of the present invention;
FIG. 4 is a schematic diagram showing a layout structure of a metal layer on a lower surface of a circuit board of the package structure according to the present invention;
FIG. 5 is a schematic diagram of the location of the via groups of the package structure of the present invention on a circuit board;
FIG. 6 is a schematic diagram showing the layout of the metal conductive blocks on the substrate in the package structure of the present invention;
fig. 7 shows a schematic circuit diagram of a power module according to the present invention;
in the drawings, like parts are provided with like reference numerals. The drawings are not to scale.
Reference numerals:
1-a substrate, 11-a first metal layer, 12-a second metal layer, 13-a third metal layer, 12-an expanded diameter part, 2-a chip module, 21-a first chip, 22-a second chip, 23-a first metal conductive block, 24-a second metal conductive block, 25-a third metal conductive block, 26-a fourth metal conductive block, 201-a gate, 202-a source, 3-a circuit board, 31-a circuit board insulating layer, 32-a fourth metal layer, 33-a fifth metal layer, 34-a sixth metal layer, 35-a seventh metal layer, 361-an eighth metal layer, 362-a ninth metal layer, 371-a tenth metal layer, 372-an eleventh metal layer, 381-a twelfth metal layer, 382-a thirteenth metal layer, 391-a fourteenth metal layer, 392-a fifteenth metal layer, 41-a first via group, 42-a second via group, 43-a third via group, 44-a fourth via group, 45-a fifth via group, 46-a sixth via group.
Detailed Description
The invention will be further explained with reference to the drawings.
As shown in fig. 1 of the accompanying drawings, the power module packaging structure provided by the invention comprises a lining plate 1, a module function unit is arranged on the lining plate 1, a circuit board 3 covers the upper surface of the module function unit, and the circuit board 3 is used for bonding the lining plate 1 and the module function unit.
Specifically, the circuit board 3 constitutes a current transfer loop of a main current and a control signal together with the backing board 1 and the module functional unit, instead of the conventional bonding wire. As shown in fig. 1 of the accompanying drawings, the structure of the whole power module without bonding wires makes it unnecessary to reserve the positions of the bonding wires on the metal layer in the module, and also makes it unnecessary to consider the positions of the bonding wires and whether the bonding process is convenient, so that the structure of the whole power module is more compact, the size of the whole power module is smaller, and the packaging operation of the whole power module is also convenient.
In one embodiment, as shown in fig. 3, the module functional unit includes a chip module 2, the chip module 2 includes a first chip 21, a second chip 22, a first metal conductive block 23, a second metal conductive block 24, a third metal conductive block 25, and a fourth metal conductive block 26, the first chip 21 is disposed on an upper surface of the third metal conductive block 25, the second chip 22 is disposed on an upper surface of the fourth metal conductive block 26, and upper surfaces of the first chip 21, the second chip 22, the first metal conductive block 23, and the second metal conductive block 24 are on the same horizontal plane.
Specifically, the first chip 21 and the second chip 22 are thin, which is not beneficial to the bonding operation of the whole power module, so that the first chip 21 and the second chip 22 are respectively supported by the third metal conductive block 25 and the fourth metal conductive block 26, which is convenient for the bonding operation between the components in the power module. More importantly, the third metal conductive bumps 25 and the fourth metal conductive bumps 26 have a large surface area, so that heat generated by the first chip 21 and the second chip 22 can be rapidly transferred to the substrate and dissipated through a heat sink (not shown in the drawings) connected to the substrate, thereby performing a heat transfer function.
In one embodiment, a plurality of first chips 21 are disposed in parallel on the third metal conductive block 25, and a plurality of second chips 22 are disposed in parallel on the fourth metal conductive block 26.
Specifically, when the main current is large, a plurality of chips may be connected in parallel to shunt the main current. Specifically, the areas of the upper surfaces of the third metal conductive blocks 25 and the fourth metal conductive blocks 26 are increased, the number of the first chips 21 and the number of the second chips 22 are increased, the plurality of first chips 21 and the plurality of second chips 22 are connected in parallel, and the current passing through the chip module 2 is prevented from exceeding the load range of a single chip by shunting in parallel.
In one embodiment, a first metal layer 11, a second metal layer 12 and a third metal layer 13 are sequentially disposed on the upper surface of the substrate 1, a third metal conductive block 25 is disposed on the first metal layer 11 in parallel with the first metal conductive block 23, the first metal conductive block 23 is located at a side close to the second metal layer 12, a fourth metal conductive block 26 is disposed on the second metal layer 12, and the second metal conductive block 24 is disposed on the third metal layer 13.
The circuit board 3 comprises a circuit board insulating layer 31, and a fourth metal layer 32, a fifth metal layer 33 and a sixth metal layer 34 which are sequentially arranged on the lower surface of the circuit board insulating layer 31, wherein the fourth metal layer 32 is in surface contact with the source electrode 202 of the first chip 21, the fifth metal layer 33 is in surface contact with the first metal conductive block 23 and the source electrode 202 of the second chip 22 simultaneously, and the sixth metal layer 34 is in surface contact with the second metal conductive block 24;
the circuit board 3 further includes a seventh metal layer 35 disposed on the upper surface of the circuit board insulating layer 31, and both ends of the seventh metal layer 35 are connected to the fourth metal layer 32 and the sixth metal layer 34 through a first via group 41 and a second via group 42 respectively disposed on the circuit board insulating layer 31.
Specifically, the arrow in fig. 2 indicates the main current flowing direction in the power module. A main current is input to the second metal layer 12 of the backing plate 1 through an external power terminal and enters the second chip 22 through the bottom drain electrode after passing through the third metal conductive block 25, the main current flows out from the source electrode 202 on the upper surface of the second chip 22 and enters the first metal conductive block 23 on the first metal layer 11 through the fifth metal layer 33 on the lower surface of the circuit board 3, the main current then passes through the first metal layer 11 and through the fourth metal conductive bumps 26 into the first chip 21, and enters the seventh metal layer 35 on the upper surface of the circuit board 3 through the source 202 of the first chip 21, the fourth metal layer 32 and the first via group 41, then the main current passes through the seventh metal layer 35, the second via group 42, and the sixth metal layer 34 in sequence and enters the second metal conductive block 24, and finally the main current passes through the third metal layer 13 connected to the second metal conductive block 24 and enters the external power terminal for output.
As shown by the arrows in fig. 2, the general flow direction of the main current is to the right during the circulation from the second metal layer 12 to the fourth metal layer 32, and the general flow direction of the main current is to the left from the seventh metal layer 35 to the third metal layer 13 after entering the seventh metal layer 35 through the fourth metal layer 32. Therefore, the main current loop of the packaging structure of the invention forms a laminated circuit structure, thereby reducing the stray inductance of the loop.
In one embodiment, a fourteenth metal layer 391 and a fifteenth metal layer 392 are further disposed on the lower surface of the circuit board insulating layer 31, the fourteenth metal layer 391 and the fifteenth metal layer 392 are in surface contact with the source 202 of the first chip 21 and the source 202 of the second chip 22 respectively, and the fourteenth metal layer 391 and the fourth metal layer 32, the fifteenth metal layer 392 and the fifth metal layer 33 are all spaced apart from each other.
The upper surface of the circuit board insulating layer 31 is provided with a twelfth metal layer 381 and a thirteenth metal layer 382, and the twelfth metal layer 381 and the thirteenth metal layer 382 are respectively connected with the fourteenth metal layer 391 and the fifteenth metal layer 392 through a fifth via group 45 and a sixth via group 46 which are opened on the circuit board insulating layer 31.
The second metal layer 12 and the third metal layer are further provided with an eighth metal layer 361 and a ninth metal layer 362 on the lower surface of the circuit board insulating layer 31, and the eighth metal layer 361 and the ninth metal layer 362 are respectively in surface contact with the gate 201 of the first chip 21 and the gate 201 of the second chip 22;
the tenth metal layer 371 and the eleventh metal layer 372 are disposed on the upper surface of the circuit board insulating layer 31, and the tenth metal layer 371 and the eleventh metal layer 372 are connected to the eighth metal layer 361 and the ninth metal layer 362 through the third via group 43 and the fourth via group 44, respectively, which are disposed on the circuit board insulating layer 31.
Specifically, the tenth metal layer 371 and the eleventh metal layer 372 are connected to an external auxiliary gate terminal, the twelfth metal layer 381 and the thirteenth metal layer 382 are connected to an external auxiliary emitter terminal, and the auxiliary gate terminal and the auxiliary emitter terminal together form a current loop of the control signal. The current of the control signal enters through the tenth metal layer 371 and the eleventh metal layer 372, enters through the third via group 43 and the fourth via group 44, respectively, enters through the eighth metal layer 361 and the ninth metal layer 362, and finally enters through the eighth metal layer 361 and the ninth metal layer 362, respectively, into the gate 201 of the first chip 21 and the second chip 22, respectively, so as to implement the input of the control signal of the power module.
In one embodiment, the second metal layer 12 and the third metal layer 13 are respectively connected to external positive power terminals and external negative power terminals. The positive power terminal and the negative power terminal are respectively used for inputting and outputting main current.
In one embodiment, the first through fifteenth metal layers 11 through 392 are copper layers, aluminum layers, or other metal surface coatings suitable for semiconductor chip attachment.
In one embodiment, the first metal conductive block 23, the second metal conductive block 24, the third metal conductive block 25 and the fourth metal conductive block 26 are made of one of molybdenum-copper alloy, aluminum-based silicon carbide and copper.
In one embodiment, the material of the backing plate 1 is alumina ceramic, aluminum nitride ceramic or silicon nitride ceramic.
The invention also provides a packaging method for the power module packaging structure, which comprises the following steps:
fixedly connecting a first metal conductive block 23, a second metal conductive block 24, a third metal conductive block 25 and a fourth metal conductive block 26 on the corresponding metal layers on the upper surface of the lining plate 1;
fixedly connecting the gate 201 region and the source 202 region on the upper surfaces of the first chip 21 and the second chip 22 with the metal layers corresponding to the lower surface of the circuit board 3;
fixedly connecting the upper surfaces of the first metal conductive block 23 and the second metal conductive block 24 with the corresponding metal layers on the lower surface of the circuit board 3, and fixedly connecting the drain regions at the bottoms of the first chip 21 and the second chip 22 with the upper surfaces of the third metal conductive block 25 and the fourth metal conductive block 26 respectively;
a pipe shell (not shown in the drawing) is arranged on the periphery of the lining plate 1, and insulating silica gel is injected into a space enclosed by the pipe shell and the lining plate 1.
In one embodiment, the method further comprises fixedly connecting the positive power terminal and the negative power terminal to corresponding metal layers of the substrate 1 before installing the package, and fixedly connecting other auxiliary terminals to corresponding metal layers on the upper surface of the circuit board 3. Other auxiliary terminals include an auxiliary gate terminal, an auxiliary emitter terminal.
Specifically, the fixing and connecting manner adopts a sintering or welding process. Preferably, the sintering is by a silver sintering process.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "bottom", "top", "front", "rear", "inner", "outer", "left", "right", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention.
Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.
Claims (14)
1. The utility model provides a power module packaging structure which characterized in that, includes the welt, be provided with module function unit on the welt, module function unit upper surface covers has the circuit board, the circuit board be used for the bonding the welt with module function unit.
2. The power module package structure according to claim 1, wherein the module functional unit includes a chip module, the chip module includes a first chip, a second chip, a first metal conductive block, a second metal conductive block, a third metal conductive block, and a fourth metal conductive block, the first chip is disposed on an upper surface of the third metal conductive block, the second chip is disposed on an upper surface of the fourth metal conductive block, and upper surfaces of the first chip, the second chip, the first metal conductive block, and the second metal conductive block are located on a same horizontal plane.
3. The power module package structure according to claim 2, wherein a plurality of the first chips are disposed in parallel on the third metal conductive block, and a plurality of the second chips are disposed in parallel on the fourth metal conductive block.
4. The power module package structure of claim 2,
the metal plate comprises a lining plate and is characterized in that a first metal layer, a second metal layer and a third metal layer are sequentially arranged on the upper surface of the lining plate, a third metal conductive block is arranged on the first metal layer in parallel and is located close to one side of the second metal layer, a fourth metal conductive block is arranged on the second metal layer, and the second metal conductive block is arranged on the third metal layer.
5. The power module package structure according to claim 4, wherein the circuit board comprises a circuit board insulating layer, and a fourth metal layer, a fifth metal layer and a sixth metal layer sequentially disposed on a lower surface of the circuit board insulating layer, the fourth metal layer is in surface contact with the source electrode of the first chip, the fifth metal layer is in surface contact with the first metal conductive block and the source electrode of the second chip, and the sixth metal layer is in surface contact with the second metal conductive block;
the circuit board further comprises a seventh metal layer arranged on the upper surface of the circuit board insulating layer, and two ends of the seventh metal layer are respectively connected with the fourth metal layer and the sixth metal layer through a first through hole group and a second through hole group which are arranged on the circuit board insulating layer.
6. The power module package structure according to claim 5, wherein a fourteenth metal layer and a fifteenth metal layer are further disposed on a lower surface of the circuit board insulating layer, the fourteenth metal layer and the fifteenth metal layer are in contact with the source electrode of the first chip and the source electrode of the second chip, respectively, and the fourteenth metal layer and the fourth metal layer, the fifteenth metal layer and the fifth metal layer are all spaced from each other;
and a twelfth metal layer and a thirteenth metal layer are arranged on the upper surface of the circuit board insulating layer, and the twelfth metal layer and the thirteenth metal layer are respectively connected with the fourteenth metal layer and the fifteenth metal layer through a fifth through hole group and a sixth through hole group which are arranged on the circuit board insulating layer.
7. The power module package structure of claim 6,
an eighth metal layer and a ninth metal layer are further arranged on the lower surface of the insulating layer of the circuit board, and the eighth metal layer and the ninth metal layer are respectively in contact with the gate electrode of the first chip and the gate electrode of the second chip;
and a tenth metal layer and an eleventh metal layer are arranged on the upper surface of the circuit board insulating layer, and the tenth metal layer and the eleventh metal layer are respectively connected with the eighth metal layer and the ninth metal layer through a third through hole group and a fourth through hole group which are arranged on the circuit board insulating layer.
8. The power module package structure according to any one of claims 4 to 7, wherein the second metal layer and the third metal layer are connected to an external positive power terminal and an external negative power terminal, respectively.
9. The power module package structure of claim 7, wherein the first through fifteenth metal layers are copper layers, aluminum layers or other metal surface plating layers suitable for semiconductor chip connection.
10. The power module package structure according to any one of claims 2 to 7, wherein the first metal conductive block, the second metal conductive block, the third metal conductive block and the fourth metal conductive block are made of one of molybdenum-copper alloy, aluminum-based silicon carbide and copper.
11. The power module package structure according to any one of claims 2 to 7, wherein the material of the backing plate is an aluminum oxide ceramic, an aluminum nitride ceramic or a silicon nitride ceramic.
12. The method for packaging the power module package structure according to any one of claims 2 to 11, comprising:
fixedly connecting a first metal conductive block, a second metal conductive block, a third metal conductive block and a fourth metal conductive block on the corresponding metal layers on the upper surface of the lining plate;
fixedly connecting gate electrode regions and source electrode regions on the upper surfaces of the first chip and the second chip with metal layers corresponding to the lower surface of the circuit board;
fixedly connecting the upper surfaces of the first metal conductive block and the second metal conductive block with the metal layers corresponding to the lower surface of the circuit board, and fixedly connecting the drain regions at the bottoms of the first chip and the second chip with the upper surfaces of the third metal conductive block and the fourth metal conductive block respectively;
and installing a pipe shell on the periphery of the lining plate, and injecting insulating silica gel into a space enclosed by the pipe shell and the lining plate.
13. The method of claim 12, further comprising fixedly attaching positive and negative power terminals to respective metal layers of the substrate and other auxiliary terminals to respective metal layers of the upper surface of the circuit board prior to mounting the package.
14. The packaging method according to claim 12 or 13, wherein the means for fixedly connecting is a sintering or welding process.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104347568A (en) * | 2013-08-07 | 2015-02-11 | 万国半导体股份有限公司 | Multi-chip mixed packaging type semiconductor device and manufacturing method thereof |
| CN105070695A (en) * | 2015-08-14 | 2015-11-18 | 株洲南车时代电气股份有限公司 | Bi-side heat radiation electric car power module |
| CN105161477A (en) * | 2015-08-14 | 2015-12-16 | 株洲南车时代电气股份有限公司 | Planar power module |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104347568A (en) * | 2013-08-07 | 2015-02-11 | 万国半导体股份有限公司 | Multi-chip mixed packaging type semiconductor device and manufacturing method thereof |
| CN105070695A (en) * | 2015-08-14 | 2015-11-18 | 株洲南车时代电气股份有限公司 | Bi-side heat radiation electric car power module |
| CN105161477A (en) * | 2015-08-14 | 2015-12-16 | 株洲南车时代电气股份有限公司 | Planar power module |
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