CN111128766A - Packaging method for improving warping - Google Patents
Packaging method for improving warping Download PDFInfo
- Publication number
- CN111128766A CN111128766A CN201911321879.9A CN201911321879A CN111128766A CN 111128766 A CN111128766 A CN 111128766A CN 201911321879 A CN201911321879 A CN 201911321879A CN 111128766 A CN111128766 A CN 111128766A
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- CN
- China
- Prior art keywords
- frame
- packaging
- substrate
- cutting
- encapsulating material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a packaging method for improving warpage, which comprises the following steps: firstly, laying a frame in a lower die cavity of an encapsulation die; step two, uniformly scattering encapsulation material powder on the frame; step three, sucking the substrate with the chip mounted on the substrate by an upper die, and suspending the chip surface of the substrate above the encapsulating material and the frame in a downward manner; heating the lower die to melt the encapsulating material, pressing the upper die downwards to soak the chip in the melted encapsulating material, and demoulding to form a plastic package body after the encapsulating material is solidified; and step five, cutting the plastic package body into single package structures, and cutting off the frame part during cutting. The invention embeds the reinforcer into the resin composite material, has no influence on the processing procedures before and after encapsulation, has high installation precision, convenient operation and mature technology, and can be realized by the prior machine equipment.
Description
Technical Field
The invention relates to a packaging method for improving warping, and belongs to the technical field of semiconductor packaging.
Background
With the development of semiconductor packaging technology, new products have higher requirements on the thickness dimension of the package, especially for portable electronic products. The conventional packaging structure mainly comprises a substrate, and a chip arranged on the substrate, wherein the chip is electrically connected with the substrate through a wire and is coated by a resin composite material, and the warpage of the molded chip is often large due to the mismatch of the shrinkage rates of the resin composite material and the substrate. The warpage is usually improved by adjusting the ratio of the resin composite material to match the resin composite material with the substrate, but this method is limited by the characteristics of the composite material, and often can only be fine-tuned, and cannot achieve the desired effect. There are also some methods of improving warpage by mounting or growing a reinforcing member on a substrate, but such methods have disadvantages of occupying a substrate space, making mounting difficult, and making accuracy difficult to grasp.
Disclosure of Invention
The present invention is directed to provide a package method for improving warpage, which embeds a reinforcement into a resin composite material, and has high mounting accuracy and convenient operation.
The technical scheme adopted by the invention for solving the problems is as follows: a packaging method for improving warpage, the method comprising the steps of:
firstly, laying a frame in a mold cavity of a lower mold of an encapsulation mold;
step two, uniformly scattering encapsulation material powder on the frame;
step three, sucking the substrate with the chip mounted on the substrate by an upper die, and suspending the chip surface of the substrate above the encapsulating material and the frame in a downward manner;
step four, pressing down the upper die to enable the chip to be soaked in the packaging material in a molten state, vacuumizing to exhaust gas, solidifying and demolding to form a packaging body, and packaging the frame on the upper surface of the packaging body;
and step five, cutting the packaging body into single packaging structures, and cutting off the frame part during cutting.
Preferably, the frame comprises an outer frame and an internal connecting rib, the internal connecting rib is of a # -shaped structure and is correspondingly distributed above the cutting channel of the substrate, and the width of the internal connecting rib is smaller than or equal to that of the cutting channel of the substrate.
Preferably, the frame material is a semiconductor, an insulating material or a metal.
Preferably, the encapsulating material powder consists of a filler and an epoxy resin.
Compared with the prior art, the invention has the advantages that:
1. due to the reinforcing structure of the frame, the product is not easy to warp in the whole state, so that the processing operation is convenient;
2. due to the reinforcing structure of the frame, the product has higher rigidity in the whole state and is not easy to be bent and damaged by misoperation;
3. the production and processing of the invention can be carried out by using the existing equipment without additional investment;
4. the frame is positioned above the substrate cutting channel and is far away from the effective area of the product, the effective area of the product cannot be influenced in the production process, and the reinforcing piece is cut off together when the frame is cut into single products, so that the final structure of the single products cannot be influenced.
Drawings
Fig. 1 to 8 are schematic flow charts of a packaging method for improving warpage according to the present invention.
Wherein:
lower die 1
Encapsulating material 3
Upper die 4
And a chip 6.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
In this embodiment, a package method for improving warpage includes the following steps:
step one, referring to fig. 1 and 2, laying a frame in a mold cavity of a lower mold of an encapsulation mold, and designing the structural size and thickness of the frame in advance according to a product;
the frame comprises an outer frame and internal connecting ribs, the internal connecting ribs are of a # -shaped structure and are correspondingly distributed above the cutting channels of the substrate, and the width of the internal connecting ribs is smaller than or equal to that of the cutting channels of the substrate;
the material of the frame is required to have high Young modulus (Young modulus is more than 100Gpa), is not easy to deform and bend, can be selected according to the requirements of factors such as cost, acquisition difficulty and the like, and can be a semiconductor, such as silicon; insulation materials such as synthetic fibers; or metals, such as alloy steels;
step two, referring to fig. 3, spraying encapsulating material powder in the die cavity of the lower die to uniformly cover the frame;
the encapsulating material powder consists of a filler and epoxy resin;
step three, referring to fig. 4, sucking the substrate with the chip mounted thereon by the upper die, and suspending the chip surface of the substrate above the encapsulating material and the frame;
step four, referring to fig. 5 to 7, after the lower die is heated to about 175 ℃ to melt the encapsulating material, the upper die is pressed down to soak the chip in the encapsulating material in a molten state, the upper die is vacuumized to exhaust gas, the die is released after the chip is solidified to form a packaging body, and at the moment, the frame is also packaged on the upper surface of the packaging body;
due to the reinforced supporting function of the frame, the stress concentration of the encapsulating material caused by thermal expansion and cold contraction is limited, so that the packaging body is smoother and firmer;
step five, referring to fig. 8, the package body is cut into single package structures, and the frame part is cut off during cutting.
In addition to the above embodiments, the present invention also includes other embodiments, and any technical solutions formed by equivalent transformation or equivalent replacement should fall within the scope of the claims of the present invention.
Claims (5)
1. A method of packaging with improved warpage, the method comprising the steps of:
firstly, laying a frame in a mold cavity of a lower mold of an encapsulation mold;
step two, uniformly scattering encapsulation material powder on the frame;
step three, sucking the substrate with the chip mounted on the substrate by an upper die, and suspending the chip surface of the substrate above the encapsulating material and the frame in a downward manner;
step four, pressing down the upper die to enable the chip to be soaked in the packaging material in a molten state, vacuumizing to exhaust gas, solidifying and demolding to form a packaging body, and packaging the frame on the upper surface of the packaging body;
and step five, cutting the packaging body into single packaging structures, and cutting off the frame part during cutting.
2. The packaging method for improving warpage according to claim 1, wherein: the frame comprises an outer frame and an inner connecting rib.
3. The packaging method for improving warpage according to claim 2, wherein: the internal connecting ribs are of a # -shaped structure and correspondingly distributed above the cutting channels of the substrate, and the width of the internal connecting ribs is smaller than or equal to that of the cutting channels of the substrate.
4. The packaging method for improving warpage according to claim 1, wherein: the frame material is semiconductor, insulating material or metal.
5. The packaging method for improving warpage according to claim 1, wherein: the encapsulating material powder is composed of a filler and an epoxy resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911321879.9A CN111128766A (en) | 2019-12-20 | 2019-12-20 | Packaging method for improving warping |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911321879.9A CN111128766A (en) | 2019-12-20 | 2019-12-20 | Packaging method for improving warping |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111128766A true CN111128766A (en) | 2020-05-08 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911321879.9A Pending CN111128766A (en) | 2019-12-20 | 2019-12-20 | Packaging method for improving warping |
Country Status (1)
| Country | Link |
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| CN (1) | CN111128766A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113345846A (en) * | 2021-06-03 | 2021-09-03 | 长鑫存储技术有限公司 | Package structure and method for manufacturing package structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064118A (en) * | 2010-11-16 | 2011-05-18 | 日月光半导体制造股份有限公司 | Method and packaging mould for manufacturing semiconductor packaging piece |
| CN105140190A (en) * | 2015-07-29 | 2015-12-09 | 三星半导体(中国)研究开发有限公司 | Semiconductor package element and method for manufacturing same |
| CN110021591A (en) * | 2018-01-08 | 2019-07-16 | 联发科技股份有限公司 | Semiconductor packages |
-
2019
- 2019-12-20 CN CN201911321879.9A patent/CN111128766A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102064118A (en) * | 2010-11-16 | 2011-05-18 | 日月光半导体制造股份有限公司 | Method and packaging mould for manufacturing semiconductor packaging piece |
| CN105140190A (en) * | 2015-07-29 | 2015-12-09 | 三星半导体(中国)研究开发有限公司 | Semiconductor package element and method for manufacturing same |
| CN106910723A (en) * | 2015-07-29 | 2017-06-30 | 三星半导体(中国)研究开发有限公司 | Semiconductor package part and the method for manufacturing the semiconductor package part |
| CN110021591A (en) * | 2018-01-08 | 2019-07-16 | 联发科技股份有限公司 | Semiconductor packages |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113345846A (en) * | 2021-06-03 | 2021-09-03 | 长鑫存储技术有限公司 | Package structure and method for manufacturing package structure |
| CN113345846B (en) * | 2021-06-03 | 2022-03-22 | 长鑫存储技术有限公司 | Package structure and method for manufacturing package structure |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200508 |
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| RJ01 | Rejection of invention patent application after publication |