CN111106131B - Array substrate - Google Patents
Array substrate Download PDFInfo
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- CN111106131B CN111106131B CN201911311006.XA CN201911311006A CN111106131B CN 111106131 B CN111106131 B CN 111106131B CN 201911311006 A CN201911311006 A CN 201911311006A CN 111106131 B CN111106131 B CN 111106131B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
The application relates to the technical field of display, in particular to an array substrate. Comprises a substrate base plate; the electrode structure is formed on the substrate and comprises a metal electrode and a first conducting layer electrically connected with the metal electrode, and the corrosion resistance of the first conducting layer is greater than that of the metal electrode; the insulating medium layer is formed on one side, away from the substrate, of the electrode structure, a through hole used for connecting the electrode structure is etched in the insulating medium layer, and only the first conducting layer is exposed at the bottom of the through hole; and the second conducting layer is formed on one side of the insulating medium layer, which is far away from the substrate base plate, and is electrically connected with the first conducting layer through the through hole so as to realize the electrical connection between the second conducting layer and the metal electrode. According to the array substrate, the first conducting layer connected with the metal electrode is exposed at the bottom of the through hole etched in the insulating medium layer, and the corrosion resistance of the first conducting layer is greater than that of the metal electrode, so that the metal electrode cannot be corroded.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate.
Background
At present, in order to improve the product quality, most of the wirings on the back surface of the array substrate use copper with lower resistance, and copper has many problems compared with aluminum, but has to be used in order to improve the product quality. One of the problems that arises when copper is used is copper corrosion.
The corrosion of copper can be caused by various reasons, one of which is poor corrosion caused by the damaged copper surface during passivation etching.
Disclosure of Invention
The application provides an array substrate, wherein a first conducting layer connected with a metal electrode is exposed at the bottom of a via hole etched in an insulating medium layer, and the corrosion resistance of the first conducting layer is greater than that of the metal electrode, so that the metal electrode cannot be corroded.
In order to achieve the above object, the present application provides an array substrate, including:
a base substrate;
an electrode structure formed on the substrate base plate, wherein the electrode structure comprises a metal electrode and a first conductive layer electrically connected with the metal electrode, and the corrosion resistance of the first conductive layer is greater than that of the metal electrode;
the insulating medium layer is formed on one side, away from the substrate, of the electrode structure, a through hole used for being connected with the electrode structure is etched in the insulating medium layer, and only the first conducting layer is exposed out of the bottom of the through hole;
and the second conducting layer is formed on one side of the insulating medium layer, which is far away from the substrate base plate, and is electrically connected with the first conducting layer through the through hole so as to realize the electrical connection between the second conducting layer and the metal electrode.
According to the array substrate, the first conducting layer is connected with the metal electrode, the first conducting layer is exposed out of the bottom of the through hole etched in the insulating medium layer, and the corrosion resistance of the first conducting layer is larger than that of the metal electrode, so that the first conducting layer always corresponds to the through hole in the process of etching the through hole in the insulating medium layer, the metal electrode is protected, and the metal electrode is prevented from being corroded in the etching process. And the second conductive layer is electrically connected to the first conductive layer so that the second conductive layer is connected to the metal electrode.
Preferably, the metal electrode includes a gate, the first conductive layer is located on a side of the gate facing the substrate, and one side of the first conductive layer extends out of a bottom surface of the gate.
Preferably, a buffer layer is further disposed on a side of the gate facing the substrate, and the first conductive layer and the buffer layer are on the same layer.
Preferably, the material of the first conductive layer is MoNb.
Preferably, the metal electrode comprises a gate, and the first conductive layer is located on a side of the gate facing away from the substrate.
Preferably, the first conductive layer is an indium tin oxide conductive layer ITO.
Preferably, a buffer layer is further disposed on a side of the gate facing the substrate.
Preferably, the metal electrode includes a source/drain, the first conductive layer is located on a side of the source/drain facing the substrate, and one side of the first conductive layer extends out of a bottom surface of the source/drain.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present application;
fig. 2 is a schematic view of another structure of an array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic view of another structure of an array substrate according to an embodiment of the present application;
fig. 4 is a flowchart illustrating a manufacturing process of an array substrate according to an embodiment of the present disclosure.
Icon: 10-an insulating dielectric layer; 11-a first layer; 12-a second layer; 20-a first conductive layer; 30-a second conductive layer; 40-a gate; 50-a buffer layer; 60-source drain.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1 to 3, an embodiment of the present invention provides an array substrate, including:
a substrate base plate;
an electrode structure formed on the substrate, the electrode structure including a metal electrode and a first conductive layer 20 electrically connected to the metal electrode, the first conductive layer 20 having a corrosion resistance greater than that of the metal electrode;
the insulating medium layer 10 is formed on one side, away from the substrate, of the electrode structure, a via hole for connecting the electrode structure is etched in the insulating medium layer 10, and only the first conducting layer 20 is exposed at the bottom of the via hole;
and the second conducting layer 30 is formed on one side of the insulating medium layer 10, which is far away from the substrate, and the second conducting layer 30 is electrically connected with the first conducting layer 20 through the via hole so as to realize the electrical connection between the second conducting layer 30 and the metal electrode.
In the array substrate of the present application, the first conductive layer 20 is connected to the metal electrode, and the first conductive layer 20 is exposed at the bottom of the via hole etched on the insulating medium layer 10, and the corrosion resistance of the first conductive layer 20 is greater than the corrosion resistance of the metal electrode, so that the first conductive layer 20 always corresponds to the via hole in the process of etching the via hole on the insulating medium layer 10, so as to protect the metal electrode and prevent the metal electrode from being corroded in the etching process. And the second conductive layer 30 is electrically connected to the first conductive layer 20 so that the second conductive layer 30 is connected to the metal electrode.
Note that the material of the metal electrode is copper.
As an alternative, the metal electrode includes a gate 40, the first conductive layer 20 is located on a side of the gate 40 facing the substrate, and a side of the first conductive layer 20 extends out of a bottom surface of the gate 40. When the via hole is etched on the insulating medium layer 10, the via hole corresponds to the portion of the first conductive layer 20 extending out of the bottom surface of the gate 40, so that the via hole does not act on the metal electrode during the etching process of the via hole, and the metal electrode is not corroded.
As an optional manner, a buffer layer 50 is further disposed on a side of the gate 40 facing the substrate, and the first conductive layer 20 and the buffer layer 50 are on the same layer. The buffer layer 50 can provide adhesion between the metal electrode and the substrate, and improve stability between the metal electrode and the substrate.
As an alternative, the material of the first conductive layer 20 is MoNb. The MoNb material is selected, so that the problem of oxidation does not exist when the first conductive layer 20 is exposed to air, and the conductivity of the first conductive layer 20 is guaranteed.
As an alternative, the metal electrode includes a gate 40, and the first conductive layer 20 is located on a side of the gate 40 facing away from the substrate. When the insulating medium layer 10 is used for etching the through hole, the etching is carried out until the side of the gate 40, which is far away from the substrate base plate, is etched, namely, the through hole is communicated with the first conducting layer 20, so that the gate 40 cannot be corroded in the process of etching the through hole.
The buffer layer 50 is provided on the side of the gate 40 facing the substrate, and the buffer layer 50 can improve the stability between the gate 40 and the substrate and also prevent the metal of the gate 40 from diffusing into the substrate.
Alternatively, the first conductive layer 20 is an indium tin oxide conductive layer ITO. It is ensured that the gate electrode 40 under the first conductive layer 20 is not corroded.
As an optional manner, the metal electrode includes a source/drain 60, the first conductive layer 20 is located on a side of the source/drain 60 facing the substrate, and one side of the first conductive layer 20 extends out of a bottom surface of the source/drain 60. When the via hole is etched in the insulating medium layer 10, the via hole corresponds to the portion of the first conductive layer 20 extending out of the bottom surface of the source/drain 60, so that the via hole does not act on the source/drain 60 during the etching process of the via hole, and further the metal electrode is not corroded.
In a specific implementation process, please continue to refer to fig. 1, the metal electrode includes a gate 40 and a source/drain 60, the insulating dielectric layer 10 includes a first layer 11 and a second layer 12, the gate 40 is located on the substrate, a first conductive layer 20 is disposed on a side of the gate 40 facing the substrate, the first layer 11 is formed on a side of the gate 40 away from the substrate, the source/drain 60 is located on a side of the first layer 11 away from the substrate, a first conductive layer 20 is disposed on a side of the source/drain 60 facing the first layer 11, via holes for connecting the gate 40 and the source/drain 60 are etched on the first layer 11 and the second layer 12, and the bottom of the via holes only expose the first conductive layer 20; and the second conducting layer 30 is formed on one side of the second layer 12, which is far away from the substrate base plate, and the second conducting layer 30 is electrically connected with the first conducting layer 20 through a through hole, so that the second conducting layer 30 is electrically connected with the gate 40 and the source drain 60. In this manner, the gate 40 and source drain 60 are not corroded during the via etching process.
Furthermore, the metal electrode comprises a gate 40 and a source drain 60, the insulating medium layer 10 comprises a first layer 11 and a second layer 12, the gate 40 is located on the substrate, a buffer layer 50 is arranged on one side of the gate 40 facing the substrate, a first conductive layer 20 is formed on one side of the gate 40 facing away from the substrate, the first layer 11 is formed on one side of the gate 40 facing away from the substrate, the source drain 60 is located on one side of the first layer 11 facing away from the substrate, a first conductive layer 20 is arranged on one side of the source drain 60 facing the first layer 11, or a first conductive layer 20 is formed on one side of the source drain 60 facing away from the first layer 11, via holes for connecting the gate 40 and the source drain 60 are etched on the first layer 11 and the second layer 12, and the bottom of the via holes only expose the first conductive layer 20; and a second conductive layer 30 formed on the side of the second layer 12 away from the substrate base plate, wherein the second conductive layer 30 is electrically connected with the first conductive layer 20 through a via hole, so as to realize the electrical connection between the second conductive layer 30 and the gate 40 and the source drain 60.
As shown in fig. 4, the manufacturing process of the array substrate includes the following steps:
a gate electrode 40 is formed on the substrate;
a first conductive layer 20 is formed on the gate electrode 40; wherein, the first conductive layer 20 is located at one side of the gate 40 facing the substrate or the side departing from the substrate;
forming a first layer 11 on the substrate layer for covering the gate 40;
forming an active drain 60 on the first layer 11;
a first conductive layer 20 is formed on the source/drain 60; the first conductive layer 20 is located on one side of the source/drain 60 facing the substrate or one side deviating from the substrate;
forming a second layer 12 on the first layer 11 to cover the source/drain 60; wherein, the first layer 11 and the second layer 12 are insulating medium layers 10;
forming openings on the second insulating layer and the first insulating layer by an etching method, wherein the openings correspond to the first conductive layer 20 on the gate 40 and the source drain 60 respectively;
a second conductive layer 30 is formed on the side of the second layer 12 facing away from said substrate layer.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (5)
1. An array substrate, comprising:
a substrate base plate;
an electrode structure formed on the substrate base plate, wherein the electrode structure comprises a metal electrode and a first conductive layer electrically connected with the metal electrode, and the corrosion resistance of the first conductive layer is greater than that of the metal electrode;
the insulating medium layer is formed on one side, away from the substrate, of the electrode structure, a through hole used for being connected with the electrode structure is etched in the insulating medium layer, and only the first conducting layer is exposed out of the bottom of the through hole;
the second conducting layer is formed on one side, away from the substrate, of the insulating medium layer and is electrically connected with the first conducting layer through the through hole so as to realize the electrical connection between the second conducting layer and the metal electrode;
the first conducting layer is positioned on one side of the metal electrode, which faces the substrate base plate, and one side of the first conducting layer extends out of the bottom surface of the metal electrode.
2. The array substrate of claim 1, wherein the metal electrode comprises a gate, the first conductive layer is located on a side of the gate facing the substrate, and the side of the first conductive layer extends out of a bottom surface of the gate.
3. The array substrate of claim 2, wherein a buffer layer is further disposed on a side of the gate electrode facing the substrate, and the first conductive layer and the buffer layer are on the same layer.
4. The array substrate of claim 2, wherein the material of the first conductive layer is MoNb.
5. The array substrate of claim 1, wherein the metal electrode comprises a source and a drain, the first conductive layer is located on a side of the source and the drain facing the substrate, and one side of the first conductive layer extends out of a bottom surface of the source and the drain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911311006.XA CN111106131B (en) | 2019-12-18 | 2019-12-18 | Array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911311006.XA CN111106131B (en) | 2019-12-18 | 2019-12-18 | Array substrate |
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| Publication Number | Publication Date |
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| CN111106131A CN111106131A (en) | 2020-05-05 |
| CN111106131B true CN111106131B (en) | 2022-09-30 |
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| CN201911311006.XA Active CN111106131B (en) | 2019-12-18 | 2019-12-18 | Array substrate |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103003861A (en) * | 2011-07-19 | 2013-03-27 | 松下电器产业株式会社 | Display device and method for manufacturing display device |
| CN103219283A (en) * | 2013-03-19 | 2013-07-24 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device of array substrate |
| CN106125437A (en) * | 2016-09-05 | 2016-11-16 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, display device |
| CN106887390A (en) * | 2017-04-06 | 2017-06-23 | 京东方科技集团股份有限公司 | A kind of method for making its electrode, thin film transistor (TFT), array base palte and display panel |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6122275B2 (en) * | 2011-11-11 | 2017-04-26 | 株式会社半導体エネルギー研究所 | Display device |
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- 2019-12-18 CN CN201911311006.XA patent/CN111106131B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103003861A (en) * | 2011-07-19 | 2013-03-27 | 松下电器产业株式会社 | Display device and method for manufacturing display device |
| CN103219283A (en) * | 2013-03-19 | 2013-07-24 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device of array substrate |
| CN106125437A (en) * | 2016-09-05 | 2016-11-16 | 京东方科技集团股份有限公司 | Display base plate and preparation method thereof, display device |
| CN106887390A (en) * | 2017-04-06 | 2017-06-23 | 京东方科技集团股份有限公司 | A kind of method for making its electrode, thin film transistor (TFT), array base palte and display panel |
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| CN111106131A (en) | 2020-05-05 |
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