CN111106067B - Method for manufacturing double epitaxial layers - Google Patents

Method for manufacturing double epitaxial layers Download PDF

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CN111106067B
CN111106067B CN201911314068.6A CN201911314068A CN111106067B CN 111106067 B CN111106067 B CN 111106067B CN 201911314068 A CN201911314068 A CN 201911314068A CN 111106067 B CN111106067 B CN 111106067B
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silicon
epitaxial layer
hard mask
mask layer
layer
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CN111106067A (en
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刘厥扬
胡展源
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates

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Abstract

The invention discloses a method for manufacturing a double epitaxial layer, which comprises the following steps: providing a silicon substrate with a fin body, and forming a first hard mask layer comprising silicon nitride; defining a forming area of the first silicon-containing epitaxial layer by photoetching, and etching the first hard mask layer to open the top surface of the fin body in the forming area of the first silicon-containing epitaxial layer; carrying out epitaxial growth to form a first silicon-containing epitaxial layer, wherein silicon nitride of the first hard mask layer can generate a silicon dangling bond in the epitaxial growth process; removing the first hard mask layer; forming a second hard mask layer comprising silicon nitride; removing the second hard mask layer on the top surface of the fin body in the formation region of the second silicon-containing epitaxial layer; carrying out epitaxial growth to form a second silicon-containing epitaxial layer; and removing the second hard mask layer. The invention can prevent the silicon dangling bond generated in the silicon nitride of the first hard mask layer by the epitaxial growth of the first silicon-containing epitaxial layer from generating defects in the epitaxial growth of the second silicon-containing epitaxial layer, thereby improving the yield of products.

Description

Method for manufacturing double epitaxial layers
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a double epitaxial layer.
Background
With the development of the technology, the Critical Dimension (CD) of the device is smaller and smaller, and when the process node of the device reaches below 28nm, the stress of the channel region is often required to be changed by adopting an embedded epitaxial layer in the source and drain regions, so as to improve the mobility of carriers and improve the performance of the device. For PMOS devices, the embedded epitaxial layer typically employs a silicon germanium epitaxial layer (SiGe); for NMOS devices, the embedded epitaxial layer typically employs a phosphorus silicon epitaxial layer (SiP). Therefore, it is usually necessary to integrate the germanium-silicon epitaxial layer and the phosphorus-silicon epitaxial layer on the same semiconductor substrate, and a Dual epitaxial layer (Dual EPI) manufacturing method is required. As shown in fig. 1A to fig. 1H, the device structure in each step of the conventional method for manufacturing a double epitaxial layer is schematically illustrated; the manufacturing method of the existing double epitaxial layer comprises the following steps:
step one, as shown in fig. 1A, providing a silicon substrate 101 formed with fins 102, forming shallow trenches between the fins 102, filling field oxygen 103 in the shallow trenches, and exposing the tops of the fins 102 when the top surfaces of the field oxygen 103 are lower than the top surfaces of the fins 102; a first hard mask layer 201 comprising silicon nitride is formed on the silicon substrate 101, and the first hard mask layer 201 covers the top surface and the side surface of each fin 102. The bottom of the first hard mask layer 201 further includes an oxide layer 2011.
Typically, Dichlorosilane (DCS) or silane is used as a silicon source in forming the silicon nitride in the first hard mask layer 201. Silicon dangling bonds are easily generated in the process of forming the silicon nitride of the first hard mask layer 201, and in order to eliminate the dangling bonds on the surface of the silicon nitride, the method further comprises ending treatment at the end stage of the silicon nitride growth process; typically, the end treatment employs NH3 in conjunction with a vacuum treatment.
In fig. 1A, the left side of line AA indicates a formation region of the first silicon-containing epitaxial layer 104, and the right side of line AA indicates a formation region of the second silicon-containing epitaxial layer 105.
Step two, as shown in fig. 1B, a photoresist pattern 202 is formed by a photolithography process to define a formation region of the first silicon-containing epitaxial layer 104; as shown in fig. 1C, the first hard mask layer 201 is etched to remove the first hard mask layer 201 on the top surface of the fin 102 in the formation region of the first silicon-containing epitaxial layer 104, the first hard mask layer 201 is remained on the side surface of the fin 102 in the formation region of the first silicon-containing epitaxial layer 104, and in fig. 1C, the first hard mask layer remained in the formation region of the first silicon-containing epitaxial layer 104 is marked with a mark 201 a; the top surface and the side surface of each fin 102 in the formation region of the second silicon-containing epitaxial layer 105 are covered with the first hard mask layer 201.
Step three, as shown in fig. 1D, performing epitaxial growth on the top of the fin 102 in the formation region of the first silicon-containing epitaxial layer 104 to form the first silicon-containing epitaxial layer 104; in the process of growing the first silicon-containing epitaxial layer 104, silicon nitride of the first hard mask layer 201 generates a silicon dangling bond; in particular, the silicon nitride of the first hard mask layer 201a remaining in the formation region of the first silicon-containing epitaxial layer 104 may generate a silicon dangling bond.
Generally, the first silicon-containing epitaxial layer 104 is a SiP epitaxial layer, a formation region of the first silicon-containing epitaxial layer 104 is used for forming an NMOS transistor, and the first silicon-containing epitaxial layer 104 is used for improving the mobility of carriers in a channel region of the NMOS transistor.
Step four, as shown in fig. 1E, a second hard mask layer 203 comprising silicon nitride is formed on the silicon substrate 101. As shown in fig. 1E, the second hard mask layer 203 covers the surface of the first hard mask layer 201 in the formation region of the second silicon-containing epitaxial layer 105, and the second hard mask layer 203 covers the side surfaces of the remaining first hard mask layers 201a in the bottom region of the first silicon-containing epitaxial layers 104 in the formation region of the first silicon-containing epitaxial layers 104. Typically, the P doping concentration in the top region of the first silicon-containing epitaxial layer 104 is greater, so the silicon nitride of the second hard mask layer 203 is not formed on the sides of the top region of the first silicon-containing epitaxial layer 104.
Typically, dichlorosilane or silane is used as the silicon source in forming the silicon nitride in the second hard mask layer 203. Silicon dangling bonds are easily generated in the process of forming the silicon nitride of the second hard mask layer 203, and in order to eliminate the dangling bonds on the surface of the silicon nitride, the method further comprises ending treatment at the tail stage of the silicon nitride growth process; typically, the end treatment employs NH3 in conjunction with a vacuum treatment.
As shown in fig. 1F, the second hard mask layer 203 on the top surface of each fin 102 in the formation region of the second silicon-containing epitaxial layer 105 is removed. The process of removing the second hard mask layer 203 on the top surface of each fin 102 in the formation region of the second silicon-containing epitaxial layer 105 is an etching process, the etching region needs to be defined by a photolithography process before the etching process, and the second hard mask layer remaining after the etching process is separately denoted by reference numeral 203 a.
In the formation region of the first silicon-containing epitaxial layer 104, the etched second hard mask layer 203a cannot completely cover the remaining first hard mask layer 201a, so that the surface of the first hard mask layer 201a is exposed, and a silicon dangling bond is also exposed.
Sixthly, as shown in fig. 1G, epitaxially growing the second silicon-containing epitaxial layer 105 on the top of the fin 102 in the formation region of the second silicon-containing epitaxial layer 105. A corresponding cap layer 105a is also formed on the surface of the second silicon-containing epitaxial layer 105.
Generally, the second silicon-containing epitaxial layer 105 is a SiGe epitaxial layer, a formation region of the second silicon-containing epitaxial layer 105 is used for forming a PMOS transistor, and the second silicon-containing epitaxial layer 105 is used for improving the mobility of carriers in a channel region of the PMOS transistor.
As can be seen from fig. 1G, the epitaxial growth process of the second silicon-containing epitaxial layer 105 forms a defect 204 at the dangling bond because the surface of the first hard mask layer 201a having the dangling bond in the formation region of the first silicon-containing epitaxial layer 104 is exposed.
Step seven, as shown in fig. 1H, the remaining first hard mask layer 201a and the second hard mask layer 203 are removed at the same time. Typically, phosphoric acid is used to remove the silicon nitride in the first hard mask layer 201a and the second hard mask layer 203. As shown in FIG. 1H, the defect 204 is not removed, and thus the yield of the product is finally affected.
Disclosure of Invention
The invention aims to provide a method for manufacturing double epitaxial layers, which can prevent a silicon dangling bond generated in silicon nitride of a first hard mask layer by epitaxial growth of a first silicon-containing epitaxial layer from generating a defect in the epitaxial growth of a second silicon-containing epitaxial layer, thereby improving the yield of products.
In order to solve the above technical problem, the method for manufacturing a double epitaxial layer provided by the present invention comprises the following steps:
providing a silicon substrate with fin bodies, forming shallow trenches among the fin bodies, filling field oxygen into the shallow trenches, and enabling the top surfaces of the field oxygen to be lower than the top surfaces of the fin bodies so as to expose the tops of the fin bodies; and forming a first hard mask layer comprising silicon nitride on the silicon substrate, wherein the first hard mask layer covers the top surface and the side surface of each fin body.
Step two, defining a forming area of a first silicon-containing epitaxial layer through photoetching, etching the first hard mask layer to remove the first hard mask layer on the top surface of the fin body in the forming area of the first silicon-containing epitaxial layer, and reserving the first hard mask layer on the side surface of the fin body in the forming area of the first silicon-containing epitaxial layer; the top surface and the side surface of each fin body in the forming area of the second silicon-containing epitaxial layer are covered with the first hard mask layer.
Performing epitaxial growth on the top of the fin body in the formation region of the first silicon-containing epitaxial layer to form the first silicon-containing epitaxial layer; in the process of growing the first silicon-containing epitaxial layer, silicon nitride of the first hard mask layer can generate a silicon dangling bond.
And fourthly, removing the first hard mask layer to eliminate the defect formed by the silicon dangling bond of the first hard mask layer in the subsequent growth process of the second silicon-containing epitaxial layer.
Step five, forming a second hard mask layer comprising silicon nitride on the silicon substrate; and removing the second hard mask layer on the top surface of each fin body in the formation region of the second silicon-containing epitaxial layer.
And sixthly, performing epitaxial growth on the top of the fin body in the formation region of the second silicon-containing epitaxial layer to form the second silicon-containing epitaxial layer.
And seventhly, removing the second hard mask layer.
In a further improvement, in the first step, dichlorosilane or silane is used as a silicon source when forming the silicon nitride in the first hard mask layer.
In a further improvement, in the first step, the forming of the silicon nitride of the first hard mask layer further includes a finishing process, where the finishing process is used to reduce or eliminate silicon dangling bonds of the silicon nitride in the first hard mask layer and to prevent the remaining silicon dangling bonds from being exposed.
In a further improvement, the ending treatment adopts NH3 in combination with vacuum treatment; alternatively, the end treatment employs N2 in combination with vacuum treatment.
In a further improvement, in the fifth step, dichlorosilane or silane is used as a silicon source in forming the silicon nitride in the second hard mask layer.
In a further improvement, in the fifth step, the forming of the silicon nitride of the second hard mask layer further includes a finishing process, where the finishing process is used to reduce or eliminate silicon dangling bonds of the silicon nitride in the second hard mask layer and to prevent the remaining silicon dangling bonds from being exposed.
In a further improvement, the ending treatment adopts NH3 in combination with vacuum treatment; alternatively, the end treatment employs N2 in combination with vacuum treatment.
The further improvement is that phosphoric acid is adopted to remove the silicon nitride in the first hard mask layer in the fourth step; and seventhly, removing the silicon nitride in the second hard mask layer by using phosphoric acid.
The further improvement is that the first silicon-containing epitaxial layer is a SiP epitaxial layer, a forming region of the first silicon-containing epitaxial layer is used for forming an NMOS tube, and the first silicon-containing epitaxial layer is used for improving the mobility of carriers in a channel region of the NMOS tube.
The further improvement is that the second silicon-containing epitaxial layer is a SiGe epitaxial layer, a forming region of the second silicon-containing epitaxial layer is used for forming a PMOS tube, and the second silicon-containing epitaxial layer is used for improving the mobility of carriers in a channel region of the PMOS tube.
In a further improvement, in the first step, the first gate structure is further formed on the fin body, and the first gate structure covers a side surface or a side surface and a top surface in the corresponding region segment of the fin body.
In a further improvement, the first silicon-containing epitaxial layers are formed on two sides of the corresponding first gate structures, and the second silicon-containing epitaxial layers are formed on two sides of the corresponding gate structures.
And after the second step is finished and before the third step of epitaxial growth, etching the fin body in the formation region of the first silicon-containing epitaxial layer to form a groove.
After the fifth step and before the sixth step of epitaxial growth, etching the fin body in the formation region of the second silicon-containing epitaxial layer to form a groove.
In a further improvement, after the seventh step is completed, the method further comprises:
and injecting N + source and drain into the first silicon-containing epitaxial layer at two sides of the first grid structure in the forming region of the NMOS tube to form a source region and a drain region of the NMOS tube.
And injecting P + source and drain into the second silicon-containing epitaxial layer at two sides of the first grid structure in the forming region of the PMOS tube to form a source region and a drain region of the PMOS tube.
The further improvement is that the first gate structure is a dummy gate structure and comprises a first gate dielectric layer and a polysilicon dummy gate which are sequentially overlapped.
The further improvement is that the method also comprises the following steps:
and forming a zero-layer interlayer film, wherein the zero-layer interlayer film is filled in the region between the first gate structures.
And removing the first gate structure, and forming a second gate structure formed by overlapping a second gate dielectric layer and a metal gate in the region where the first gate structure is removed.
According to the invention, after the epitaxial growth of the first silicon-containing epitaxial layer is completed, the silicon nitride of the first hard mask layer for opening the epitaxial growth region of the first silicon-containing epitaxial layer is directly removed, so that the silicon dangling bond generated in the silicon nitride of the first hard mask layer by the epitaxial growth of the first silicon-containing epitaxial layer can be prevented from generating defects in the epitaxial growth of the second silicon-containing epitaxial layer, and the product yield can be improved.
In addition, the invention can also carry out ending treatment at the end of the growth of the first hard mask layer, thereby reducing or eliminating the silicon dangling bond of the silicon nitride in the first hard mask layer, preventing the remained silicon dangling bond from being exposed, preventing the dangling bond of the first hard mask layer from generating adverse effect on the epitaxial growth of the first silicon-containing epitaxial layer and eliminating the defect generated thereby.
In addition, the invention can also carry out ending treatment at the end of the growth of the second hard mask layer, thereby reducing or eliminating the silicon dangling bond of the silicon nitride in the second hard mask layer, preventing the remained silicon dangling bond from being exposed, preventing the dangling bond of the second hard mask layer from generating adverse effect on the epitaxial growth of the second silicon-containing epitaxial layer and eliminating the defects generated thereby.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1H are schematic device structures at various steps of a conventional double-epitaxial-layer manufacturing method;
FIG. 2 is a flow chart of a method for fabricating a double epitaxial layer according to an embodiment of the present invention;
fig. 3A-3H are schematic device structures at various steps of a method for fabricating a double epitaxial layer according to an embodiment of the present invention.
Detailed Description
Fig. 2 is a flow chart of a method for manufacturing a double epitaxial layer according to an embodiment of the present invention; fig. 3A to fig. 3H are schematic views of device structures in the steps of the method for manufacturing a double epitaxial layer according to the embodiment of the present invention; the manufacturing method of the double epitaxial layers comprises the following steps:
step one, as shown in fig. 3A, providing a silicon substrate 1 with fins 2, forming shallow trenches between the fins 2, filling field oxygen 3 in the shallow trenches, and exposing the tops of the fins 2 when the top surfaces of the field oxygen 3 are lower than the top surfaces of the fins 2; a first hard mask layer 301 comprising silicon nitride is formed on the silicon substrate 1, and the first hard mask layer 301 covers the top surface and the side surface of each fin body 2. In fig. 3A, an oxide layer 3011 is also formed on the bottom of the first hard mask layer 301.
In the embodiment of the present invention, dichlorosilane or silane is used as a silicon source when forming the silicon nitride in the first hard mask layer 301. The formation of the silicon nitride of the first hard mask layer 301 further includes a finishing process for reducing or eliminating the silicon dangling bonds of the silicon nitride in the first hard mask layer 301 and leaving the remaining silicon dangling bonds unexposed. Typically, the end treatment employs NH3 in conjunction with a vacuum treatment. More preferably, the end treatment is performed by using N2 in combination with a vacuum treatment.
The first gate structure is further formed on the fin body 2, and covers the side surface or the side surface and the top surface of the corresponding region segment of the fin body 2.
And a first silicon-containing epitaxial layer 4 and a second silicon-containing epitaxial layer 5 which are formed subsequently are respectively formed at two sides of the corresponding first gate structure.
In fig. 3A, the left side of the BB line indicates a formation region of the first silicon-containing epitaxial layer 4, and the right side of the BB line indicates a formation region of the second silicon-containing epitaxial layer 5.
Step two, as shown in fig. 3B, defining a formation region of a first silicon-containing epitaxial layer 4 by photolithography, etching the first hard mask layer 301 to remove the first hard mask layer 301 on the top surface of the fin body 2 in the formation region of the first silicon-containing epitaxial layer 4, wherein the first hard mask layer 301 is retained on the side surface of the fin body 2 in the formation region of the first silicon-containing epitaxial layer 4, and in fig. 3B, the first hard mask layer retained in the formation region of the first silicon-containing epitaxial layer 4 is separately marked by a mark 301 a; the top surface and the side surface of each fin body 2 in the formation region of the second silicon-containing epitaxial layer 5 are covered with the first hard mask layer 301.
Preferably, after the second step and before the third step of performing the epitaxial growth, a step of etching the fin body 2 in the formation region of the first silicon-containing epitaxial layer 4 to form a groove is further included, so that the first silicon-containing epitaxial layer 4 formed subsequently is an embedded structure.
Step three, as shown in fig. 3C, performing epitaxial growth on the top of the fin body 2 in the formation region of the first silicon-containing epitaxial layer 4 to form the first silicon-containing epitaxial layer 4; during the growth of the first silicon-containing epitaxial layer 4, the silicon nitride of the first hard mask layer 301 may generate silicon dangling bonds.
In the embodiment of the invention, the first silicon-containing epitaxial layer 4 is a SiP epitaxial layer, a formation region of the first silicon-containing epitaxial layer 4 is used for forming an NMOS transistor, and the first silicon-containing epitaxial layer 4 is used for improving the mobility of carriers in a channel region of the NMOS transistor.
Step four, as shown in fig. 3D, removing the first hard mask layer 301 to eliminate the silicon dangling bond of the first hard mask layer 301 from forming a defect in the subsequent growth process of the second silicon-containing epitaxial layer 5; here, mainly, elimination of the silicon dangling bonds remaining in the first hard mask layer 301a in the formation region of the first silicon-containing epitaxial layer 4 may cause defects in the formation region of the first silicon-containing epitaxial layer 4.
In the embodiment of the present invention, phosphoric acid is used to remove silicon nitride in the first hard mask layer 301.
In fig. 3D, after the process of removing the first hard mask layer 301 is performed, the first hard mask layer corresponding to the mark 301b still remains in the formation region of the second silicon-containing epitaxial layer 5.
Step five, as shown in fig. 3E, a second hard mask layer 302 comprising silicon nitride is formed on the silicon substrate 1. As shown in fig. 3E, the second hard mask layer 302 covers the top surface and the side surface of each fin 2 in the formation region of the second silicon-containing epitaxial layer 5, and the second hard mask layer 302 covers the side surface of the bottom region of each first silicon-containing epitaxial layer 4 in the formation region of the first silicon-containing epitaxial layer 4. Typically, the P doping concentration in the top region of the first silicon-containing epitaxial layer 4 is large, so the silicon nitride of the second hard mask layer 302 is not formed on the side of the top region of the first silicon-containing epitaxial layer 4.
In an embodiment of the present invention, dichlorosilane or silane is used as a silicon source in forming the silicon nitride in the second hard mask layer 302. The formation of the silicon nitride of the second hard mask layer 302 further includes a finishing process for reducing or eliminating the silicon dangling bonds of the silicon nitride in the second hard mask layer 302 and leaving the remaining silicon dangling bonds unexposed. The ending treatment adopts NH3 matched with vacuum treatment; alternatively, the end treatment employs N2 in combination with vacuum treatment.
As shown in fig. 3F, the second hard mask layer 302 on the top surface of each fin 2 in the formation region of the second silicon-containing epitaxial layer 5 is removed. The process of removing the second hard mask layer 302 on the top surface of each fin body 2 in the formation region of the second silicon-containing epitaxial layer 5 adopts an etching process, the etching region needs to be defined by a photolithography process before the etching process, and the second hard mask layer remaining after the etching process is separately denoted by reference numeral 302 a.
Generally, after the fifth step and before the sixth step of performing the epitaxial growth, the method further includes a step of etching the fin body 2 in the formation region of the second silicon-containing epitaxial layer 5 to form a groove, so that the second silicon-containing epitaxial layer 5 formed subsequently is an embedded structure.
Sixthly, as shown in fig. 3G, epitaxially growing the second silicon-containing epitaxial layer 5 on the top of the fin body 2 in the formation region of the second silicon-containing epitaxial layer 5. A corresponding cap layer 5a is also formed on the surface of the second silicon-containing epitaxial layer 5.
Generally, the second silicon-containing epitaxial layer 5 is a SiGe epitaxial layer, a formation region of the second silicon-containing epitaxial layer 5 is used for forming a PMOS transistor, and the second silicon-containing epitaxial layer 5 is used for improving the mobility of carriers in a channel region of the PMOS transistor.
Step seven, as shown in fig. 3H, the second hard mask layer 302 is removed. In an embodiment of the present invention, phosphoric acid is used to remove the silicon nitride in the second hard mask layer 302.
Further comprising:
and injecting N + source and drain into the first silicon-containing epitaxial layer 4 at two sides of the first gate structure in the forming region of the NMOS tube to form a source region and a drain region of the NMOS tube.
And injecting P + source and drain into the second silicon-containing epitaxial layer 5 at two sides of the first grid structure in the forming region of the PMOS tube to form a source region and a drain region of the PMOS tube.
Generally, the first gate structure is a dummy gate structure and includes a first gate dielectric layer and a polysilicon dummy gate which are sequentially stacked. Then, the method also comprises the following steps:
and forming a zero-layer interlayer film, wherein the zero-layer interlayer film is filled in the region between the first gate structures.
And removing the first gate structure, and forming a second gate structure formed by overlapping a second gate dielectric layer and a metal gate in the region where the first gate structure is removed.
The subsequent back end of line (BEOL) process is then completed.
According to the embodiment of the invention, after the epitaxial growth of the first silicon-containing epitaxial layer 4 is completed, the silicon nitride of the first hard mask layer 301 for opening the epitaxial growth region of the first silicon-containing epitaxial layer 4 is directly removed, so that the silicon dangling bond generated in the silicon nitride of the first hard mask layer 301 by the epitaxial growth of the first silicon-containing epitaxial layer 4 can be prevented from generating defects in the epitaxial growth of the second silicon-containing epitaxial layer 5, and the product yield can be improved.
In addition, the embodiment of the invention can also perform ending treatment at the end of the growth of the first hard mask layer 301, thereby reducing or eliminating the silicon dangling bonds of the silicon nitride in the first hard mask layer 301 without exposing the residual silicon dangling bonds, preventing the dangling bonds of the first hard mask layer 301 from generating adverse effects on the epitaxial growth of the first silicon-containing epitaxial layer 4 and eliminating the defects generated thereby.
In addition, the embodiment of the invention can also perform ending treatment at the end of the growth of the second hard mask layer 302, thereby reducing or eliminating the silicon dangling bonds of the silicon nitride in the second hard mask layer 302 without exposing the residual silicon dangling bonds, preventing the dangling bonds of the second hard mask layer 302 from generating adverse effects on the epitaxial growth of the second silicon-containing epitaxial layer 5 and eliminating the defects generated thereby.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A method for manufacturing a double epitaxial layer is characterized by comprising the following steps:
providing a silicon substrate with fin bodies, forming shallow trenches among the fin bodies, filling field oxygen into the shallow trenches, and enabling the top surfaces of the field oxygen to be lower than the top surfaces of the fin bodies so as to expose the tops of the fin bodies; forming a first hard mask layer comprising silicon nitride on the silicon substrate, wherein the first hard mask layer covers the top surface and the side surface of each fin body;
step two, defining a forming area of a first silicon-containing epitaxial layer through photoetching, etching the first hard mask layer to remove the first hard mask layer on the top surface of the fin body in the forming area of the first silicon-containing epitaxial layer, and reserving the first hard mask layer on the side surface of the fin body in the forming area of the first silicon-containing epitaxial layer; the top surface and the side surface of each fin body in the forming region of the second silicon-containing epitaxial layer are covered with the first hard mask layer;
performing epitaxial growth on the top of the fin body in the formation region of the first silicon-containing epitaxial layer to form the first silicon-containing epitaxial layer; in the process of growing the first silicon-containing epitaxial layer, silicon nitride of the first hard mask layer can generate a silicon dangling bond;
removing the first hard mask layer to eliminate the formation of defects of the silicon dangling bond of the first hard mask layer in the subsequent growth process of the second silicon-containing epitaxial layer;
step five, forming a second hard mask layer comprising silicon nitride on the silicon substrate; removing the second hard mask layer on the top surface of each fin body in the formation region of the second silicon-containing epitaxial layer;
sixthly, performing epitaxial growth on the top of the fin body in the formation region of the second silicon-containing epitaxial layer to form the second silicon-containing epitaxial layer;
and seventhly, removing the second hard mask layer.
2. A method of manufacturing a double epitaxial layer according to claim 1, characterized in that: in the first step, dichlorosilane or silane is used as a silicon source when silicon nitride in the first hard mask layer is formed.
3. A method of manufacturing a double epitaxial layer according to claim 2, characterized in that: in the first step, the forming of the silicon nitride of the first hard mask layer further includes a finishing process, where the finishing process is used to reduce or eliminate silicon dangling bonds of the silicon nitride in the first hard mask layer and to prevent the remaining silicon dangling bonds from being exposed.
4. A method of manufacturing a double epitaxial layer according to claim 3, characterized in that: the ending treatment adopts NH3 matched with vacuum treatment; alternatively, the end treatment employs N2 in combination with vacuum treatment.
5. A method of manufacturing a double epitaxial layer according to claim 1, characterized in that: and fifthly, dichlorosilane or silane is used as a silicon source when the silicon nitride in the second hard mask layer is formed.
6. A method of manufacturing a double epitaxial layer according to claim 5, characterized in that: and fifthly, forming the silicon nitride of the second hard mask layer by ending treatment, wherein the ending treatment is used for reducing or eliminating silicon dangling bonds of the silicon nitride in the second hard mask layer and enabling the residual silicon dangling bonds not to be exposed.
7. A method of manufacturing a double epitaxial layer according to claim 6, characterized in that: the ending treatment adopts NH3 matched with vacuum treatment; alternatively, the end treatment employs N2 in combination with vacuum treatment.
8. A method of manufacturing a double epitaxial layer according to claim 1, characterized in that: removing the silicon nitride in the first hard mask layer by adopting phosphoric acid in the fourth step; and seventhly, removing the silicon nitride in the second hard mask layer by using phosphoric acid.
9. A method of manufacturing a double epitaxial layer according to claim 1, characterized in that: the first silicon-containing epitaxial layer is an SiP epitaxial layer, a forming region of the first silicon-containing epitaxial layer is used for forming an NMOS tube, and the first silicon-containing epitaxial layer is used for improving the mobility of carriers in a channel region of the NMOS tube.
10. A method of manufacturing a double epitaxial layer according to claim 9, characterized in that: the second silicon-containing epitaxial layer is a SiGe epitaxial layer, a forming region of the second silicon-containing epitaxial layer is used for forming a PMOS tube, and the second silicon-containing epitaxial layer is used for improving the mobility of carriers in a channel region of the PMOS tube.
11. A method of manufacturing a double epitaxial layer according to claim 10, characterized in that: in the first step, a first gate structure is further formed on the fin body, and the first gate structure covers the side surface or the side surface and the top surface of the corresponding region segment of the fin body.
12. A method of manufacturing a double epitaxial layer according to claim 11, characterized in that: the first silicon-containing epitaxial layers are formed on two sides of the corresponding first gate structures, and the second silicon-containing epitaxial layers are formed on two sides of the corresponding gate structures;
after the second step is completed and before the third step is carried out with epitaxial growth, the method further comprises the step of etching the fin body in the forming area of the first silicon-containing epitaxial layer to form a groove;
and after the fifth step is finished and before the sixth step is carried out with epitaxial growth, the method further comprises the step of etching the fin body in the forming area of the second silicon-containing epitaxial layer to form a groove.
13. A method of manufacturing a double epitaxial layer according to claim 12, characterized in that: after the seventh step is completed, the method further comprises the following steps:
performing N + source-drain injection to form a source region and a drain region of the NMOS tube in the first silicon-containing epitaxial layer on two sides of the first gate structure in the formation region of the NMOS tube;
and injecting P + source and drain into the second silicon-containing epitaxial layer at two sides of the first grid structure in the forming region of the PMOS tube to form a source region and a drain region of the PMOS tube.
14. A method of manufacturing a double epitaxial layer according to claim 13, characterized in that: the first grid structure is a pseudo grid structure and comprises a first grid dielectric layer and a polycrystalline silicon pseudo grid which are sequentially overlapped.
15. The method of fabricating a double epitaxial layer of claim 14, further comprising the steps of:
forming a zero-layer interlayer film, wherein the zero-layer interlayer film is filled in the region between the first grid structures;
and removing the first gate structure, and forming a second gate structure formed by overlapping a second gate dielectric layer and a metal gate in the region where the first gate structure is removed.
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