CN111105743A - Control circuit and control method of display panel and display device - Google Patents
Control circuit and control method of display panel and display device Download PDFInfo
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- CN111105743A CN111105743A CN201911342803.4A CN201911342803A CN111105743A CN 111105743 A CN111105743 A CN 111105743A CN 201911342803 A CN201911342803 A CN 201911342803A CN 111105743 A CN111105743 A CN 111105743A
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- power management
- buffer chip
- gamma buffer
- programmable gamma
- enable signal
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
Abstract
The application discloses a control circuit and a control method of a display panel and a display device, wherein the control circuit comprises a time schedule controller, a power management and programmable gamma buffer chip and a flash memory, and the time schedule controller is respectively connected with the power management and programmable gamma buffer chip and the flash memory; the power management and programmable gamma buffer chip generates voltage required by the time schedule controller to enable the time schedule controller to work, the time schedule controller works to acquire the register state of the power management and programmable gamma buffer chip in real time, and the output of the power management and programmable gamma buffer chip is controlled according to the register state. Through the mode, the situation that the power management and the programmable gamma buffer chip are burnt by relevant original paper such as a time schedule controller and the like due to the fact that short circuit or open circuit occurs to each voltage can be prevented, and the safety of a control circuit of the display panel is improved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a control circuit and a control method for a display panel, and a display device.
Background
Power Management Integrated Circuits (PMICs) and programmable Gamma correction (P-Gamma) circuits are commonly used in display panel driving. At present, the PMIC and the P-Gamma circuit are combined to form a single power management and programmable Gamma buffer chip for the application of display panel drive control to realize the power management and programmable Gamma correction functions.
The power management and programmable gamma buffer chip is internally provided with a state register, the state register is provided with an output power state bit, and the output power state bit under the normal power supply state and the output power state bit under the abnormal power supply state are different. For example, the output power status bit of the power management and programmable gamma buffer chip (e.g. several key voltages: VGH _ PG or AVDD _ PG) is set to 0 in a normal operating state, and is set to 1 when the output voltage is lower than a certain set threshold (e.g. 80% VGH), which indicates an abnormal risk of short circuit or open circuit with the power management and programmable gamma buffer chip connection circuit, and similarly, when VGL _ PG (negative voltage) is higher than a certain set threshold (e.g. 80% VGL), the output power status bit is set to 1, which also indicates an abnormal risk of short circuit or open circuit with the power management and programmable gamma buffer chip connection circuit.
In the prior art, when each path of voltage is broken or short-circuited, and the output power status bit in the power management and programmable gamma buffer chip indicates an abnormal status, the power management and programmable gamma buffer chip is burned out abnormally by a time schedule controller and other related components.
Disclosure of Invention
The application provides a control circuit and a control method of a display panel and a display device, which can solve the problem that a power management and programmable gamma buffer chip is burnt by a time schedule controller and other related elements when the display panel control circuit is broken or short-circuited in the prior art.
In order to solve the technical problem, the application adopts a technical scheme that: the control circuit of the display panel comprises a time schedule controller, a power management and programmable gamma buffer chip and a flash memory, wherein the time schedule controller is respectively connected with the power management and programmable gamma buffer chip and the flash memory; the flash memory is pre-stored with codes required by the power management and programmable gamma buffer chip during working, the power management and programmable gamma buffer chip generates voltage required by the time schedule controller to enable the time schedule controller to work, the time schedule controller works to acquire the register state of the power management and programmable gamma buffer chip in real time and control the output of the power management and programmable gamma buffer chip according to the register state, wherein the register state represents the power supply state of a circuit to be powered, connected with the power management and programmable gamma buffer chip, of the power management and programmable gamma buffer chip, and the power supply state comprises normal power supply and abnormal power supply. .
The time schedule controller is connected with the power management and programmable gamma buffer chip through an I2C bus, and detects the register state of the power management and programmable gamma buffer chip in real time through an I2C bus.
The time sequence controller also comprises an enable signal control end, wherein the enable signal control end is connected with an enable signal end of the power management and programmable gamma buffer chip and is used for controlling the output of the power management and programmable gamma buffer chip according to the state of a register of the power management and programmable gamma buffer chip.
If the register is abnormal in power supply acquired by the time schedule controller, the time schedule controller outputs a low level to an enable signal end of the power management and programmable gamma buffer chip through the enable signal control end to control the power management and programmable gamma buffer chip to stop outputting voltage; and if the register is normally powered by the time schedule controller, the time schedule controller outputs a high level to an enable signal end of the power management and programmable gamma buffer chip through the enable signal control end to control the power management and programmable gamma buffer chip to normally output voltage.
And the time schedule controller is connected with the flash memory through an SPI bus.
In order to solve the above technical problem, another technical solution adopted by the present application is: a control method of a control circuit of a display panel is provided, the control method including: the time schedule controller acquires the state of the register in the power management and programmable gamma buffer chip in real time; and controlling the output of the power management and programmable gamma buffer chip according to the state of the register.
The time schedule controller is connected with the power management and programmable gamma buffer chip through an I2C bus, and detects the register state of the power management and programmable gamma buffer chip in real time through an I2C bus.
The time sequence controller also comprises an enable signal control end, wherein the enable signal control end is connected with an enable signal end of the power management and programmable gamma buffer chip and is used for controlling the output of the power management and programmable gamma buffer chip according to the state of a register of the power management and programmable gamma buffer chip.
If the register state obtained by the time schedule controller is abnormal in power supply, the time schedule controller outputs a low level to an enable signal end of the power management and programmable gamma buffer chip through the enable signal control end, and controls the power management and programmable gamma buffer chip to stop outputting voltage; and if the register state obtained by the time sequence controller is normal, the time sequence controller outputs a high level to an enable signal end of the power management and programmable gamma buffer chip through the enable signal control end to control the power management and programmable gamma buffer chip to normally output voltage.
In order to solve the above technical problem, another technical solution adopted by the present application is: the display device comprises a display panel and any one of the control circuits, wherein the control circuit is connected with the display panel and is used for outputting signals to the display panel.
The beneficial effect of this application is: the control circuit comprises a time schedule controller, a programmable gamma buffer chip, a power management unit, a register state acquisition unit, a programmable gamma buffer chip control unit and a display panel control circuit.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
FIG. 1 is a schematic structural diagram of an embodiment of a control circuit of a display panel according to the present application;
FIG. 2 is a schematic flow chart diagram illustrating an embodiment of a control method for a display panel control circuit according to the present disclosure;
fig. 3 is a schematic structural diagram of an embodiment of a display device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, a control circuit 100 of a display panel according to the present invention includes a timing controller (Tcon)110, a power management and programmable Gamma buffer chip (PMIC and P-Gamma chip) 120, and a Flash memory (Flash) 130. The timing controller 110 is connected to the power management and programmable gamma buffer chip 120 and the flash memory 130, respectively.
Optionally, the timing controller 110 is connected to the power management and programmable gamma buffer chip 120 via an I2C bus in this application. And the timing controller 110 can also obtain the power management and register (not shown) status in the programmable gamma buffer chip 120 in real time through the I2C bus. The register state represents a power supply state of the power management and programmable gamma buffer chip 120 for a circuit (not shown) to be powered, which is connected to the power management and programmable gamma buffer chip 120, and the power supply state includes normal power supply and abnormal power supply.
Specifically, the timing controller 110 can obtain the register state of the critical voltage in the power management and programmable gamma buffer chip 120 through the I2C bus, and take the low level (VGL-NG) output by the power management and programmable gamma buffer chip 120 as an example to describe in detail:
it is understood that the data of the VGL-NG voltage signal can be represented by 6 bits inside the power management and programmable gamma buffer chip 120, such as 010101, wherein the status of 0/1 of a certain bit can indicate whether the VGL-NG voltage is normal or not, and the status of VGL-NG in the register has only two states, 0 for normal operation and 1 for abnormal operation. Therefore, the flag bit state of the VGL-NG in the register, which represents whether the voltage is normal or not, can be detected only through the I2C bus, if the set value of the VGL-NG in the register is detected to be 0, the VGL-NG voltage is normal, otherwise, if the set value of the VGL-NG in the register is detected to be 1, the VGL-NG voltage is abnormal. Of course, in other embodiments, other voltage values are also possible, and this is only for illustration and is not specifically limited.
In the above embodiment, by adding the function of detecting the status of the register in the power management and programmable gamma buffer chip 120 in real time to the timing controller 110, the status of the register can be obtained in real time, and the occurrence of the situation that the power management and programmable gamma buffer chip is burnt by the related elements such as the timing controller due to short circuit or open circuit of each voltage can be prevented.
With continued reference to fig. 1, the timing controller 110 further includes an enable signal control terminal 111, and the enable signal control terminal 111 is connected to an enable signal terminal 121 of the power management and programmable gamma buffer chip 120. In the embodiment of the present invention, an enable signal control terminal 111 is added to the timing controller 110, and the power management and the output of the programmable gamma buffer chip 120 are controlled by the enable signal control terminal 111 in the timing controller 110.
Specifically, if the timing controller 110 obtains that the register state in the power management and programmable gamma buffer chip 120 is abnormal in power supply through the I2C bus, for example, it detects that the setting value indicating the VGL-NG state flag bit in the register is 1, indicating that the VGL-NG voltage is abnormal, the timing controller 110 outputs a low level to the enable signal terminal 121 (i.e., pulls down the enable signal terminal 121) of the power management and programmable gamma buffer chip 120 through the enable signal control terminal 111, thereby controlling the power management and programmable gamma buffer chip 120 to stop outputting the voltage, and further protecting the control circuit of the display panel from being damaged due to the abnormal voltage.
On the contrary, if the timing controller 110 obtains that the register status is normal, for example, it detects that the setting value of the VGL-NG status flag bit in the register is 0, which indicates that the VGL-NG voltage is normal, the timing controller 110 outputs a high level to the enable signal terminal 121 of the power management and programmable gamma buffer chip 120 through the enable signal control terminal 111, and controls the power management and programmable gamma buffer chip 120 to normally output the voltage to the display panel.
Optionally, in the present application, the timing controller 110 is connected to the flash memory 130 through an SPI bus, the flash memory 130 is used for storing codes (codes) required for the operation of the power management and programmable gamma buffer chip 120, and the flash memory 130 is connected to the power management and programmable gamma buffer chip 120. In operation, the timing controller 110 reads codes from the flash memory 130 and writes them to the power management and programmable gamma buffer chip 120. Specifically, the timing controller 110 stores the codes read from the flash memory 130 and required for the operation of the power management and programmable gamma buffer chip 120 in a memory area inside the timing controller 110, and then writes the codes into the registers of the power management and programmable gamma buffer chip 120.
In the above embodiment, by adding the function of detecting the state of the register in the power management and programmable gamma buffer chip in real time to the timing controller, the state of the register is obtained in real time, and the output of the power management and programmable gamma buffer chip is controlled according to the state of the register, so that the situation that the power management and programmable gamma buffer chip is burnt by relevant elements such as the timing controller due to short circuit or open circuit of each path of voltage can be prevented, and the safety of the control circuit of the display panel is improved.
Referring to fig. 2, fig. 2 is a schematic flowchart illustrating an embodiment of a control method of a display panel control circuit according to the present application, where, as shown in fig. 2, the control method of the present application includes the following steps:
s100, the time schedule controller obtains the power management and the state of a register in the programmable gamma buffer chip in real time.
Referring to fig. 1, the timing controller 110 is connected to the power management and programmable gamma buffer chip 120 through an I2C bus. And the timing controller 110 can also acquire the power management and register status in the programmable gamma buffer chip 120 in real time through the I2C bus. Specifically, the timing controller 110 can obtain the register state of the critical voltage in the power management and programmable gamma buffer chip 120 through the I2C bus, and take the low level (VGL-NG) output by the power management and programmable gamma buffer chip 120 as an example to describe in detail:
it is understood that the data of the VGL-NG voltage signal can be represented by 6 bits inside the power management and programmable gamma buffer chip 120, such as 010101, wherein the status of 0/1 of a certain bit can indicate whether the VGL-NG voltage is normal or not, and the status of VGL-NG in the register has only two states, 0 for normal operation and 1 for abnormal operation. Therefore, the flag bit state of the VGL-NG in the register, which represents whether the voltage is normal or not, can be detected only through the I2C bus, if the set value of the VGL-NG in the register is detected to be 0, the VGL-NG voltage is normal, otherwise, if the set value of the VGL-NG in the register is detected to be 1, the VGL-NG voltage is abnormal. Of course, in other embodiments, other voltage values are also possible, and this is only for illustration and is not specifically limited.
And S200, controlling the output of the power management and programmable gamma buffer chip according to the state of the register.
Further, the timing controller 110 further includes an enable signal control terminal 111, and the enable signal control terminal 111 is connected to an enable signal terminal 121 of the power management and programmable gamma buffer chip 120. In the embodiment of the present invention, an enable signal control terminal 111 is added to the timing controller 110, and the power management and the output of the programmable gamma buffer chip 120 are controlled by the enable signal control terminal 111 in the timing controller 110.
Specifically, if the timing controller 110 obtains that the register state in the power management and programmable gamma buffer chip 120 is abnormal in power supply through the I2C bus, for example, it detects that the setting value indicating the VGL-NG state flag bit in the register is 1, indicating that the VGL-NG voltage is abnormal, the timing controller 110 outputs a low level to the enable signal terminal 121 (i.e., pulls down the enable signal terminal 121) of the power management and programmable gamma buffer chip 120 through the enable signal control terminal 111, thereby controlling the power management and programmable gamma buffer chip 120 to stop outputting the voltage, and further protecting the control circuit of the display panel from being damaged due to the abnormal voltage.
On the contrary, if the timing controller 110 obtains that the register status is normal, for example, it detects that the setting value of the VGL-NG status flag bit in the register is 0, which indicates that the VGL-NG voltage is normal, the timing controller 110 outputs a high level to the enable signal terminal 121 of the power management and programmable gamma buffer chip 120 through the enable signal control terminal 111, and controls the power management and programmable gamma buffer chip 120 to normally output the voltage to the display panel.
In the above embodiment, by adding the function of detecting the state of the register in the power management and programmable gamma buffer chip in real time to the timing controller, the state of the register is obtained in real time, and the output of the power management and programmable gamma buffer chip is controlled according to the state of the register, so that the situation that the power management and programmable gamma buffer chip is burnt by relevant elements such as the timing controller due to short circuit or open circuit of each path of voltage can be prevented, and the safety of the control circuit of the display panel is improved.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an embodiment of a display device of the present application, where the display device 200 includes a display panel 210 and a control circuit a with any of the above structures, and the control circuit a is connected to the display panel 210 and is configured to output a signal to the display panel 210. Optionally, the structure of the control circuit a is described in detail in the foregoing embodiments, and is not described herein again.
In summary, it is easily understood by those skilled in the art that the present application provides a control circuit and a control method for a display panel, and a display device, in which a function of detecting a state of a register in a power management and programmable gamma buffer chip in real time is added in a timing controller, so as to obtain the state of the register in real time, and control the output of the power management and programmable gamma buffer chip according to the state of the register, thereby preventing the power management and programmable gamma buffer chip from being burned out by related components such as the timing controller due to short circuit or open circuit of each voltage path, and improving the safety of the control circuit of the display panel.
The above embodiments are merely examples and are not intended to limit the scope of the present disclosure, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present disclosure or those directly or indirectly applied to other related technical fields are intended to be included in the scope of the present disclosure.
Claims (10)
1. The control circuit of the display panel is characterized by comprising a time schedule controller, a power management and programmable gamma buffer chip and a flash memory, wherein the time schedule controller is respectively connected with the power management and programmable gamma buffer chip and the flash memory;
the flash memory is pre-stored with codes required by the power management and programmable gamma buffer chip during working, the power management and programmable gamma buffer chip generates voltage required by the time schedule controller to enable the time schedule controller to work, the time schedule controller works to acquire the register state of the power management and programmable gamma buffer chip in real time and control the output of the power management and programmable gamma buffer chip according to the register state;
the register state represents a power supply state of the power management and programmable gamma buffer chip, which is a circuit to be powered and connected with the power management and programmable gamma buffer chip, wherein the power supply state comprises normal power supply and abnormal power supply.
2. The control circuit of claim 1, wherein the timing controller is coupled to the power management and programmable gamma buffer chip via an I2C bus and detects the power management and programmable gamma buffer chip register state in real time via the I2C bus.
3. The control circuit of claim 2, wherein the timing controller further comprises an enable signal control terminal connected to the enable signal terminal of the power management and programmable gamma buffer chip for controlling the output of the power management and programmable gamma buffer chip according to the register state of the power management and programmable gamma buffer chip.
4. The control circuit of claim 3, wherein if the timing controller obtains the register state as a power supply abnormality, the timing controller outputs a low level to the enable signal terminal of the power management and programmable gamma buffer chip through the enable signal control terminal to control the power management and programmable gamma buffer chip to stop outputting the voltage;
and if the register state obtained by the time sequence controller is normal, the time sequence controller outputs a high level to an enable signal end of the power management and programmable gamma buffer chip through the enable signal control end to control the power management and programmable gamma buffer chip to normally output voltage.
5. The control circuit of claim 1, wherein the timing controller is coupled to the flash memory via an SPI bus.
6. A control method of a control circuit of a display panel according to claim 1, the control method comprising:
the time schedule controller acquires the state of the register in the power management and programmable gamma buffer chip in real time;
and the time schedule controller controls the power supply management and the output of the programmable gamma buffer chip according to the state of the register.
7. The method of claim 6, wherein the timing controller is connected to the power management and programmable gamma buffer chip via an I2C bus and detects the power management and programmable gamma buffer chip register state in real time via the I2C bus.
8. The method as claimed in claim 6, wherein the timing controller further comprises an enable signal control terminal connected to the enable signal terminal of the power management and programmable gamma buffer chip for controlling the output of the power management and programmable gamma buffer chip according to the register state of the power management and programmable gamma buffer chip.
9. The control method according to claim 7, wherein if the register state obtained by the timing controller is abnormal, the timing controller outputs a low level to an enable signal terminal of the power management and programmable gamma buffer chip through the enable signal control terminal to control the power management and programmable gamma buffer chip to stop outputting the voltage;
and if the register state obtained by the time sequence controller is normal, the time sequence controller outputs a high level to an enable signal end of the power management and programmable gamma buffer chip through the enable signal control end to control the power management and programmable gamma buffer chip to normally output voltage.
10. A display device, comprising a display panel and the control circuit of any one of claims 1-5, wherein the control circuit is connected to the display panel for outputting signals to the display panel.
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| CN201911342803.4A CN111105743B (en) | 2019-12-23 | 2019-12-23 | Control circuit and control method of display panel and display device |
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| CN201911342803.4A CN111105743B (en) | 2019-12-23 | 2019-12-23 | Control circuit and control method of display panel and display device |
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| CN111105743B (en) | 2022-10-04 |
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