CN111104362A - Device and method for configuring field programmable gate array and field programmable gate array - Google Patents
Device and method for configuring field programmable gate array and field programmable gate array Download PDFInfo
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- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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Abstract
A device and a method for configuring a field programmable gate array and the field programmable gate array are provided. The device for configuring the field programmable gate array comprises a protocol controller and a data distributor, wherein the protocol controller is configured to read initial data according to a data transmission protocol, convert the initial data to obtain stored data and a data storage address corresponding to the stored data, and output the stored data and the data storage address; the data distributor is connected with the protocol controller, is configured to receive the storage data and the data storage address, and distributes the storage data to at least one storage unit corresponding to the data storage address according to the data storage address for storage. The device improves the efficiency of system level verification of the field programmable gate array.
Description
Technical Field
The embodiment of the disclosure relates to a device and a method for configuring a field programmable gate array and the field programmable gate array.
Background
An FPGA (Field Programmable Gate Array) is a product of further development based on Programmable devices such as PAL (Programmable Array Logic) and GAL (general Logic Array). The FPGA is a semiconductor device formed by a matrix of configurable logic blocks connected by programmable interconnections, and appears as a semi-custom Circuit in the field of ASIC (Application Specific Integrated Circuit), which not only solves the disadvantages of custom circuits, but also overcomes the drawback of limited gate circuits of the original programmable devices.
Disclosure of Invention
At least one embodiment of the present disclosure provides an apparatus for configuring a field programmable gate array, including: the protocol controller is configured to read initial data according to a data transmission protocol, convert the initial data to obtain storage data and a data storage address corresponding to the storage data, and output the storage data and the data storage address; and the data distributor is connected with the protocol controller and is configured to receive the storage data and the data storage address and distribute the storage data to at least one storage unit corresponding to the data storage address according to the data storage address for storage.
For example, an apparatus for configuring a field programmable gate array according to at least one embodiment of the present disclosure further includes an initial memory connected to the protocol controller via a data bus, where the initial memory is configured to store the initial data and send the initial data to the protocol controller according to the data transmission protocol.
For example, in an apparatus for configuring a field programmable gate array provided in at least one embodiment of the present disclosure, the initial memory includes a repeatedly erasable and writable memory.
For example, in an apparatus for configuring a field programmable gate array provided in at least one embodiment of the present disclosure, the protocol controller is further configured to store the data transmission protocol.
For example, in an apparatus for configuring a field programmable gate array provided in at least one embodiment of the present disclosure, the protocol controller includes a data transfer unit and a control unit, the data transfer unit is configured to read the initial data according to the data transmission protocol, convert the initial data into the data storage address and the storage data, and output the data storage address and the storage data; and the control unit is configured to control the data transfer unit to read the initial data and output the data storage address and the storage data.
For example, in an apparatus for configuring a field programmable gate array provided in at least one embodiment of the present disclosure, the data transfer unit includes a protocol implementation unit and a data splicing unit, the protocol implementation unit is configured to read the initial data according to the data transmission protocol, and convert the initial data to obtain the data storage address and the received data, where the received data has a first bit width; and the data splicing unit is configured to acquire the received data from the protocol implementation unit, convert the received data into the stored data, and output the stored data to the data distributor, where the stored data has a second bit width, and the second bit width is different from the first bit width.
For example, in an apparatus for configuring a field programmable gate array provided in at least one embodiment of the present disclosure, the initial data includes the number of the at least one memory unit, the capacity of the at least one memory unit, and the second bit width, where the second bit width is a bit width of a data storage address of the at least one memory unit.
For example, in an apparatus for configuring a field programmable gate array provided in at least one embodiment of the present disclosure, the control unit is further configured to provide the second bit width to the data splicing unit.
For example, in an apparatus for configuring a field programmable gate array provided in at least one embodiment of the present disclosure, the control unit is further configured to: and controlling the operation of reading the initial data by the protocol implementation unit and controlling the operation of acquiring the received data and outputting the stored data to the data distributor by the data splicing unit.
For example, in an apparatus for configuring a field programmable gate array provided in at least one embodiment of the present disclosure, the control unit is further configured to obtain the data storage address from the protocol implementation unit, and output the storage address to the data distributor.
For example, in an apparatus for configuring a field programmable gate array according to at least one embodiment of the present disclosure, the control unit is further configured to control the data distributor to initiate an operation of distributing the storage data to at least one storage unit corresponding to the data storage address according to the data storage address.
At least one embodiment of the present disclosure also provides a field programmable gate array, including: the apparatus for configuring a field programmable gate array of any of the above embodiments; at least one storage unit which is connected with the data distributor of the device for configuring the field programmable gate array and is configured to be capable of being written into the storage data by the data distributor according to the data storage address; and the function processing unit is connected with the at least one storage unit and used for reading the storage data from the at least one storage unit.
For example, in a field programmable gate array provided in at least one embodiment of the present disclosure, the at least one memory cell has a write inhibit function.
At least one embodiment of the present disclosure further provides a method for configuring a field programmable gate array, including: reading initial data according to a data transmission protocol, converting the initial data into storage data, and outputting the storage data and a data storage address corresponding to the storage data; distributing the storage data to at least one storage unit corresponding to the data storage address according to the data storage address for storage; and allowing the functional processing unit to read the stored data from the at least one storage unit.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.
Fig. 1 is a schematic diagram of an apparatus for configuring a field programmable gate array according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a method for configuring a field programmable gate array according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of an apparatus for configuring a field programmable gate array according to another embodiment of the present disclosure;
fig. 4 is a schematic diagram of an apparatus for configuring a field programmable gate array according to another embodiment of the present disclosure;
fig. 5 is a schematic diagram of an apparatus for configuring a field programmable gate array according to another embodiment of the present disclosure;
fig. 6 is a schematic diagram of a field programmable gate array according to an embodiment of the present disclosure; and
fig. 7 is a signal timing diagram of an apparatus for configuring a field programmable gate array according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents.
With the rapid development of technologies such as artificial intelligence, cloud computing, big data processing and the like, FPGAs are widely applied due to their parallel processing capability and programmability, and the capacity of FPGAs is also increased year by year to meet the huge system-level verification requirements. Before the FPGA runs formally, the FPGA needs to be verified at a system level to ensure correctness of the FPGA system level design. An RTL (Register Transfer Level) design in the FPGA generates a bit file after tool compiling, synthesizing and wiring. A bit file is a file generated by a program that produces the bit stream required by the FPGA, which contains configuration information in the circuit. The bit file records RTL design information and maps the design information to FPGA hardware so as to realize an FPGA functional circuit. The design information of the RTL includes information of firmware such as a boot rom, a boot loader, etc., where the firmware includes a program written in an EPROM (Erasable Programmable Read Only Memory) or an EEPROM (Electrically Erasable Programmable Read Only Memory) is used to complete initialization of the system, and the boot rom is usually implemented in the form of a rom, so that the boot rom is fixed as hardware logic together with the RTL design in the FPGA system level verification and cannot be dynamically modified. When the system level verification is carried out, the bit file needs to be regenerated when the starting read-only memory is modified, so that the time for recompiling and generating the bit file is often tens of hours or even longer, the efficiency of the system level test is greatly reduced, and the quick iteration of the system level verification is not facilitated.
The FPGA system level verification usually needs to repeatedly modify the firmware content to realize the comprehensive test of the system, the rapid iteration of the FPGA system level verification is very important for improving the verification efficiency, the firmware is realized in a read-only memory mode, once a bit file of the FPGA is generated, the bit file cannot be changed, and the time for the FPGA to iterate the bit file in large-scale system level design can exceed dozens of hours, even days.
At least one embodiment of the present disclosure provides an apparatus for configuring a field programmable gate array. The device comprises a protocol controller and a data distributor, wherein the protocol controller is configured to read initial data according to a data transmission protocol, convert the initial data into storage data and a data storage address corresponding to the storage data, and output the storage data and the data storage address corresponding to the storage data; the data distributor is connected with the protocol controller, is configured to receive the storage data and the data storage address, and distributes the storage data to at least one storage unit corresponding to the data storage address according to the data storage address for storage.
According to the device for configuring a Field Programmable Gate Array (FPGA), provided by the embodiment of the disclosure, initial data can be obtained from the outside of the FPGA through the protocol controller and the data distributor, and the initial data is converted into storage data to be distributed to the storage unit of the FPGA, so that the storage data is written into the storage unit, and further fast iteration system-level verification can be performed on the FPGA, the system-level verification efficiency can be improved, and therefore the cost can be reduced.
At least one embodiment of the present disclosure also provides a method for configuring a field programmable gate array, and a field programmable gate array including the above apparatus for configuring a field programmable gate array.
Embodiments of the present disclosure and examples thereof are described in detail below with reference to the accompanying drawings.
At least one embodiment of the present disclosure provides an apparatus for configuring a field programmable gate array, and fig. 1 is a schematic block diagram of an apparatus 10 for configuring a field programmable gate array provided in at least one embodiment of the present disclosure.
As shown in fig. 1, the apparatus 10 for configuring a field programmable gate array according to this embodiment includes a protocol controller 110 and a data distributor 120, and an output port of the protocol controller 110 is connected to an input port of the data distributor 120.
For example, in some examples, data distributor 120 includes at least one storage device (e.g., a register). After receiving the data, the data distributor 120 divides the data into at least one storage device, and writes the data in the at least one storage device into storage units of the data according to a storage address corresponding to the data.
For example, in some examples, the protocol controller 110 reads the initial data from outside the FPGA according to a data transmission protocol with a storage device (data source) storing the initial data, converts (e.g., resolves) the read initial data into the storage data and a data storage address corresponding to the storage data, and outputs the storage data and the storage address to the data distributor 120. The data distributor 120 receives the storage data and the data storage address, and the output port of the data distributor 120 may be correspondingly connected to the storage unit included in the storage unit group 130. The memory unit group 130 includes at least one memory unit, and the data distributor 120 includes at least one output port, for example, the memory units are connected to the output ports in a one-to-one correspondence. The data distributor 120 distributes the storage data to the storage unit corresponding to the data storage address according to the data storage address for storage. The storage unit receives the storage data, and the data stored in the storage unit can be read by other functional processing units (not shown in the figure) of the FPGA, so that the storage unit can be used for performing fast iterative system-level verification on the FPGA and improving system-level verification efficiency.
For example, in the present example, the initial data includes data for FPGA system level verification, which may be stored in a storage device external to the FPGA, read by the apparatus 10 for configuring a field programmable gate array, and converted into storage data, and the storage data is distributed to the storage unit group 130. The memory cell group 130 is disposed inside the FPGA, communicates (e.g., is electrically connected) with the data distributor 120, is written with memory data, and can be read by other function processing units (not shown in the figure).
For example, memory cell group 130 includes one or more memory cells (e.g., 2 or more), and as shown in fig. 1, the plurality of memory cells may include memory cell 1, memory cell 2, and memory cell 3 …, where N is a positive integer greater than or equal to 2. The number of the memory cells is not limited in the embodiments of the present disclosure.
For example, in some examples, a data transfer protocol is provided in the protocol controller 110, e.g., the protocol controller 110 has the data transfer protocol stored therein, so that the protocol controller 110 can invoke the data transfer protocol in operation; alternatively, the protocol controller 110 implements the data transfer protocol in hardware.
For example, in some examples, the apparatus 10 for configuring a field programmable gate array is located inside, i.e. as part of, an FPGA device, while the storage device storing the initial data is located outside the FPGA device, communicating with the protocol controller 110 through a data interface (not shown in the figures) that conforms to the aforementioned data transfer protocol. The embodiments of the present disclosure do not limit the data transmission protocol and the data interface.
In this embodiment, the system level verification of the FPGA does not need to regenerate a bit file in order to modify the firmware content, and the data used for the system level verification of the FPGA can be stored in a storage device outside the FPGA and read, converted and distributed to a storage unit by a device configured with a field programmable gate array, so that the FPGA can be used for performing fast iterative system level verification on the FPGA and improving the system level verification efficiency.
At least one embodiment of the present disclosure provides a method of configuring a field programmable gate array, which employs an apparatus as shown in fig. 1. The operation of the apparatus 10 for configuring a field programmable gate array shown in fig. 1 is described below with reference to a flowchart shown in fig. 2.
As shown in fig. 2, the method for configuring a field programmable gate array of the present embodiment includes steps S101 to S103.
Step S101: reading initial data according to a data transmission protocol, converting the initial data into storage data, and outputting the storage data and a data storage address corresponding to the storage data.
For example, in some examples, the initial data includes data for FPGA system level verification, which may be stored in a storage device external to the FPGA.
Step S102: and distributing the storage data to at least one storage unit corresponding to the data storage address according to the data storage address for storage.
Step S103: allowing the functional processing unit to read the stored data from the at least one memory unit.
For example, in some examples, the functional processing unit includes a functional module designed by a user in an FPGA, and can be used to implement technical functions such as digital signal processing and allocating computing resources. The embodiment of the present disclosure does not limit the specific form of the function processing unit.
For example, in some examples, the method may be implemented via HDL (Hardware Description Language). HDL is a language for describing the behavior, structure and data flow of electronic system hardware. With HDL, the method can be described layer by layer from top to bottom (abstract to concrete), each layer consisting of at least one module; performing simulation verification layer by using an Electronic Design Automation (EDA) tool, combining modules which need to be changed into actual circuits in each layer, and converting the modules by using an automatic comprehensive tool to obtain a gate-level circuit netlist; and finally, converting the gate-level circuit netlist into a specific circuit wiring structure by using an automatic layout and wiring tool in the FPGA, and realizing the method in the FPGA through wiring.
At least one embodiment of the present disclosure further provides another apparatus for configuring a field programmable gate array, and fig. 3 is a schematic block diagram of an apparatus 20 for configuring a field programmable gate array provided in at least one embodiment of the present disclosure.
As shown in fig. 3, compared to the embodiment shown in fig. 1, the apparatus 20 for configuring a field programmable gate array of this embodiment includes an initial memory 240 in addition to the protocol controller 210 and the data distributor 220. The output port of the protocol controller 210 is connected to the input port of the data distributor 220, and the protocol controller 210 is connected to the initialization memory 240 through a data bus.
For example, in some examples, the protocol controller 210 reads the initial data from the initial memory 240 according to a data transfer protocol with the initial memory 240 storing the initial data, converts (e.g., resolves) the read initial data into the stored data and a data storage address corresponding to the stored data, and outputs the stored data and the storage address to the data distributor 220. The data distributor 220 receives the storage data and the data storage address, and the output port of the data distributor 220 may be correspondingly connected to the storage unit included in the storage unit group 230. The memory cell group 230 includes at least one memory cell, and the data distributor 220 includes at least one output port, for example, the memory cells are connected to the output ports in a one-to-one correspondence. The data distributor 220 distributes the storage data to the storage unit corresponding to the data storage address according to the data storage address for storage. The storage unit receives the storage data, and the data stored in the storage unit can be read by other function processing units (not shown in the figure) of the FPGA.
For example, in the present example, the initial data includes data for FPGA system level verification, which is stored in the initial memory 240, read by the apparatus 20 for configuring a field programmable gate array, and converted into the storage data, and the storage data is distributed to the storage unit group 230. The memory cell group 230 is disposed inside the FPGA, communicates (e.g., is electrically connected) with the data distributor 220, is written with memory data, and can be read by other function processing units (not shown in the figure).
For example, the memory cell group 230 includes one or more memory cells (e.g., 2 or more), and the plurality of memory cells may include memory cell 1, memory cell 2, and memory cell 3 …, where N is a positive integer equal to or greater than 2.
For example, in some examples, the initial memory 240 is pluggably connected to the protocol controller 210 via a data bus, configured to store initial data, and to send the initial data to the protocol controller 210 according to a data transfer protocol.
For example, in some examples, the initial memory 240 comprises a repeatedly erasable and writable memory, such as an electrically erasable programmable read-only memory (EEPROM), Flash memory (Flash), and the like. Embodiments of the present disclosure are not limited with respect to the specific type of initial memory.
For example, the initial memory 240 may be Flash and has SPI (serial interface) (SPI Flash for short), and the SPI Flash may be programmed quickly and repeatedly, so that initial data may be programmed into the SPI Flash quickly. For another example, Flash may have a CFI interface, and thus CFI Flash is obtained.
For example, in some examples, a data transfer protocol is set in the protocol controller 210, for example, the protocol controller 210 stores the data transfer protocol therein, so that the protocol controller 210 can invoke different hardware according to the data transfer protocol to implement data transfer in operation; alternatively, the protocol controller 210 implements a data transfer protocol (e.g., a fixed protocol) in hardware.
For example, in some examples, the data transfer protocol includes addressing instructions. The address of the initial data stored in the initial memory 240 is stored in the protocol controller 210, and the protocol controller 210 reads the initial data stored in the corresponding address according to the data transmission protocol.
For example, in some examples, the data bus may implement chip select, data transfer, and the like.
For example, in some examples, the protocol controller 210 and the data distributor 220 are located inside, i.e., as part of, an FPGA device.
For example, in some examples, the initial memory 240 may include an interface to be written with data, the interface conforming to the aforementioned data transfer protocol. Thus, the initial memory 240 can be fixedly arranged with the protocol controller 210, and the like, and the initial memory 240 is arranged in the FPGA device; alternatively, in other examples, the initial memory 240 may be taken out of the apparatus 20 configured with the field programmable gate array for an erase write operation. The programmed initial memory 240 is connected to the protocol controller 210 via a bus, so that the initial memory 240 is disposed outside the FPGA device, i.e., an external storage device.
For example, the protocol controller 210 of the apparatus 20 configuring the field programmable gate array may set the protocol controller 210 and the data distributor 220 before reading the initial data from the initial memory 240, and the setting operation includes a reset operation and the like. The reset ports of the protocol controller 210 and the data distributor 220 are connected to I/O ports (input/output ports) of the FPGA, respectively, and after the initial memory 240 is connected to the protocol controller 210 through the bus, the FPGA transmits a reset signal to the protocol controller 210 and the data distributor 220 to reset the protocol controller 210 and the data distributor 220, and the protocol controller 210 after the reset starts reading initial data from the initial memory 240.
In the present embodiment, the initial data can be quickly written into the initial memory 240, for example, when the initial memory 240 is selected as SPI Flash, the writing of the initial data only needs several minutes.
At least one embodiment of the present disclosure further provides an apparatus for configuring a field programmable gate array, and fig. 4 is a schematic block diagram of the apparatus 30 for configuring a field programmable gate array provided in at least one embodiment of the present disclosure.
As shown in fig. 4, the apparatus 30 for configuring a field programmable gate array of the present embodiment includes a protocol controller 310, a data distributor 320, and an initial memory 340, wherein an output port of the protocol controller 310 is connected to an input port of the data distributor 320, and the protocol controller 310 is connected to the initial memory 340 through a data bus. Compared to the embodiment of fig. 3, in the present embodiment, the protocol controller 310 includes a data transfer unit 311 and a control unit 312, and the data transfer unit 311 is connected with the control unit 312.
For example, in some examples, the protocol controller 310 reads initial data from the initial memory 340 according to a data transmission protocol with the initial memory 340, converts the read initial data into storage data and a data storage address corresponding to the storage data, and outputs the storage data and the storage address to the data distributor 320. The data distributor 320 receives the storage data and the data storage address, and the output port of the data distributor 320 may be correspondingly connected to the storage unit included in the storage unit group 330. The memory unit group 330 includes at least one memory unit, and the data distributor 320 includes at least one output port, for example, the memory units are connected to the output ports in a one-to-one correspondence. The data distributor 320 distributes the storage data to at least one storage unit corresponding to the data storage address according to the data storage address. The storage unit receives the storage data, and the data stored in the storage unit can be read by other function processing units (not shown in the figure) of the FPGA.
For example, in the present example, the initial data includes data for FPGA system level verification, is stored in the initial memory 340, is read by the apparatus 30 for configuring a field programmable gate array, is converted into storage data, and distributes the storage data to the storage unit group 330. The memory cell group 330 is disposed inside the FPGA, communicates (e.g., is electrically connected) with the data distributor 320, is written with memory data, and can be read by other function processing units (not shown in the figure).
For example, memory cell group 330 includes one or more memory cells (e.g., 2 or more), and the plurality of memory cells may include memory cell 1, memory cell 2, and memory cell 3 …, where N is a positive integer equal to or greater than 2.
For example, in some examples, the initial data also includes the number of memory cells (N) and the capacity of each memory cell in the group of memory cells 330.
For example, in some examples, the output port of the data transfer unit 311 is connected to the input port of the data distributor 320, and the data transfer unit 311 is connected to the initial memory 340 through a data bus, reads the initial data from the initial memory 340 according to a data transmission protocol, converts the initial data into the storage data and a data storage address corresponding to the storage data, and outputs the storage data and the storage address to the data distributor 320.
For example, in some examples, a data transmission protocol is set in the data transfer unit 311, for example, the data transfer unit 311 stores the data transmission protocol therein, so that the data transfer unit 311 may invoke different hardware according to the data transmission protocol in operation to realize data transmission; alternatively, the data transfer unit 311 implements a data transfer protocol (e.g., a fixed protocol) in a hardware manner.
For example, in some examples, the data transfer unit 311 is connected to the control unit 312, and the control unit 312 is configured to control the data transfer unit 311 to read initial data and output a data storage address and storage data. For example, the control unit 312 sends a first control signal to the data transfer unit 311 to control the operation of the data transfer unit 311 to read initial data and output a data storage address and storage data.
For example, in some examples, the address where the initial data is stored in the initial memory 340 is stored in the control unit 312, and the data transfer unit 311 reads the address of the initial data stored in the control unit 312. The data transfer unit 311 reads the initial data from the initial memory 340 according to the transmission protocol, where the initial data is stored in the initial memory 340 corresponding to the address of the initial data.
For example, in some examples, the initial memory 340 is pluggably connected with the data transfer unit 311 through a data bus, configured to store initial data, and transmit the initial data to the data transfer unit 311 according to a data transmission protocol.
For example, in some examples, the initial memory 340 includes a repeatedly erasable and writable memory, such as an electrically erasable programmable read-only memory (EEPROM), Flash memory (Flash), and the like. Embodiments of the present disclosure are not limited with respect to the specific type of initial memory.
For example, the initial memory 340 may be selected to be Flash and have SPI (serial interface) (SPI Flash for short), and the SPI Flash may be programmed repeatedly and quickly, so that the initial data may be programmed into the SPI Flash quickly. For another example, Flash may have a CFI interface, and thus CFI Flash is obtained.
For example, in some examples, each Memory cell in the Memory cell group 330 is a Read-Only Memory with an added write port, such as a Flash ROM (Flash Read-Only Memory). When the data distributor 320 sends all data to the memory cell group 330, the function of writing data in the memory cell group 330 is turned off, and at this time, the memory cell group 330 is changed to the write-inhibit mode, and data cannot be written any more, and only the function processing unit (not shown in the figure) can read the stored data in the memory cell group 330.
At least one embodiment of the present disclosure further provides an apparatus for configuring a field programmable gate array, and fig. 5 is a schematic block diagram of an apparatus 40 for configuring a field programmable gate array provided in at least one embodiment of the present disclosure.
As shown in fig. 5, the apparatus 40 for configuring a field programmable gate array of the present embodiment includes a protocol controller 410, a data distributor 420, and an initial memory 440, wherein an output port of the protocol controller 410 is connected to an input port of the data distributor 420, and the protocol controller 410 is connected to the initial memory 440 through a data bus. Compared to the embodiment shown in fig. 4, in the present embodiment, the protocol controller 410 includes a data transfer unit 411 and a control unit 412, and the data transfer unit 411 is connected to the control unit 412. The data transmission unit 411 includes a protocol implementation unit 413 and a data splicing unit 414, and the protocol implementation unit 413 is connected to the data splicing unit 414.
For example, in some examples, the initial memory 440 comprises a repeatedly erasable and writable memory, such as an electrically erasable programmable read-only memory (EEPROM), Flash memory (Flash), and the like.
For example, in this example, the initial memory 440 may be selected to be Flash and have SPI (serial interface) (SPI Flash for short), which can be quickly and repeatedly programmed, so that the initial data can be quickly programmed into the SPI Flash.
For example, in some examples, the protocol controller 410 reads initial data from the initial memory 440 according to a data transfer protocol with the initial memory 440, converts the read initial data into storage data and a data storage address corresponding to the storage data, and outputs the storage data and the storage address to the data distributor 420. The data distributor 420 receives the storage data and the data storage address, and the output port of the data distributor 420 may be correspondingly connected to the storage unit included in the storage unit group 430. The memory cell group 430 includes at least one memory cell. The data distributor 420 distributes the storage data to the storage unit group 430 corresponding to the data storage address according to the data storage address. The storage unit receives the storage data, and the data stored in the storage unit can be read by other function processing units (not shown in the figure) of the FPGA.
For example, in the present example, the initial data includes data for FPGA system level verification, is stored in the initial memory 440, is read by the apparatus 40 for configuring a field programmable gate array, is converted into storage data, and distributes the storage data to the storage unit group 430. The memory cell group 430 is disposed inside the FPGA, communicates (e.g., is electrically connected) with the data distributor 420, is written with memory data, and can be read by other function processing units (not shown in the figure).
For example, memory cell group 430 includes one or more memory cells (e.g., 2 or more), and the plurality of memory cells may include memory cell 1, memory cell 2, and memory cell 3 …, where N is a positive integer greater than or equal to 2.
For example, in some examples, the protocol implementation unit 413 is connected to the initial memory 440 through a data bus, reads the initial data from the initial memory 440 according to a data transmission protocol, and converts the initial data into the received data and a data storage address corresponding to the received data. The received data has a first bit width.
For example, in some examples, a data transmission protocol is set in the protocol implementation unit 413, for example, the protocol implementation unit 413 stores the data transmission protocol therein, so that the protocol implementation unit 413 may invoke different hardware according to the data transmission protocol in operation; alternatively, the protocol implementation unit 413 implements a data transmission protocol (e.g., a fixed protocol) in a hardware manner.
For example, in this example, the first bit width is 1 byte (8 bits) wide in the SPI Flash interface standard.
For example, in some examples, the data splicing unit 414 is connected to the protocol implementation unit 413, acquires the received data from the protocol implementation unit 413, converts the received data into the stored data, and outputs the stored data to the data distributor 420. The stored data has a second bit width.
For example, in some examples, the initial data further includes a number of at least one memory cell (N), a capacity of each memory cell in the group of memory cells 430, and a second bit width.
For example, in some examples, the second bit width is a bit width of a data storage address of a memory cell of memory cell group 430. The protocol implementation unit 413 parses the initial data to obtain a second bit width, and sends the second bit width to the data concatenation unit 414.
For example, in some examples, the received data has a first bit width, the stored data has a second bit width, and the first bit width is different from the second bit width.
For example, in some examples, the protocol implementation unit 413 is connected to the control unit 312, and the control unit 412 is configured to control operations of the protocol implementation unit 413 to read initial data and output a data storage address and receive data. For example, the control unit 412 sends a first control signal to the protocol implementation unit 413 to control the operation of the data transfer unit 411 to read initial data and output a data storage address and receive data.
For example, in some examples, the protocol implementation unit 413 reads an address stored in the initial memory 440 of initial data stored in the control unit 412.
For example, in some examples, the control unit 412 is connected to the data distributor 420, and the control unit 412 obtains a data storage address corresponding to the storage data from the protocol implementation unit 413 and sends the data storage address to the data distributor 420.
For example, in some examples, the data stitching unit 414 is connected to the control unit 412, and the control unit 412 is configured to control the operation of the data stitching unit 414 to obtain the received data and convert the received data into the stored data, and output the stored data to the data distributor 420. The control unit 412 sends a second control signal to the data splicing unit 414 to control the operation of the data splicing unit 414 to acquire the received data and output the stored data to the data distributor.
For example, in some examples, the number N of memory cells in the group of memory cells 430, the capacity of each memory cell in the group of memory cells 430, and the second bit width are stored in the control unit 412. The control unit 412 generates a data storage address according to the number N of the at least one memory cell, the capacity of each memory cell in the memory cell group 430, and the second bit width, and sends the data storage address to the data distributor 420 and the second bit width to the data concatenation unit 414.
For example, in some examples, each Memory cell in the Memory cell group 430 is a Read-Only Memory with an added write port, such as a Flash ROM (Flash Read-Only Memory). When the data distributor 420 sends all data to the memory cell group 430, the function of writing data into the memory cell group 430 is turned off, and at this time, the memory cell group 430 changes to the write-inhibit mode, and data cannot be written any more, and only the function processing unit (not shown in the figure) can read the stored data in the memory cell group 430.
At least one embodiment of the present disclosure provides a field programmable gate array, and fig. 6 is a schematic block diagram of the field programmable gate array provided in at least one embodiment of the present disclosure.
As shown in fig. 6, the field programmable gate array includes the apparatus 40 for configuring a field programmable gate array, shown in fig. 5, a memory cell group 530 and a function processing unit 550.
For example, in some examples, the function processing unit 550 includes a user designed circuit, and the specific structure of the function processing unit 550 is not limited herein. The function processing unit 550 is connected to the storage unit group 530, and is configured to read the storage data from the data distributor 530.
An FPGA (Field Programmable Gate Array) sends a reset signal to the protocol implementation unit 413, the data splicing unit 414, the control unit 412, and the reset port Rt of the data distributor 420 through the FPGA input/output port, so that the protocol implementation unit 413, the data splicing unit 414, the control unit 412, and the data distributor 420 are reset.
The first read enable port R _ en1 of the control unit 412 is connected to the read enable port R _ en of the protocol implementation unit 413, the read address port R _ ad of the control unit 412 is connected to the read address port R _ ad of the protocol implementation unit 413, and after the reset signal is released, the control unit 412 sends a read enable signal to the protocol implementation unit 413 through the read enable port R _ en and sends a read address to the protocol implementation unit 413 through the read address port R _ ad, so that the protocol implementation unit 413 reads the initial data stored in the control unit 412 according to the read address under the driving of the read enable signal.
The protocol implementation unit 413 is connected to the initial memory 440 through the chip select port cs _ n, sends a chip select signal to the initial memory 440, is connected to the initial memory 440 through the clock port clk, sends a clock signal to the initial memory 440, is connected to the initial memory 440 through the enable port sdo, and sends a read address to the initial memory 440 according to a data transmission protocol. The initial memory 440 is connected to the initial memory 440 through the read port sdi, and the initial memory 440 returns the initial data of the corresponding address to the protocol implementation unit 413 through the read port sdi according to the read address sent by the protocol implementation unit 413. The protocol implementation unit 413 obtains the received data, the storage address, and the second bit width by converting the initial data. Wherein the received data has a first bit width.
The protocol implementation unit 413 is connected to the write address port W _ ad of the control unit 412 via the first write address port W _ ad1, and sends the memory address and the second bit width to the control unit 412.
The control unit 412 is connected to the read enable port R _ en of the data splicing unit 414 through the second read enable port R _ en2, and sends the read enable and the second bit width to the data splicing unit 414. The data splicing unit 414 is connected to the read data port R _ d of the protocol implementation unit 413 through the data input port In _ d, and obtains the received data from the protocol implementation unit 413, and converts the received data into the stored data, where the stored data has a second bit width. For example, the data conversion mode may select data splicing, in which received data having a first bit width is spliced into stored data having a second bit width.
For example, the data stitching unit 414 is connected to the data input port In _ d of the data distributor 420 through the write data port W _ d, and transmits the storage data having the second bit width to the data distributor 420.
For example, in some examples, the data stitching unit 414 completes transmitting a store data having the second bit width to generate a corresponding transfer complete signal. The data splicing unit 414 connects the transmission completion port FIN with the transmission completion port FIN of the control unit 412, and the data splicing unit 414 sends a transmission completion signal to the transmission completion port FIN of the control unit 412 through the transmission completion port FIN. For example, the control unit 412 is connected with the write enable port W _ en of the data distributor 420 through the write enable port W _ en, and is connected with the write address port W _ ad of the data distributor 420 through the second write address port W _ ad 2. The control unit 412, after receiving the transmission completion signal sent by the data splicing unit 414, sends the storage address to the data distributor 420, and sends write enable to the data distributor 420.
For example, the memory cell group 530 is connected to the data distributor 420, and the memory cell group 530 includes at least one memory cell. The number of memory cells and the capacity of each memory cell can be set according to actual requirements.
For example, in some examples, as shown in FIG. 6, memory cell group 530 includes four memory cells. The four storage units are storage unit 531, storage unit 532, storage unit 533, and storage unit 534, respectively. The data distributor 420 is connected to the memory cell group 530 through the address distribution port Mem _ ad. The data distributor 420 is respectively correspondingly connected to the data receiving ports of the storage unit 531, the storage unit 532, the storage unit 533, and the storage unit 534 through the data distribution ports Mem _ d _1, Mem _ d _2, Mem _ d _3, and Mem _ d _4, and distributes the stored data to the corresponding storage units according to the storage addresses. For example, in other examples, the data splicing unit 414 may further send the final transmission completion signal to the transmission completion port FIN of the control unit 412 through the transmission completion port FIN after sending all the storage data with the second bit width to the data distributor 420.
For example, in some examples, after the control unit 412 receives the last transmission completion signal or the final transmission completion signal sent by the data splicing unit 414, the control unit 412 sends a write enable pause signal to the write enable port W _ en of the data distributor 420 through the write enable port W _ en, the data distributor 420 turns off the write data function, at this time, the memory cell group 530 has the write disable function, the memory cell group 530 operates as a read-only memory cell, data cannot be written any more, and only the function processing unit 550 can read the stored data in the memory cell group 530.
For example, in other examples, the total address capacity of the memory cell group 530 is stored in the control unit 412, when the total amount of memory addresses transmitted by the control unit 412 to the write address port W _ ad of the data distributor 420 through the second address port W _ ad2 reaches the total address capacity of the memory cell group 530, the control unit 412 transmits a write enable pause signal to the write enable port W _ en of the data distributor 420 through the write enable port W _ en, the data distributor 420 turns off the write data function, the memory cells of the memory cell group 530 at this time have the write inhibit function, the memory cell group 530 operates as a read-only memory cell, cannot be written with data any more, and only the memory data in the memory cell group 530 can be read by the function processing unit 550.
For example, in some examples, after the data distributor 420 turns off the write data function, a reset signal is sent to the reset port Rt of the function processing unit 550 through the reset release port R _ Rt, so that the function processing unit 550 starts up normally.
For example, in some examples, after the functional processing unit 550 boots up, the memory data is read from the memory cell group 530 to implement system level verification. If the stored data needs to be modified, only the current initial data in the initial memory 440 needs to be erased, new initial data is written, and then the initial memory 440 is connected to the protocol controller 410 to start a new round of system level verification.
The operation of the apparatus 40 for configuring a field programmable gate array shown in fig. 5 is explained with reference to a signal timing chart shown in fig. 7, wherein five stages, including a first stage a, a second stage b, a third stage c, a fourth stage d and a fifth stage e, are collectively shown in fig. 7, and the detailed process is as follows.
In the first stage a (reset stage), the FPGA transmits a reset signal to the control unit 412, the protocol implementation unit 413, the data splicing unit 414, and the reset port Rt of the data distributor 420 through the input/output port, and the control unit 412, the protocol implementation unit 413, the data splicing unit 414, and the data distributor 420 are reset.
In the second stage b, after the control unit 412, the protocol implementation unit 413, the data splicing unit 414 and the data distributor 420 complete resetting, the control unit 412 sends a read enable to the read enable port R _ en of the protocol implementation unit 413 through the first read enable port R _ en1, sends a read enable to the read address port R _ ad of the protocol implementation unit 413 through the read address port R _ ad, and sends the read enable and the second bit width to the read enable port R _ en of the data splicing unit 414 through the second read enable port R _ en 2.
In the third stage c, the protocol implementation unit 413 sends a read address to the initial memory 440 through the enable port sdo; the initial memory 440 transmits corresponding initial data to the read port sdi of the protocol implementation unit 413 according to the read address.
In the fourth stage d, the data splicing unit 414 obtains the received data from the protocol implementation unit 413 through the data input port In _ d, where the received data has the first bit width, and the data splicing unit 414 splices the received data into the stored data, where the stored data has the second bit width. The data stitching unit 414 sends the storage data to the data distributor 420 through the write data port W _ d, and the control unit 412 sends the storage address to the data distributor 420 through the second write address port W _ ad 2.
In the fifth stage e, the second bit width of the stored data is different from the second bit width in the fourth stage d, and the time step taken by the data splicing unit 414 to splice the received data into the stored data changes with the change of the second bit width.
In the fourth stage d and the fifth stage e, the data concatenation unit 414 completes transmission of a storage data with the second bit width to generate a corresponding transmission completion signal. The data splicing unit 414 connects the transmission completion port FIN with the transmission completion port FIN of the control unit 412, and the data splicing unit 414 sends a transmission completion signal to the transmission completion port FIN of the control unit 412 through the transmission completion port FIN. After receiving the last transmission completion signal sent by the data splicing unit 414, the control unit 412 sends a write enable pause signal to the write enable port W _ en of the data distributor 420 through the write enable port W _ en, and the data distributor 420 closes the write data function, at this time, the storage unit group 430 has a write-inhibit function, cannot be written with data any more, and only the function processing unit can read the storage data in the storage unit group 430.
The following points need to be explained:
(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.
(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present disclosure, and shall be covered by the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (14)
1. An apparatus to configure a field programmable gate array, comprising:
the protocol controller is configured to read initial data according to a data transmission protocol, convert the initial data to obtain storage data and a data storage address corresponding to the storage data, and output the storage data and the data storage address; and
and the data distributor is connected with the protocol controller and is configured to receive the storage data and the data storage address and distribute the storage data to at least one storage unit corresponding to the data storage address according to the data storage address for storage.
2. The apparatus of claim 1, further comprising:
an initial memory connected to the protocol controller through a data bus,
wherein the initial memory is configured to store the initial data and to transmit the initial data to the protocol controller according to the data transmission protocol.
3. The apparatus of claim 2, wherein the initial memory comprises a repeatedly erasable and writable memory.
4. The apparatus of claim 1, wherein the protocol controller is further configured to store the data transmission protocol.
5. The apparatus of claim 1, wherein the protocol controller comprises a data transfer unit and a control unit,
the data transmission unit is configured to read the initial data according to the data transmission protocol, convert the initial data into the data storage address and the storage data, and output the data storage address and the storage data; and
the control unit is configured to control the data transfer unit to read the initial data and output the data storage address and the storage data.
6. The apparatus of claim 5, wherein the data transfer unit comprises a protocol implementation unit and a data splicing unit,
the protocol implementation unit is configured to read the initial data according to the data transmission protocol, and convert the initial data to obtain the data storage address and received data, where the received data has a first bit width; and
the data stitching unit is configured to obtain the received data from the protocol implementation unit and convert the received data into the stored data, and output the stored data to the data distributor, the stored data having a second bit width,
wherein the second bit width is different from the first bit width.
7. The apparatus of any of claims 1-6, wherein the initial data comprises a number of the at least one memory location, a capacity of the at least one memory location, and the second bit width,
the second bit width is a bit width of a data storage address of the at least one storage unit.
8. The apparatus of claim 7, wherein the control unit is further configured to provide the second bit width to the data stitching unit.
9. The apparatus of any of claims 1-6, wherein the control unit is further configured to:
controlling the operation of the protocol implementation unit to read the initial data, an
And controlling the data splicing unit to acquire the received data and output the stored data to the data distributor.
10. The apparatus of any of claims 1-6, wherein the control unit is further configured to obtain the data storage address from the protocol implementation unit and output the storage address to the data distributor.
11. The apparatus according to any of claims 1-6, wherein the control unit is further configured to control the data distributor to initiate an operation of distributing the storage data according to the data storage address to at least one storage unit corresponding to the data storage address.
12. A field programmable gate array, comprising:
an apparatus for configuring a field programmable gate array as claimed in any one of claims 1 to 11;
at least one storage unit which is connected with the data distributor of the device for configuring the field programmable gate array and is configured to be capable of being written into the storage data by the data distributor according to the data storage address; and
and the function processing unit is connected with the at least one storage unit and used for reading the storage data from the at least one storage unit.
13. The field programmable gate array of claim 12, wherein the at least one memory cell has a write inhibit function.
14. A method of configuring a field programmable gate array, comprising:
reading initial data according to a data transmission protocol, converting the initial data into storage data, and outputting the storage data and a data storage address corresponding to the storage data;
distributing the storage data to at least one storage unit corresponding to the data storage address according to the data storage address for storage; and
allowing the functional processing unit to read said stored data from said at least one memory unit.
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