CN111104357B - Automatic addressing method and device for multiple slave control modules - Google Patents
Automatic addressing method and device for multiple slave control modules Download PDFInfo
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- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
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- G06F13/4027—Coupling between buses using bus bridges
- G06F13/404—Coupling between buses using bus bridges with address mapping
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- H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
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Abstract
The invention provides an automatic addressing method and device for multiple slave control modules, which are used for detecting whether the connection between a master control module and a first-stage slave control module is normal or not, and alarming if the connection is abnormal; if the first PWM signal is normal, the main control module sends a first PWM signal containing the address information of the first-stage slave control module to the first-stage slave control module; the first-stage slave control module receives the first PWM signal and analyzes the first PWM signal to obtain corresponding address information, detects whether the connection between the first-stage slave control module and the second-stage slave control module is normal or not, if the connection is abnormal, the first-stage slave control module feeds the abnormal information back to the master control module, and if the connection is normal, the first-stage slave control module sends a second PWM signal containing the address information of the second-stage slave control module to the second-stage slave control module; and repeating the process until the last-stage slave control module receives the PWM signal which is sent by the last-stage slave control module and contains the address information of the last-stage slave control module. The accuracy and efficiency of addressing of the slave control module are improved, and the occurrence of wrong addressing state and non-addressing state is prevented.
Description
Technical Field
The invention belongs to the technical field of multi-node address identification and battery management system addressing, and particularly relates to an automatic addressing method and device for multiple slave control modules.
Background
With the application development of the single chip microcomputer technology, a considerable number of systems are more and more complex in structure, the number of sub nodes contained in the same system is more and more, and in order to manage data of the sub nodes and prevent the data from being unrecognized by a host due to the ID problem among the sub nodes, a simple and reliable addressing mode is needed to realize the distinction among the sub nodes.
In the field of new energy application, the battery management system is a key component, and is composed of a master control module and a plurality of slave control modules. Because the number of the battery modules is large, the physical distribution is complex, the workload of manually addressing the slave control modules is large, and errors are easy to occur.
In order to solve the problem of addressing of the battery modules, addressing of the slave battery modules is carried out in a level identification mode and a PWM identification mode. The level identification mode is the simplest automatic addressing mode, and the realization mode is that the I/O level of a port is detected by a slave control module, whether automatic addressing is needed currently is judged through the change of the I/O level, the I/O level is fixed, fixed address coding is carried out on the I/O level through an upper computer, and then interactive confirmation is carried out on the I/O level and the master control module. However, the coding method is inefficient, and since the slave control module and the battery module are integrated, when any one of the slave control module and the battery module fails, the slave control module needs to be coded and then installed together, thereby increasing the maintenance cost. In addition, when the I/O level is abnormal, the system can not identify, so that the system can enter a wrong addressing state or an unaddressed state. In addition, because the system wiring harness is more and complicated, in order to reduce the complexity of the system wiring harness, the automatic addressing signal not only realizes the addressing function in the system, but also needs to complete the alarming function.
In addition, the PWM automatic addressing mode can not only finish the automatic addressing of the multiple acquisition modules independently, but also finish the automatic addressing of the multiple acquisition modules by matching with a bus communication mode. For example, in the chinese patent application with publication number "CN 107508930A," entitled "ID assignment method and system," a method for assigning addresses to slave control units using PWM waves is proposed, but the addressing lines are also unidirectional, and they cannot complete the function of returning a hard-line alarm, resulting in low level and low accuracy of the slave control module addressing accuracy.
Disclosure of Invention
The invention aims to provide an automatic addressing method for multiple slave control modules, which is used for solving the problems of low addressing accuracy and low addressing efficiency of the slave control modules in the prior art; meanwhile, an automatic addressing device of the multiple slave control modules is also provided.
In order to achieve the above object, the present invention provides an automatic addressing method for multiple slave control modules, wherein the slave control modules in the addressing method are connected in a cascade manner, and the method comprises the following steps:
1) detecting whether the connection between the master control module and the first-stage slave control module is normal or not, and if the connection is abnormal, alarming; if the connection is normal, the main control module sends a first PWM signal containing the address information of the first-stage slave control module to the first-stage slave control module;
2) the first-stage slave control module receives the first PWM signal and analyzes the first PWM signal to obtain corresponding address information, whether the connection between the first-stage slave control module and the second-stage slave control module is normal or not is detected, if the connection is abnormal, the first-stage slave control module feeds the abnormal information back to the master control module, and if the connection is normal, the first-stage slave control module sends a second PWM signal containing the address information of the second-stage slave control module to the second-stage slave control module;
3) and repeating the step 2) until the last-stage slave control module receives the PWM signal which is sent by the last-stage slave control module and contains the address information of the last-stage slave control module.
The method comprises the steps of addressing a slave control module through a PWM signal, detecting whether the connection between a master control module and a first-stage slave control module is normal or not, and alarming if the connection is abnormal; if the connection is normal, the main control module sends a first PWM signal containing the address information of the first-stage slave control module to the first-stage slave control module; the first-stage slave control module receives the first PWM signal and analyzes the first PWM signal to obtain corresponding address information, whether the connection between the first-stage slave control module and the second-stage slave control module is normal or not is detected, if the connection is abnormal, the first-stage slave control module feeds the abnormal information back to the master control module, and if the connection is normal, the first-stage slave control module sends a second PWM signal containing the address information of the second-stage slave control module to the second-stage slave control module; and repeating the process until the last-stage slave control module receives the PWM signal which is sent by the last-stage slave control module and contains the address information of the last-stage slave control module. The accuracy and efficiency of addressing of the slave control module are improved, and the occurrence of wrong addressing state and non-addressing state is prevented.
In order to obtain the PWM signal, the process of forming the PWM signal is: and forming a PWM signal containing address information by adjusting the PWM duty ratio.
In order to judge whether the connection between the modules is normal, if any one stage of slave control module is abnormal, the receiving of the PWM signal of the previous stage of slave control module is stopped, the divider resistor in the PWM receiving input port in the slave control module is released, so that the previous stage of slave control module detects the abnormality, and the divider resistor in the PWM receiving input port in each slave control module is sequentially released according to the direction opposite to the cascade direction, so that the master control module detects the abnormality.
The invention also provides an automatic addressing device of the multiple slave control modules, which comprises a master control module and at least two slave control modules, wherein the master control module is sequentially connected with the slave control modules in a cascade way, a PWM driving output port is arranged in the master control module, and each slave control module is provided with a PWM receiving input port and a PWM driving output port; the PWM driving output port of the master control module detects whether the connection between the master control module and the first-stage slave control module is normal or not, and if the connection is abnormal, an alarm is given; if the connection is normal, the PWM driving output port of the main control module sends a first PWM signal containing the block address information of the first-stage slave control module to the first-stage slave control module;
the PWM receiving input port of the first-stage slave control module receives the first PWM signal and then analyzes the first PWM signal to obtain corresponding address information, whether the connection between the first-stage slave control module and the second-stage slave control module is normal or not is detected, if the connection is abnormal, the first-stage slave control module feeds the abnormal information back to the main control module, and if the connection is normal, the PWM driving output port of the first-stage slave control module sends a second PWM signal containing the address information of the second-stage slave control module to the second-stage slave control module;
and repeating the process until the last-stage slave control module receives the PWM signal which is sent by the PWM driving output port of the last-stage slave control module and contains the address information of the last-stage slave control module.
The method comprises the steps of addressing a slave control module through a PWM signal, detecting whether the connection between a master control module and a first-stage slave control module is normal or not, and alarming if the connection is abnormal; if the connection is normal, the main control module sends a first PWM signal containing the address information of the first-stage slave control module to the first-stage slave control module; the first-stage slave control module receives the first PWM signal and analyzes the first PWM signal to obtain corresponding address information, whether the connection between the first-stage slave control module and the second-stage slave control module is normal or not is detected, if the connection is abnormal, the first-stage slave control module feeds the abnormal information back to the master control module, and if the connection is normal, the first-stage slave control module sends a second PWM signal containing the address information of the second-stage slave control module to the second-stage slave control module; and repeating the process until the last-stage slave control module receives the PWM signal which is sent by the last-stage slave control module and contains the address information of the last-stage slave control module. The accuracy and efficiency of addressing of the slave control module are improved, and the occurrence of wrong addressing state and non-addressing state is prevented.
In order to obtain the PWM signal, the process of forming the PWM signal is: and forming a PWM signal containing address information by adjusting the PWM duty ratio.
Furthermore, the PWM driving output port comprises a high-level output unit, a PWM driving output unit and a voltage amplitude detection unit, and the PWM receiving input port comprises a PWM input detection unit and a resistance pull-down detection unit; the judgment process of the abnormal connection of any level of slave control module is as follows: the high-level output unit of the PWM driving output port in the upper-level slave control module outputs a high-level signal to the PWM receiving input port of the lower-level slave control module, the resistance pull-down detection unit in the PWM receiving input port of the lower-level slave control module detects the voltage of the PWM receiving input port, if the voltage changes, the connection between the upper-level slave control module and the lower-level slave control module is normal, the PWM driving output unit of the PWM driving output port in the upper-level slave control module outputs a corresponding PWM signal to the lower-level slave control module, and the PWM input detection unit of the lower-level slave control module analyzes the received PWM signal to acquire corresponding address information.
In order to judge whether the connection between the modules is normal, if any one stage of slave control module is abnormal, the receiving of the PWM signal of the previous stage of slave control module is stopped, the divider resistor in the PWM receiving input port in the slave control module is released, so that the previous stage of slave control module detects the abnormality, and the divider resistor in the PWM receiving input port in each slave control module is sequentially released according to the direction opposite to the cascade direction, so that the master control module detects the abnormality.
Drawings
FIG. 1 is a block diagram of an automatic addressing device of a multi-slave control module according to the present invention;
FIG. 2 is a block diagram of a main control module according to the present invention;
FIG. 3 is a block diagram of the slave module according to the present invention;
fig. 4 is a diagram of a detection circuit for detecting the connection relationship between an upper module and a lower module according to the present invention.
Detailed Description
The following further describes embodiments of the present invention with reference to the drawings:
the invention provides an automatic addressing device of multiple slave control modules, which comprises a master control module and at least two slave control modules, wherein the master control module is sequentially connected with the slave control modules in a cascade manner, as shown in figure 1. The master control module is provided with a PWM driving output port, and each slave control module is provided with a PWM receiving input port and a PWM driving output port; the master control module is provided with a PWM driving output port, and each slave control module is provided with a PWM receiving input port and a PWM driving output port. The PWM driving output port of the master control module is connected with the PWM receiving input port of the next-stage slave control module, the current slave control module is connected with the PWM receiving input port of the next-stage slave control module through the PWM driving output port, namely, the slave control module with the address of i is connected with the PWM receiving input port of the slave control module with the address of i +1 through the PWM driving output port, and the slave control module with the address of i is connected with the PWM driving output port of the slave control module with the address of i-1 through the PWM receiving input port.
The PWM driving output port of the master control module detects whether the connection between the master control module and the first-stage slave control module is normal or not, and if the connection is abnormal, an alarm is given; if the connection is normal, the PWM driving output port of the main control module sends a first PWM signal containing the block address information of the first-stage slave control module to the first-stage slave control module; the first-stage slave control module receives the first PWM signal through a PWM receiving input port, analyzes the first PWM signal to obtain corresponding address information, detects whether the connection between the first-stage slave control module and the second-stage slave control module is normal or not, if the connection is abnormal, the first-stage slave control module feeds the abnormal information back to the master control module, and if the connection is normal, the first-stage slave control module sends a second PWM signal containing the address information of the second-stage slave control module to the second-stage slave control module through a PWM driving output port of the first-stage slave control module; and repeating the process until the last-stage slave control module receives the PWM signal which is sent by the PWM driving output port of the last-stage slave control module and contains the address information of the last-stage slave control module.
As shown in fig. 2, the PWM driving output port of the main control module includes three parts, namely a high level output unit, a PWM driving output unit and a voltage amplitude detection unit. The processor outputs high level through high side driving, outputs PWM through frequency modulation and driving, and the voltage amplitude detection unit is used for detecting the voltage amplitude of the port. As shown in fig. 3, the slave control module processes the addressed information into a PWM receive input port and a PWM drive output port. The PWM driving output port comprises a high level output unit, a PWM driving output unit and a voltage amplitude detection unit. The processor outputs high level through high side driving, outputs PWM through frequency modulation and driving, and the voltage amplitude detection unit is used for detecting the voltage amplitude of the port. The PWM receiving input port comprises a PWM input detection unit and a resistance pull-down detection unit. The high-level output unit of the PWM driving output port in the upper-level slave control module outputs a high-level signal to the PWM receiving input port of the lower-level slave control module, the resistance pull-down detection unit in the PWM receiving input port of the lower-level slave control module detects the voltage of the PWM receiving input port, if the voltage changes, the connection between the upper-level slave control module and the lower-level slave control module is normal, the PWM driving output unit of the PWM driving output port in the upper-level slave control module outputs a corresponding PWM signal to the lower-level slave control module, and the PWM input detection unit of the lower-level slave control module analyzes the received PWM signal to acquire corresponding address information.
Taking the example that the master module sends the addressing information to the slave module as an example, as shown in fig. 4, the port driver 11 of the high-level output unit of the master module is grounded through the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2, and the connection point of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 is connected to the port detector 21 of the resistor pull-down detection unit of the lower module; the high-level output unit is also grounded with a switch tube Q1 through a third voltage-dividing resistor R3, a port driver 21 is connected with a processor of the slave control module, a port driver 12 of a PWM (pulse-width modulation) drive output unit of the master control module outputs a PWM wave containing programming information of the slave control module, an input end of a switch tube Q1 is connected with a port detector 22 of a PWM drive input detection unit of the slave control module, and the detector 22 detects the PWM wave output by the PWM drive output unit of the master control module to analyze the PWM wave and address the slave control module. In order to prevent the current in the first branch circuit from not meeting a set value, a current limiting resistor R is connected between the high-level output unit and one end of the third voltage dividing resistor in series, the other end of the third voltage dividing resistor R3 is connected with the input end of the switching tube Q1, and an anti-reverse diode D is arranged at one end of the third voltage dividing resistor R3 and one end of the current limiting resistor R. And if the amplitude of the voltage output by the PWM driving output unit is changed, the connection point of the current limiting resistor R and the anti-reverse diode D is grounded through a fourth voltage-dividing resistor R4 and a fifth voltage-dividing resistor R5.
Based on the system, the automatic addressing method for the multiple slave control modules of the embodiment comprises the following steps:
1. in the initial state, the PWM driving output ports of the master control module and the slave control module are in a non-output state.
2. When the addressing state is entered, the master control module drives the output port to output the high level output by the high level output unit of the processor to the port through the PWM, at this time, the next-stage slave control module connected with the master control module can detect the current level voltage of the connected port through the resistance pull-down detection unit of the PWM receiving input port, that is, the detection unit 21 in fig. 4 detects whether the voltage changes, if so, the connection between the master control module and the slave control module is normal, otherwise, the connection is abnormal. The voltage output by the main control module may be 24V or 12V, and if the voltage output by the high-level output unit of the driving output port of the main control module passes through the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 and then changes, that is, is no longer 24V, it indicates that the connection is normal; if the voltage output by the high-level output unit of the driving output port of the main control module changes after passing through the first voltage-dividing resistor and the second voltage-dividing resistor, namely is no longer 12V, the connection is normal.
3. If the master control module and the slave control module are normally connected, a processor of the slave control module sends a driving signal to the switching tube to control the switching tube to be conducted, the third voltage dividing resistor R3 divides voltage, at this time, a voltage amplitude detection unit of the master control module detects that the voltage output by a high level output unit of the master control module changes through the fourth voltage dividing resistor R4 and the fifth voltage dividing resistor R5, addressing information is modulated into PWM (the duty ratio is 5% x n, n is a serial number containing addressing address information required by the slave control module, of course, the duty ratio base number can also be adjusted according to the actual application requirement and is not fixed to 5%), and the driving output unit is output to the next slave control module through the PWM in the master control module.
4. The slave control module detects the current input PWM frequency through a PWM input detection unit in a PWM receiving input port, compares and decodes the current input PWM frequency to obtain the address information which needs to be written into a processor at present, writes the address information into the processor of the slave control module, and completes addressing and writing of the current slave control module.
5. The automatic addressing between the slave control modules is similar to the addressing between the master control module and the first-level slave control module.
Assuming that the slave module to be addressed currently is k, the previous slave module address is k-1 (assuming that the slave module address k-1 is known as i).
The slave control module k-1 outputs a high level signal to a PWM input port of a next-level slave control module k connected with the slave control module k through a PWM port, after the slave control module k detects the high level, the current high level signal is pulled down through a voltage dividing resistor on the slave control module k, and the slave control module k-1 judges whether the current slave control module k is reliably connected with the slave control module k-1 and whether detection circuits of the current slave control module k and the slave control module k-1 are normal through voltage diagnosis of the PWM port. If the slave control module k-1 passes the voltage diagnosis of the PWM port, PWM with fixed frequency is output. And after the slave control module k connected with the slave control module k-1 detects the PWM signal, performing reverse decoding to acquire the current address information as i +1, and writing the current address information into a processor of the slave control module k to finish the addressing of the current slave control module k.
6. In the process, if the slave control module detects that the slave control module is abnormal, the voltage-dividing resistor in the PWM receiving input port in the slave control module is released, so that the previous-stage module detects that the slave control module has a fault, and according to the method, the voltage-dividing resistors on the slave control modules are sequentially released, and therefore the fault message is uploaded to the master control module through the hard wire signal. If the third-level slave control module is abnormal in connection, the divider resistor in the PWM receiving input port in the third-level slave control module is released, the second-level slave control module detects the abnormality, the divider resistor in the PWM receiving input port in the third-level slave control module is released, the master control module detects the abnormality, and finally the master control module sends out abnormal connection alarm information.
The specific embodiments are given above, but the present invention is not limited to the above-described embodiments. The basic idea of the present invention lies in the above basic scheme, and it is obvious to those skilled in the art that no creative effort is needed to design various modified models, formulas and parameters according to the teaching of the present invention. Variations, modifications, substitutions and alterations may be made to the embodiments without departing from the principles and spirit of the invention, and still fall within the scope of the invention.
Claims (4)
1. The automatic addressing method for the multiple slave control modules is characterized by comprising the following steps of:
1) detecting whether the connection between the master control module and the first-stage slave control module is normal or not, and if the connection is abnormal, alarming; if the connection is normal, the main control module sends a first PWM signal containing the address information of the first-stage slave control module to the first-stage slave control module;
2) the first-stage slave control module receives the first PWM signal and analyzes the first PWM signal to obtain corresponding address information, whether the connection between the first-stage slave control module and the second-stage slave control module is normal or not is detected, if the connection is abnormal, the first-stage slave control module feeds the abnormal information back to the master control module, and if the connection is normal, the first-stage slave control module sends a second PWM signal containing the address information of the second-stage slave control module to the second-stage slave control module;
3) repeating the step 2) until the last-stage slave control module receives the PWM signal which is sent by the last-stage slave control module and contains the address information of the last-stage slave control module;
if any one of the slave control modules is abnormal in connection, stopping receiving the PWM signal of the previous slave control module, releasing the divider resistors in the PWM receiving input ports in the slave control modules to enable the previous slave control module to detect the abnormality, and sequentially releasing the divider resistors in the PWM receiving input ports in the slave control modules in the direction opposite to the cascade direction to enable the master control module to detect the abnormality.
2. The method for multi-slave module automatic addressing according to claim 1, wherein the PWM signal is formed by the following steps: and forming a PWM signal containing address information by adjusting the PWM duty ratio.
3. The automatic addressing device for the multiple slave control modules comprises a master control module and at least two slave control modules, wherein the master control module is sequentially connected with the slave control modules in a cascade manner;
a) the PWM driving output port of the master control module detects whether the connection between the master control module and the first-stage slave control module is normal or not, and if the connection is abnormal, an alarm is given; if the connection is normal, the PWM driving output port of the main control module sends a first PWM signal containing the block address information of the first-stage slave control module to the first-stage slave control module;
b) the PWM receiving input port of the first-stage slave control module receives the first PWM signal and then analyzes the first PWM signal to obtain corresponding address information, whether the connection between the first-stage slave control module and the second-stage slave control module is normal or not is detected, if the connection is abnormal, the first-stage slave control module feeds the abnormal information back to the main control module, and if the connection is normal, the PWM driving output port of the first-stage slave control module sends a second PWM signal containing the address information of the second-stage slave control module to the second-stage slave control module;
c) repeating the step b) until the last-stage slave control module receives a PWM signal which is sent by a PWM driving output port of the last-stage slave control module and contains the address information of the last-stage slave control module;
the PWM driving output port comprises a high-level output unit, a PWM driving output unit and a voltage amplitude detection unit, and the PWM receiving input port comprises a PWM input detection unit and a resistor pull-down detection unit; the judgment process of the abnormal connection of any level of slave control module is as follows: a high level output unit of a PWM driving output port in a previous-stage slave control module outputs a high level signal to a PWM receiving input port of a next-stage slave control module, a resistance pull-down detection unit in the PWM receiving input port of the next-stage slave control module detects the voltage of the PWM receiving input port, if the voltage changes, the connection between the previous-stage slave control module and the next-stage slave control module is normal, the PWM driving output unit of the PWM driving output port in the previous-stage slave control module outputs a corresponding PWM signal to the next-stage slave control module, and a PWM input detection unit of the next-stage slave control module analyzes the received PWM signal to acquire corresponding address information;
if any stage of slave control module is abnormal in connection, stopping receiving the PWM signal of the previous stage, releasing the divider resistors in the PWM receiving input ports in the slave control modules to enable the slave control modules of the previous stage to detect the abnormality, and sequentially releasing the divider resistors in the PWM receiving input ports in the slave control modules according to the direction opposite to the cascade direction to enable the master control module to detect the abnormality.
4. The multiple slave control module automatic addressing device according to claim 3, wherein the PWM signal is formed by: and forming a PWM signal containing address information by adjusting the PWM duty ratio.
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| US9928196B2 (en) * | 2015-09-30 | 2018-03-27 | International Business Machines Corporation | Programming interface operations in a driver in communication with a port for reinitialization of storage controller elements |
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| CN107508930A (en) * | 2017-09-15 | 2017-12-22 | 上海炙云新能源科技有限公司 | ID distribution methods and system |
| CN108333527A (en) * | 2018-02-06 | 2018-07-27 | 中航锂电技术研究院有限公司 | Battery management system loop interlock and from control address setting method |
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