CN111103915A - Direct current offset cancelling circuit - Google Patents

Direct current offset cancelling circuit Download PDF

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Publication number
CN111103915A
CN111103915A CN201910650910.7A CN201910650910A CN111103915A CN 111103915 A CN111103915 A CN 111103915A CN 201910650910 A CN201910650910 A CN 201910650910A CN 111103915 A CN111103915 A CN 111103915A
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mos transistor
resistor
source
mos
nmos2
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王日炎
周伶俐
朱智勇
贺黉胤
何俊良
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GUANGZHOU RUNXIN INFORMATION TECHNOLOGY CO LTD
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GUANGZHOU RUNXIN INFORMATION TECHNOLOGY CO LTD
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Publication of CN111103915A publication Critical patent/CN111103915A/en
Priority to DE102020118913.3A priority patent/DE102020118913A1/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/30—Circuits for homodyne or synchrodyne receivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/12—Frequency selective two-port networks using amplifiers with feedback
    • H03H11/1217—Frequency selective two-port networks using amplifiers with feedback using a plurality of operational amplifiers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/30—Circuits for homodyne or synchrodyne receivers
    • H04B2001/305—Circuits for homodyne or synchrodyne receivers using dc offset compensation techniques

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a direct current offset cancellation circuit which comprises a resistor R1-a resistor R7, an operational amplifier OPA1, an operational amplifier OPA2, a capacitor C1, a capacitor C2, a MOS tube NMOS1, a MOS tube NMOS2, a first MOS tube series resistor and a second MOS tube series resistor, wherein the grid electrode of the first MOS tube series resistor is connected with reference voltage, the drain electrode of the second MOS tube series resistor is connected with the grid electrode of the MOS tube NMOS2, the source electrode of the second MOS tube series resistor is connected with the source electrode of the MOS tube NMOS2, and the grid electrode of the second MOS tube series resistor is connected with the reference voltage. According to the invention, the MOS transistor NMOS1 with the gate source short circuit and the MOS transistor NMOS2 are added to be used as common mode voltage to quickly establish a branch circuit, and the series resistance of the MOS transistor replaces a large resistance in the traditional structure, so that the area of a chip can be obviously reduced.

Description

Direct current offset cancelling circuit
Technical Field
The invention relates to the technical field of wireless communication and integrated circuit design, in particular to a direct current offset cancellation circuit.
Background
Currently, with the development of science and technology, various portable electronic products become indispensable tools in daily life. Receivers are important components of such products, and high performance receivers are one of the goals pursued by integrated circuit designers. The zero intermediate frequency receiver is widely used in wireless devices because of its great advantages in power consumption and integration. In zero-if receivers, the if signal is located near zero frequency, the mismatch introduced due to the mismatch will be amplified step by step together with the if signal. When the offset reaches a certain level, the link dc operating point will be shifted, and even the channel will be saturated, which results in the performance of the receiver being greatly reduced or the receiver not working normally, so the dc offset cancellation technique is more critical in the zero-if receiver.
Common dc offset cancellation methods are classified into analog dc offset cancellation methods and digital dc offset cancellation methods. The digital DC offset elimination method needs to design a complex digital algorithm and is not beneficial to improving the integration level. The commonly used analog direct current offset method is equivalent to a high-pass filter in amplitude-frequency response, and can eliminate direct current signals and a part of low-frequency signals to achieve the effect of eliminating direct current offset.
However, the existing solutions have the following drawbacks:
as shown in fig. 1, the conventional analog dc offset circuit needs a large resistor and capacitor to obtain a low high-pass corner, thereby reducing the low-frequency signal loss. Due to the existence of large resistance and large capacitance, the common-mode voltage has long establishing time, even reaches millisecond level, and directly influences the establishing speed of a receiver, and in addition, the large resistance can cause the area of a chip to be large.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a direct current offset cancellation circuit which can solve the technical problems of long establishment time and large chip area in the prior art.
The invention is realized by adopting the following technical scheme:
a direct current offset cancellation circuit comprises a resistor R1 to a resistor R7, an operational amplifier OPA1, an operational amplifier OPA2, a capacitor C1, a capacitor C2, a MOS transistor NMOS1, a MOS transistor NMOS2, a first MOS transistor series resistor and a second MOS transistor series resistor, wherein one end of the resistor R1 is connected with a signal input end VIP, one end of a resistor R2 is connected with a signal input end VIN, the other end of a resistor R1, one end of a resistor R3 and one end of a resistor R5 are connected with a non-inverting input end of an operational amplifier OPA1, the other end of a resistor R2, one end of a resistor R4 and one end of a resistor R4 are connected with an inverting input end of the operational amplifier OPA 4, the other end of the resistor R4 and one end of the capacitor C4 are connected with a non-inverting input end of the operational amplifier OPA 4, the other end of the resistor R4 and one end of the capacitor C4 are connected with an inverting output end of the MOS transistor NMOS 4, the other end of the capacitor C2, the grid of the MOS transistor NMOS2 and the drain of the MOS transistor NMOS2 are connected with the in-phase output end of the operational amplifier OPA2, the source of the MOS transistor NMOS1 and the other end of the resistor R3 are connected with the in-phase output end of the operational amplifier OPA1 to serve as a signal output end VOP, the source of the MOS transistor NMOS2 and the other end of the resistor R4 are connected with the inverted output end of the operational amplifier OPA1 to serve as a signal output end VON, the drain of the first MOS transistor series resistor is connected with the grid of the MOS transistor NMOS1, the source of the first MOS transistor series resistor is connected with the source of the MOS transistor NMOS1, the grid of the first MOS transistor series resistor is connected with a reference voltage, the drain of the second MOS transistor series resistor is connected with the grid of the MOS transistor NMOS2, the source of the second MOS transistor series resistor is connected with the source of the MOS transistor NMOS2, and the grid of the second MOS.
Further, first MOS pipe series resistance includes a plurality of MOS pipes, and a plurality of MOS pipes arrange in proper order, and the source electrode of adjacent MOS pipe is connected to the drain electrode of preceding MOS pipe, and the source electrode of first MOS pipe connects the source electrode of MOS pipe NMOS1, and the grid of MOS pipe NMOS1 is connected to the drain electrode of last MOS pipe, and the grid of a plurality of MOS pipes all connects reference voltage.
Further, the second MOS transistor series resistor comprises a plurality of MOS transistors, the plurality of MOS transistors are arranged in sequence, the drain electrode of the previous MOS transistor is connected with the source electrode of the adjacent MOS transistor, the source electrode of the first MOS transistor is connected with the source electrode of the NMOS2, the drain electrode of the last MOS transistor is connected with the gate electrode of the NMOS2, and the gate electrodes of the plurality of MOS transistors are all connected with the reference voltage.
Compared with the prior art, the invention has the beneficial effects that: .
According to the invention, the MOS transistor NMOS1 with the gate source short circuit and the MOS transistor NMOS2 are added to be used as common mode voltage to quickly establish a branch circuit, and the series resistance of the MOS transistor replaces a large resistance in the traditional structure, so that the area of a chip can be obviously reduced.
Drawings
FIG. 1 is a diagram of a prior art DC offset cancellation circuit;
FIG. 2 is a circuit diagram of a DC offset cancellation circuit according to the present invention;
FIG. 3 is a circuit diagram of the first MOS transistor series resistor or the second MOS transistor series resistor according to the present invention;
fig. 4 is a simulation diagram of the common mode voltage setup time of the dc offset cancellation circuit of the present invention and the dc offset cancellation circuit of the prior art.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and the detailed description, and it should be noted that any combination of the embodiments or technical features described below can be used to form a new embodiment without conflict.
As shown in fig. 2, the present invention provides a dc offset canceling circuit, which includes a resistor R1 to a resistor R7, an operational amplifier OPA1, an operational amplifier OPA2, a capacitor C1, a capacitor C2, a MOS transistor NMOS1, a MOS transistor NMOS2, a first MOS transistor series resistor, and a second MOS transistor series resistor, where the MOS transistor series resistor replaces a large resistor in a conventional structure, one end of the resistor R1 is connected to the signal input terminal VIP, one end of the resistor R2 is connected to the signal input terminal VIN, the other end of the resistor R1, one end of the resistor R3, and one end of the resistor R5 are connected to the non-inverting input terminal of the operational amplifier OPA1, the other end of the resistor R2, one end of the resistor R4, and one end of the resistor R6 are connected to the inverting input terminal of the operational amplifier OPA1, the other end of the resistor R5 and one end of the capacitor C1 are connected to the non-inverting input terminal of the operational amplifier OPA2, the other end of the resistor R6 and one end of the capacitor C, the other end of the capacitor C1, the grid of the MOS tube NMOS1 and the drain of the MOS tube NMOS1 are all connected with the inverting output end of the operational amplifier OPA2, the other end of the capacitor C2, the grid of the MOS transistor NMOS2 and the drain of the MOS transistor NMOS2 are both connected with the in-phase output end of the operational amplifier OPA2, the source of the MOS transistor NMOS1 and the other end of the resistor R3 are both connected with the in-phase output end of the operational amplifier OPA1 to serve as a signal output end VOP, the source of the MOS transistor NMOS2 and the other end of the resistor R4 are both connected with the inverted output end of the operational amplifier OPA1 to serve as a signal output end VON, the drain of the first MOS transistor series resistor is connected with the grid of the MOS transistor NMOS1, the source of the first MOS transistor series resistor is connected with the source of the MOS transistor NMOS1, the grid of the first MOS transistor series resistor is connected with a reference voltage, the drain of the second MOS transistor series resistor is connected with the grid of the MOS transistor NMOS2, the source of the second MOS transistor series resistor is connected with the source of the MOS transistor NMOS2, and the grid of the second MOS.
As shown in fig. 3, the first MOS transistor series circuit and the second MOS transistor series circuit of the present invention have the same actual structure, and each of the first MOS transistor series circuit and the second MOS transistor series circuit includes a plurality of MOS transistors, for example, the plurality of MOS transistors are arranged in sequence, the drain of the previous MOS transistor is connected to the source of the adjacent MOS transistor, the source of the first MOS transistor is connected to the source of the MOS transistor NMOS1, the drain of the last MOS transistor is connected to the gate of the MOS transistor NMOS1, and the gates of the plurality of MOS transistors are connected to the reference voltage. Taking the second MOS transistor series circuit as an example, the MOS transistors are sequentially arranged, the drain of the previous MOS transistor is connected to the source of the adjacent MOS transistor, the source of the first MOS transistor is connected to the source of the MOS transistor NMOS2, the drain of the last MOS transistor is connected to the gate of the MOS transistor NMOS2, and the gates of the MOS transistors are all connected to the reference voltage.
In the conventional circuit structure, referring to fig. 1, when the circuit works normally, the amplitude-frequency response is equivalent to a high-pass filter, so that a direct-current signal and a part of low-frequency signals can be filtered, and the effect of eliminating direct-current offset is achieved; the signal dc gain a (0) can be simplified as:
Figure BDA0002135178560000051
in the above formula, Av(0) Representing the open-loop DC gain, A, of the operational amplifier OPAt1vf(0) Represents the open-loop dc gain of the operational amplifier OPAt 2; rt3/Rt1Is the closed-loop direct current gain of a main signal link, and takes noise and linear factors into consideration in an actual circuit, Rt1Can be given a value ofCan take values of several kilo-ohms to tens of kilo-ohms, and Rt3Is a value of Rt1Several to tens of times. To simplify the analysis, consider the case where the main signal link gain is 1, i.e., Rt3Value of (A) and Rt1Equal, when the term before the denominator of equation (1) is about 0, equation (1) can be written as:
Figure BDA0002135178560000052
it can be seen that for greater DC offset cancellation capability (A (0) is small), R should be reducedt5And (4) taking values. The high pass knee point HP can be expressed as:
Figure BDA0002135178560000053
therefore, in order to reduce the low frequency loss of the main signal, it should be better to make HP as small as possible, and R is known from the previous analysist5Smaller, therefore R is requiredt7And Ct1The product is large; taking into account chip area, R, in actual circuit designt7Can be large, even up to several mega ohms, and can consume a large chip area. Compared with the traditional circuit, the MOS transistor NMOS1 and NMOS2 with the short-circuited gate and source are added as a common-mode voltage to quickly establish a branch circuit; the first MOS tube series resistor and the second MOS tube series resistor are used for replacing a large resistor (Rt 7 and Rt8 in fig. 1) of a traditional structure, so that the chip area is obviously reduced, and the specific principle is as follows:
when a link is electrified, the potentials of the two points A and B are quickly pulled up; due to the link misalignment (which may be tens or hundreds of millivolts), the two potentials VOP and VON are one higher and the other lower due to the action of the primary signal link op-amp; at the moment, the analog direct current offset can detect voltage values of VOP and VON, and feed current values back to input ends VIP and VIN, the feedback current is multiplied by resistors R1 and R2 to obtain regulated voltage which is added to the input ends VIN and VIP, and then output end voltages VOP and VON can be changed correspondingly; the steps are circulated until the difference value between the VOP and the VON is very small, and the establishment of the common mode voltage is completed; the conventional circuit structure has the disadvantages that the Rt7 and the Rt8 and the capacitors C1 and C2 are large, so that the whole establishing process is slow.
At the beginning of common mode voltage establishment, the A and B potentials are pulled up quickly, and if the VOP potential is higher and the VON potential is lower, the voltage of the VON is pulled up quickly to be close to the potential of a point B because NOMS1 and NMOS2 are equivalent to diodes according to the working principle of the diodes; and the voltage of the VOP will be pulled low synchronously due to the action of the main signal link OPA 1; after the common mode voltage is built up, the NMOS1 and the NMOS2 work in a cut-off area, which is equivalent to open circuit, because the difference between the grid-source voltages is close to 0, and no longer has an effect on the circuit.
In fig. 4, the solid line is the simulation time curve established by the common mode voltage of the present invention, and the dotted line is the simulation time curve of the conventional circuit structure. As can be seen from fig. 4, the common-mode voltage of the dc offset cancellation circuit provided by the present invention is established more rapidly, and for the same common-mode voltage (the common-mode voltage that enables the circuit to work normally), the establishment time of the common-mode voltage of the circuit provided by the present invention is about 38% faster than that of the conventional structure.
The above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are within the protection scope of the present invention.

Claims (3)

1. A direct current offset canceling circuit is characterized by comprising a resistor R1 to a resistor R7, an operational amplifier OPA1, an operational amplifier OPA2, a capacitor C1, a capacitor C2, a MOS transistor NMOS1, a MOS transistor NMOS2, a first MOS transistor series resistor and a second MOS transistor series resistor, wherein one end of the resistor R1 is connected with a signal input end VIP, one end of the resistor R2 is connected with a signal input end VIN, the other end of the resistor R1, one end of the resistor R3 and one end of the resistor R5 are connected with a non-inverting input end of an operational amplifier OPA1, the other end of the resistor R2, one end of the resistor R4 and one end of the resistor R4 are connected with an inverting input end of the operational amplifier OPA 4, the other end of the resistor R4 and one end of the capacitor C4 are connected with a non-inverting input end of the operational amplifier OPA 4, the other end of the resistor R4 and one end of the capacitor C4 are connected with an inverting input end of the operational amplifier OPA 4, the inverting gate of the MOS transistor NMOS 4 and the drain of the operational amplifier OPA 4, the other end of the capacitor C2, the grid of the MOS transistor NMOS2 and the drain of the MOS transistor NMOS2 are connected with the in-phase output end of the operational amplifier OPA2, the source of the MOS transistor NMOS1 and the other end of the resistor R3 are connected with the in-phase output end of the operational amplifier OPA1 to serve as a signal output end VOP, the source of the MOS transistor NMOS2 and the other end of the resistor R4 are connected with the inverted output end of the operational amplifier OPA1 to serve as a signal output end VON, the drain of the first MOS transistor series resistor is connected with the grid of the MOS transistor NMOS1, the source of the first MOS transistor series resistor is connected with the source of the MOS transistor NMOS1, the grid of the first MOS transistor series resistor is connected with a reference voltage, the drain of the second MOS transistor series resistor is connected with the grid of the MOS transistor NMOS2, the source of the second MOS transistor series resistor is connected with the source of the MOS transistor NMOS2, and the grid of the second MOS.
2. The DC offset canceling circuit of claim 1, wherein the first MOS transistor series resistor comprises a plurality of MOS transistors, the plurality of MOS transistors are arranged in sequence, the drain of the former MOS transistor is connected to the source of the adjacent MOS transistor, the source of the first MOS transistor is connected to the source of the NMOS1, the drain of the last MOS transistor is connected to the gate of the NMOS1, and the gates of the plurality of MOS transistors are connected to the reference voltage.
3. The DC offset canceling circuit of claim 1, wherein the second MOS transistor series resistor comprises a plurality of MOS transistors, the plurality of MOS transistors are arranged in sequence, the drain of the former MOS transistor is connected to the source of the adjacent MOS transistor, the source of the first MOS transistor is connected to the source of the NMOS2, the drain of the last MOS transistor is connected to the gate of the NMOS2, and the gates of the plurality of MOS transistors are connected to the reference voltage.
CN201910650910.7A 2019-07-18 2019-07-18 Direct current offset cancelling circuit Pending CN111103915A (en)

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CN201910650910.7A CN111103915A (en) 2019-07-18 2019-07-18 Direct current offset cancelling circuit
DE102020118913.3A DE102020118913A1 (en) 2019-07-18 2020-07-17 DC OFFSET ELIMINATION CIRCUIT

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