CN111095569A - Semiconductor device and method for manufacturing semiconductor device - Google Patents
Semiconductor device and method for manufacturing semiconductor device Download PDFInfo
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- CN111095569A CN111095569A CN201980004053.1A CN201980004053A CN111095569A CN 111095569 A CN111095569 A CN 111095569A CN 201980004053 A CN201980004053 A CN 201980004053A CN 111095569 A CN111095569 A CN 111095569A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 541
- 238000000034 method Methods 0.000 title claims description 64
- 238000004519 manufacturing process Methods 0.000 title claims description 50
- 230000007547 defect Effects 0.000 claims abstract description 336
- 239000000758 substrate Substances 0.000 claims abstract description 332
- 239000013078 crystal Substances 0.000 claims abstract description 328
- 239000000852 hydrogen donor Substances 0.000 claims abstract description 34
- 239000002019 doping agent Substances 0.000 claims abstract description 23
- 229910052739 hydrogen Inorganic materials 0.000 claims description 291
- 239000001257 hydrogen Substances 0.000 claims description 291
- 238000009826 distribution Methods 0.000 claims description 163
- -1 hydrogen ions Chemical class 0.000 claims description 160
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- 238000000137 annealing Methods 0.000 claims description 99
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- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 229910052734 helium Inorganic materials 0.000 description 61
- 239000001307 helium Substances 0.000 description 61
- 238000010586 diagram Methods 0.000 description 53
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- 238000009825 accumulation Methods 0.000 description 25
- 238000002513 implantation Methods 0.000 description 25
- 239000000969 carrier Substances 0.000 description 14
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
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- 239000010937 tungsten Substances 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
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Abstract
Provided is a semiconductor device provided with: a semiconductor substrate; a hydrogen donor provided inside the semiconductor substrate in a depth direction, having a doping concentration higher than a doping concentration of a dopant of the semiconductor substrate, having a peak of a doping concentration profile at a first position separated from the one main surface of the semiconductor substrate by a predetermined distance in the depth direction of the semiconductor substrate, and having a tail of the doping concentration profile having a doping concentration smaller than the peak at a position closer to the one main surface side than the first position; and a crystal defect region having a central peak of a crystal defect density at a position shallower than the first position in a depth direction of the semiconductor substrate.
Description
Technical Field
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
Background
In recent years, semiconductor devices such as Insulated Gate Bipolar Transistors (IGBTs) have been known (for example, see patent document 1).
Patent document 1: U.S. patent application publication No. 2005/0116249 specification
Disclosure of Invention
Technical problem
In a semiconductor device, it is desirable to control the carrier lifetime.
Technical scheme
In a first aspect of the present invention, a semiconductor device including a semiconductor substrate is provided. The semiconductor device may be provided with a hydrogen donor. The hydrogen donor may be provided inside the semiconductor substrate in the depth direction and have a doping concentration higher than that of the dopant of the semiconductor substrate. The hydrogen donor may have a peak of a doping concentration distribution at a first position separated by a predetermined distance in a depth direction of the semiconductor substrate from the one main surface of the semiconductor substrate. The hydrogen donor may have a tail of the doping concentration distribution having a doping concentration smaller than the peak at a position closer to the one principal surface side than the first position. The semiconductor device may include a crystal defect region having a central peak of a crystal defect density at a position closer to the one principal surface side than the first position in a depth direction of the semiconductor substrate.
The semiconductor substrate may have a drift region of the first conductivity type disposed in a manner to include the first location. The semiconductor substrate may have an anode region of the second conductivity type disposed between the drift region and one main surface of the semiconductor substrate.
The semiconductor substrate may have a buffer region of the first conductivity type having a higher doping concentration than the drift region between the drift region and the other main surface of the semiconductor substrate.
The doping concentration profile of the hydrogen donor may have donor peaks at a plurality of positions in the buffer region. The crystal defect region may have a central peak of a crystal defect density between a plurality of donor peaks of the hydrogen donor in a depth direction of the semiconductor substrate.
The doping concentration profile of the hydrogen donor may have donor peaks at a plurality of positions in the buffer region. The crystal defect region may have a central peak of the crystal defect density at a position closer to the other principal surface side of the semiconductor substrate than the plurality of donor peaks of hydrogen donors in the depth direction of the semiconductor substrate.
The crystal defect region may be provided from the central peak to one main surface in the depth direction of the semiconductor substrate.
Concentration profile of hydrogen donors doping concentration at first locationThe degree may be 1 × 1014(/cm3) Above and 1 × 1015(/cm3) The following.
The semiconductor device may include a transistor portion in which a collector region of the second conductivity type is provided in a region in contact with the other main surface of the semiconductor substrate. The semiconductor device may include a diode portion in which a cathode region of the first conductivity type having a higher doping concentration than that of the drift region is provided in a region in contact with the other main surface of the semiconductor substrate. The diode part may include a crystal defect region. The transistor portion may include a crystal defect region. The transistor portion may include a crystal defect region in a region in contact with the diode portion. The semiconductor device may include an edge termination structure portion disposed on the upper surface of the semiconductor substrate between the active portion and the outer peripheral end of the semiconductor substrate, the active portion being provided with a transistor portion and a diode portion. The edge termination structure portion may include a crystal defect region.
The distribution of the crystal defect density may have a tail from the central peak toward the one main surface of the semiconductor substrate. The crystal defect density of the anode region may be less than half of the crystal defect density at the central peak.
The crystal defect density of the anode region may be the same as the minimum value of the crystal defect density in the drift region.
In a second aspect of the present invention, a method for manufacturing a semiconductor device is provided. The manufacturing method may include a step of implanting hydrogen ions from one main surface of the semiconductor substrate in a depth direction of the semiconductor substrate. The manufacturing method may include annealing the semiconductor substrate at the first temperature. The annealing step can reduce crystal defects generated at the position of the maximum hydrogen concentration of the implantation of hydrogen ions. The annealing step may be performed such that a position where the defect density of the crystal defect formed by the implantation of the hydrogen ion becomes the maximum is formed on the one principal surface side of the position of the maximum hydrogen concentration.
The manufacturing method may include a step of implanting hydrogen ions in the depth direction of the semiconductor substrate from the other main surface of the semiconductor substrate before the step of implanting hydrogen ions in the depth direction of the semiconductor substrate from the one main surface of the semiconductor substrate. The manufacturing method may include, before the step of implanting hydrogen ions from one main surface of the semiconductor substrate in the depth direction of the semiconductor substrate, a step of annealing the semiconductor substrate implanted with hydrogen ions from the other main surface at a second temperature higher than the first temperature.
The step of implanting hydrogen ions from the other main surface of the semiconductor substrate in the depth direction of the semiconductor substrate may include: and implanting hydrogen ions a plurality of times so that the peak position of the concentration distribution of hydrogen ions in the depth direction of the semiconductor substrate is different.
The manufacturing method may include a step of forming the semiconductor substrate into a chip after the step of annealing at the first temperature. The method may further include a bonding step of bonding the semiconductor substrate formed into a chip to the circuit substrate at a third temperature. The third temperature may be lower than the first temperature.
In the step of implanting hydrogen ions, the hydrogen ions may be implanted at an acceleration energy at which a range from one main surface of the semiconductor substrate is 8 μm or more.
The acceleration energy in the step of implanting hydrogen ions may be 1.0MeV or more. The acceleration energy may be 1.5MeV or more. The acceleration energy in the step of implanting hydrogen ions may be 11.0MeV or less. The acceleration energy may be 5.0MeV or less. The acceleration energy may be 2.0MeV or less.
The dose of the hydrogen ions in the step of implanting the hydrogen ions may be 1.0 × 1012/cm2The above. The dose of the hydrogen ions in the step of implanting the hydrogen ions may be 1.0 × 1015/cm2The following.
It should be noted that the above summary of the invention does not list all necessary features of the invention. In addition, sub-combinations of these feature groups can also be inventions.
Drawings
Fig. 1A is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention.
Fig. 1B is a diagram showing an example of a cross section of the semiconductor device 100 according to the present embodiment.
Fig. 2 is a diagram showing a cross section of a semiconductor device 150 of a comparative example.
Fig. 3 shows respective profiles of net doping concentration (a), hydrogen concentration and helium concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E) and carrier concentration (F) along the a-a 'line of the semiconductor device 100 of the embodiment shown in fig. 1B and the z-z' line of the semiconductor device 150 of the comparative example.
Fig. 4 is a diagram showing another example of a cross section of the semiconductor device 100 of the present embodiment.
Fig. 5 is a diagram showing another example of a cross section of the semiconductor device 100 of the present embodiment.
Fig. 6 is a diagram showing another example of a cross section of the semiconductor device 100 of the present embodiment.
Fig. 7A shows respective profiles of net doping concentration (a), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along the C-C' line of the semiconductor device 100 of the embodiment shown in fig. 5.
Fig. 7B shows respective profiles of net doping concentration (a), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) in the case where the crystal defect region 19-2 on the lower surface 23 side is formed by implanting helium ions.
Fig. 7C shows another example of each profile of net doping concentration (a), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F).
Fig. 7D shows another example of each profile of net doping concentration (a), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F).
Fig. 8A is a diagram partially showing an example of the upper surface of the semiconductor device 200 of the present embodiment.
Fig. 8B is a diagram partially showing another example of the upper surface of the semiconductor device 200.
Fig. 8C is a diagram partially showing another example of the upper surface of the semiconductor device 200.
Fig. 8D is a diagram partially showing another example of the upper surface of the semiconductor device 200.
Fig. 9A is a view showing an example of a section d-d' of fig. 8A.
Fig. 9B is a view showing an example of a section d-d' of fig. 8B.
Fig. 9C is a view showing an example of a section d-d' of fig. 8C.
Fig. 10A is a diagram illustrating an example of an outline of a method for manufacturing a semiconductor device according to the present embodiment.
Fig. 10B is a diagram illustrating another example of a method for manufacturing a semiconductor device.
Fig. 11 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present embodiment.
Fig. 12 is a graph showing respective distributions of the hydrogen concentration (B), the crystal defect density (C), and the carrier concentration (F) along the line h-h' of fig. 11.
Fig. 13 is a diagram illustrating another example of the method for manufacturing a semiconductor device according to the present embodiment.
Fig. 14 is a diagram illustrating another example of the method for manufacturing the semiconductor device according to the present embodiment.
Fig. 15 is a diagram illustrating an example of an outline of a method for manufacturing a semiconductor device according to the present embodiment.
Fig. 16 is a diagram illustrating a step of forming the crystal defect region 19 and the high concentration region 26 by implanting hydrogen ions (protons in this example) from the upper surface 21 side of the semiconductor substrate 10.
Fig. 17 is a diagram illustrating a step of forming the crystal defect region 19 and the high concentration region 26 by implanting hydrogen ions (protons in this example) from the lower surface 23 side of the semiconductor substrate 10.
Fig. 18 shows the profile of the net doping concentration (a), the hydrogen concentration (B), the crystal defect density (C), the carrier lifetime (D), the carrier mobility (E), and the carrier concentration (F) in the depth direction in the semiconductor device 100 shown in fig. 17.
Description of the symbols
10: semiconductor substrate, 11: well region, 12: emitter region, 14: anode region, 15: contact zone, 16: accumulation region, 17: base region, 18: drift region, 19: crystal defect region, 19-1: crystal defect region, 19-2: crystal defect region, 20: buffer, 21: upper surface, 22: collector region, 23: lower surface, 24: collector electrode, 26: high concentration region, 27: lower surface side electrode, 29: extension portion, 30: dummy groove portion, 31: connection portion, 32: dummy insulating film, 34: dummy conductive portion, 38: interlayer insulating film, 39: extension portion, 40: gate trench portion, 41: connection portion, 42: gate insulating film, 44: gate conductive portion, 48: gate runner, 49: contact hole, 50: gate metal layer, 52: emitter electrode, 53: upper surface-side electrode, 54: contact hole, 56: contact hole, 58: barrier metal, 60 first mesa portion, 62: second table surface portion, 64: third mesa portion, 70: transistor portion, 74: upper surface side lifetime control region, 78: lower surface side lifetime control region, 80: diode unit, 81: extension zone, 82: cathode region, 90: boundary portion, 92: edge termination structure portion, 100: semiconductor device, 110: mask, 116: gate pad, 118: emitter pad, 120: active part, 140: outer peripheral end, 150: semiconductor device, 200: semiconductor device, 274: upper surface side lifetime control region
Detailed Description
The present invention will be described below with reference to embodiments of the invention, but the following embodiments do not limit the invention according to claims. Note that all combinations of the features described in the embodiments are not necessarily essential to the technical means of the invention.
In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "up", and the other side is referred to as "down". One of the two main surfaces of the substrate, layer, or other member is referred to as an upper surface, and the other surface is referred to as a lower surface. The directions of "up" and "down" are not limited to the direction of gravity or the mounting direction to a substrate or the like when actually mounting a semiconductor device.
In this specification, technical matters will be described using orthogonal coordinate axes of X, Y and Z axes. In this specification, a plane parallel to the upper surface of the semiconductor substrate is referred to as an XY plane, and a depth direction perpendicular to the upper surface of the semiconductor substrate is referred to as a Z axis.
In each of the embodiments, the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, the layer, the region, and the like in the embodiments are opposite in polarity. In the present specification, the term "P + -type" (or "N + -type") means a higher doping concentration than the P-type (or "N-type"), and the term "P-type" (or "N-type") means a lower doping concentration than the P-type (or "N-type").
In the present specification, the doping concentration refers to the concentration of an impurity which is subjected to donor or acceptor conversion. In this specification, a difference in concentration between a donor and an acceptor (i.e., net doping concentration) is sometimes referred to as a doping concentration. In addition, the peak of the doping concentration distribution of the doped region may be the doping concentration of the doped region.
Fig. 1A is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or the like, a diamond semiconductor substrate, or an oxide semiconductor substrate such as gallium oxide. The semiconductor substrate 10 of this example is a silicon substrate. In fig. 1A, an end portion of the outer periphery of the semiconductor substrate 10 is referred to as an outer peripheral end 140.
The semiconductor device 100 includes an active portion 120 and an edge termination structure portion 92. The active portion 120 is a region in which a main current flows between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in an on state. That is, the region is a region in which current flows in the semiconductor substrate 10 in the depth direction from the upper surface to the lower surface or from the lower surface to the upper surface of the semiconductor substrate 10. An interlayer insulating film, an emitter electrode, and the like, which will be described later, are provided above the active portion 120, but are omitted in fig. 1A. The region covered by the emitter electrode may be used as the active portion 120.
At least one of transistor portion 70 and diode portion 80 is provided in active portion 120. Transistor portion 70 includes a transistor such as an Insulated Gate Bipolar Transistor (IGBT). The diode section 80 includes a diode such as a freewheeling diode (FWD). In the example of fig. 1A, transistor portion 70 and diode portion 80 are arranged in a predetermined arrangement direction (Y-axis direction). The transistor portions 70 and the diode portions 80 may be alternately arranged in contact with each other in the array direction. In the active portion 120, transistor portions 70 may be provided at both ends in the Y-axis direction. In other examples, diode portion 80 may be provided in active portion 120 without providing transistor portion 70.
Each diode portion 80 is provided with an N + -type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In fig. 1A, a diode portion 80 shown by a solid line is a region where a cathode region 82 is provided on the lower surface 23 of the semiconductor substrate 10. In the semiconductor device 100 of this example, the collector region 22 is provided in a region other than the cathode region 82 in a region in contact with the lower surface of the semiconductor substrate 10.
The diode portion 80 is a region obtained by projecting the cathode region 82 in the Z-axis direction. The transistor portion 70 is a region in which the collector region 22 is provided on the lower surface of the semiconductor substrate 10, and unit structures including emitter regions and gate groove portions, which will be described later, are periodically provided on the upper surface of the semiconductor substrate 10. An extension region 81 (in fig. 1A, a portion shown by a broken line extending the diode portion 80) in which a region obtained by projecting the cathode region 82 extends to an end of the active portion 120 or the gate runner 48 in the X-axis direction may be included in the diode portion 80.
The semiconductor device 100 of this example further includes a gate metal layer 50 and a gate runner 48. The semiconductor device 100 may have respective pads such as a gate pad 116 and an emitter pad 118. Gate pad 116 is electrically connected to gate metal layer 50 and gate runner 48. Emitter pad 118 is electrically connected to emitter electrode 52.
The gate metal layer 50 may be provided so as to surround the active portion 120 when the semiconductor substrate 10 is viewed in plan view. Gate pad 116 and emitter pad 118 may be disposed within a region surrounded by gate metal layer 50. The gate metal layer 50 may be formed of a metal material such as aluminum or aluminum-silicon alloy. The gate metal layer 50 is insulated from the semiconductor substrate 10 by an interlayer insulating film. Further, the gate metal layer 50 is provided separately from the emitter electrode. The gate metal layer 50 transfers a gate voltage applied to the gate pad 116 to the transistor part 70.
The gate runner 48 connects the gate metal layer 50 with the transistor portion 70. The gate runner 48 may be formed of a semiconductor material such as polycrystalline silicon doped with impurities. A portion of gate runner 48 may be disposed over active portion 120. The gate runner 48 shown in fig. 1A is provided so as to cross the active portion 120 in the X-axis direction. This can suppress a decrease or delay in the gate voltage even inside the active portion 120 separated from the gate metal layer 50. A part of the gate runner 48 may be disposed along the gate metal layer 50 so as to surround the active portion 120. The gate runner 48 may be connected to the transistor portion 70 at an end of the active portion 120.
The edge termination structure portion 92 is disposed between the active portion 120 and the outer peripheral end 140 of the semiconductor substrate 10 on the upper surface of the semiconductor substrate 10. In this example, the gate metal layer 50 is disposed between the edge termination structure portion 92 and the active portion 120. The edge termination structure portion 92 may be arranged in a ring shape on the upper surface of the semiconductor substrate 10 so as to surround the active portion 120. The edge termination structure 92 of this example is disposed along the outer peripheral edge 140 of the semiconductor substrate 10. The edge termination structure portion 92 alleviates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 92 has a structure such as a guard ring, a field plate, a surface field reduction, and a combination thereof.
Fig. 1B is a view showing an example of a YZ cross section of a part of the semiconductor device 100. In this example, a YZ cross section of a part of the diode unit 80 illustrated in fig. 1A is shown. As described above, in the semiconductor device 100, the diode portion 80 shown in fig. 1B may be provided in the active portion 120, and a chip in which the transistor portion 70 is not provided may be provided, or the diode portion 80 and the transistor portion 70 may be provided in the active portion 120. In any chip, the diode portion 80 may have the same configuration as the semiconductor device 100 described with reference to fig. 1B to 7D. In addition, diode unit 80 may be provided with dummy groove 30 in the same manner as semiconductor device 100 described with reference to fig. 9A to 9C, 16, and 17. In fig. 1B of the present example, the dummy groove portion 30 is omitted. Note that, the dummy groove portion 30 may not be provided in the diode portion 80. The semiconductor device 100 of this example includes a semiconductor substrate 10, an upper surface-side electrode 53, and a lower surface-side electrode 27. The upper surface side electrode 53 is provided on the upper surface 21 of the semiconductor substrate 10. The lower surface side electrode 27 is provided on the lower surface 23 of the semiconductor substrate 10. The upper surface side electrode 53 and the lower surface side electrode 27 are formed of a conductive material such as a metal. The upper surface 21 and the lower surface 23 are main surfaces of the semiconductor substrate 10.
The semiconductor substrate 10 has a drift region 18 of a first conductivity type. The drift region 18 in this example is N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without providing other doped regions. The dopant of the semiconductor substrate 10 may be an N-type donor such as phosphorus or antimony. As an example, the dopant of the semiconductor substrate 10 of this example is phosphorus. The ratio of the donor concentration of the dopant to the chemical concentration is referred to as the donor ratio. The donor ratio of the dopant in the semiconductor substrate 10 may be 90% or more and 100% or less of the chemical concentration of the dopant. The donor ratio of phosphorus or antimony in this example may be 95% or more and 100% or less.
The doping concentration of the drift region 18 may coincide with the doping concentration of the semiconductor substrate 10. In the case where the doping concentration of the drift region 18 coincides with the doping concentration of the semiconductor substrate 10, the dopant of the drift region 18 may coincide with the dopant of the semiconductor substrate 10. Alternatively, the doping concentration of the drift region 18 may be more than twice as high as the dopant of the semiconductor substrate 10. In this case, the dopant of the drift region 18 may be different from the dopant of the semiconductor substrate 10. For example, the dopant of the drift region 18 is hydrogen, and the dopant of the semiconductor substrate 10 is phosphorus or antimony.
The single crystal wafer of the semiconductor substrate 10 may be manufactured from an ingot (ingot) formed by a czochralski method (CZ method), a magnetron czochralski method (MCZ method), a floating zone melting method (FZ method), or the like. As an example, the single crystal wafer of the semiconductor substrate 10 is a wafer manufactured by a magnetron czochralski method (MCZ method).
An anode region 14 of the first conductivity type is disposed above the drift region 18. The anode region 14 in this example is, for example, P-type. The anode region 14 may be disposed between the drift region 18 and the upper surface 21 in the Z-axis direction. In this example, the upper surface of the anode region 14 is disposed in contact with the upper surface 21. In this example, the anode region 14 is provided in contact with the drift region 18.
A cathode region 82 of the first conductivity type having a higher doping concentration than the drift region 18 is provided below the drift region 18. For example, the cathode region 82 of this example is N + type. The cathode region 82 is disposed in contact with the lower surface 23. In this example, the cathode region 82 is provided in contact with the drift region 18. The cathode region 82 can be formed by implanting ions of phosphorus or the like from the lower surface 23 of the semiconductor substrate 10 and annealing.
The semiconductor device 100 of this example is provided with a high concentration region 26 inside the semiconductor substrate 10. The high concentration region 26 may be formed by implanting hydrogen ions from the upper surface 21. The hydrogen ion may be proton, deuterium, tritium. In this case protons. The concentration distribution of hydrogen in the depth direction of the semiconductor substrate 10 has a peak of the concentration distribution at a first position Ps separated by a predetermined distance Dps in the depth direction of the semiconductor substrate 10 from the one main surface (upper surface 21 in this example) of the semiconductor substrate 10. In fig. 1B, the peak of the concentration distribution of hydrogen at the first position Ps is shown with an "x" symbol (mark). The first position Ps may be arranged closer to the upper surface 21 than 1/2 of the thickness T of the semiconductor substrate.
The concentration distribution of hydrogen in the depth direction of the semiconductor substrate 10 has a tail of a concentration distribution having a concentration smaller than the peak at a position closer to the upper surface 21 side than the first position Ps. Note that the concentration distribution of hydrogen and the tailing of the concentration distribution will be described later.
The high concentration region 26 is disposed in a range including the first position Ps. The high concentration region 26 includes hydrogen donors. The high concentration region 26 may include VOH composite defects, in which hydrogen (H), oxygen (O), and vacancies (V) are combined into one or more clusters, as hydrogen donors. Sometimes VOH recombination defects become N-type donors. In this specification, the VOH recombination defect is sometimes simply referred to as a hydrogen donor. Further, the chemical concentration of hydrogen is sometimes referred to as hydrogen concentration. As an example, the high concentration region 26 of this example is N + type.
The oxygen of the semiconductor substrate 10 may be intentionallyThe introduction may be unintentional. The oxygen in the semiconductor substrate 10 may be introduced from an oxide film formed on the main surface of the semiconductor substrate 10. The oxygen concentration of the semiconductor substrate 10 may be 1 × 1016(/cm3) Above and 1 × 1018(/cm3) Hereinafter, the value may be 5 × 1016(/cm3) Above and 5 × 1017(/cm3) The following.
The hydrogen donor is formed after hydrogen ions are implanted from the main surface (upper surface 21 in this example) of the semiconductor substrate 10. The donor rate of the hydrogen donor can be increased by thermally annealing the semiconductor substrate 10 after the implantation of the hydrogen ions. By implanting hydrogen ions, hydrogen donors are formed in a region where hydrogen is present at the maximum concentration (i.e., a region corresponding to the range Rp of hydrogen ions). Further, by annealing the semiconductor substrate 10, the formation of VOH recombination defects is promoted, and the concentration of hydrogen donors is increased. Thereby, the high concentration region 26 having a higher doping concentration than the drift region 18 is formed. The high concentration region 26 may be formed so as to be sandwiched by the drift region 18 in the Z-axis direction (depth direction perpendicular to the main surface of the semiconductor substrate 10). Note that, a method of forming the high concentration region 26 will be described later.
The first position Ps may be a peak position in the Z-axis direction of the doping concentration of the high concentration region 26. In the present specification, the peak of the hydrogen donor concentration at the first position Ps is sometimes referred to as a donor peak. The doping concentration at the first position Ps of the high concentration region 26 may be 1 × 1013(/cm3) Above and 1 × 1017(/cm3) Hereinafter, it may be 1 × 1014(/cm3) Above and 1 × 1016(/cm3) Hereinafter, the value may be 1 × 1014(/cm3) Above and 1 × 1015(/cm3) The following.
A crystal defect region 19-1 is provided above the high concentration region 26. The crystal defect region 19-1 may be a region containing crystal defects formed by implanting hydrogen ions from the upper surface 21. In fig. 1B, the range in the Z-axis direction where the crystal defect region 19-1 is provided is shown by a double arrow.
The crystal defect region 19-1 has a peak of the crystal defect density at a position Ks separated by a distance Dks in the Z-axis direction from the upper surface 21. Crystal defect region 19-1 may be provided to upper surface 21 from position Ks. The crystal defect may be a defect serving as a recombination center (center) of carriers, and may be mainly vacancy (V) or double vacancy (VV). The crystal defect density may refer to the density of recombination centers. In general, a dopant such as a donor or an acceptor is also included in a crystal defect, but in the present specification, a crystal defect is defined as a defect that mainly acts on recombination of carriers as a recombination center.
In this example, the peak in the Z-axis direction of the crystal defect density in the crystal defect region 19-1 is referred to as a central peak. The position of the central peak in the Z-axis direction is set as the position Ks. The position Ks is set shallower than the peak position of the doping concentration of the high concentration region 26, i.e., the first position Ps, with respect to the upper surface 21. That is, distance Dks is less than distance Dps. In fig. 1B, the central peak of the crystal defect density at the position Ks is shown with a "+" sign (mark).
In the semiconductor device 100 of this example, the carrier lifetime is controlled by utilizing crystal defects generated by hydrogen ion implantation. In this example, the position in the Z-axis direction of the region where the lifetime is controlled (lifetime is decreased) is set in a different region from the position in the Z-axis direction of the position (range, Rp) where the hydrogen ion stops and the maximum hydrogen concentration value where hydrogen is the most exists. In this example, the region in which the lifetime is reduced is a shallow region on the upper surface 21 side with respect to the position of the maximum value of the hydrogen concentration, that is, a region through which hydrogen ions pass. While the hydrogen ions pass through the semiconductor substrate 10, the hydrogen ions collide with atoms of the semiconductor (silicon in this example) to attenuate energy, and damage the crystal, thereby forming a large number of crystal defects in a region (passage region) shallower than the range Rp of the hydrogen ions. Thereby, a crystal defect region is formed in the hydrogen ion passage region, and the lifetime is controlled.
On the other hand, since a large amount of hydrogen is present near the position where the hydrogen concentration is the maximum, the hydrogen ends up dangling bonds existing in vacancies or double vacancies. As a result, the density of recombination centers becomes extremely low in the vicinity of the position where the hydrogen concentration becomes maximum as compared with the pass region, and it can be said that there is substantially no contribution to carrier recombination as compared with the pass region.
The central peak of the crystal defect density in the crystal defect region 19-1 can be made the upper surface side lifetime controlled region 74. The crystal defect density of the upper surface side lifetime controlled region 74 is high compared with other regions of the semiconductor substrate 10. The range of formation of the lifetime control region for this example will be described later.
Fig. 2 is a diagram showing a cross section of a semiconductor device 150 of a comparative example. The semiconductor device 150 of the comparative example differs from the semiconductor device 100 shown in fig. 1B in that, in the semiconductor device 100 of the present example shown in fig. 1B, the upper-surface-side lifetime controlled region 274 is provided instead of the upper-surface-side lifetime controlled region 74 and the high-concentration region 26 is not provided. The upper surface side lifetime controlled region 274 is formed by injecting helium from the upper surface 21.
In the semiconductor device 150 of the comparative example, the upper surface side lifetime control region 274 is provided at the position Ks' in the Z-axis direction. The distance Dks 'in the Z-axis direction from the upper surface 21 to the position Ks' is smaller than the distance Dks in the semiconductor device 100 shown in fig. 1B.
If helium ions and hydrogen ions are implanted from the upper surface 21 of the semiconductor substrate 10 with the same acceleration energy, the hydrogen ions are implanted from the upper surface 21 to a position deeper in the depth direction of the semiconductor substrate 10 than the helium ions. Thus, distance Dks is greater than distance Dks'.
In the semiconductor device 150 of the comparative example, helium implanted into the semiconductor substrate 10 hardly donates more than hydrogen even when annealing is performed. Therefore, in the semiconductor device 150 of the comparative example, the high concentration region 26 is not provided. Further, unlike the semiconductor device 100 of the present example, in the semiconductor device 150 of the comparative example, since there is no hydrogen (or the hydrogen concentration is very low) terminating the dangling bonds existing in the vacancies or double vacancies, the peak position at which the crystal defect density as the recombination center becomes the maximum overlaps with the peak position at which the helium concentration of helium exists at the maximum in the semiconductor substrate 10. Therefore, the position where recombination of carriers is most frequently performed is the peak position of the helium concentration.
Fig. 3 shows respective profiles of net doping concentration (a), hydrogen concentration and helium concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E) and carrier concentration (F) along the a-a 'line of the semiconductor device 100 of the embodiment shown in fig. 1B and the z-z' line of the semiconductor device 150 of the comparative example. As described above, the upper surface side lifetime control region 74 is formed by implanting hydrogen ions into the semiconductor substrate 10 in the semiconductor device 100, and the upper surface side lifetime control region 274 is formed by implanting helium ions into the semiconductor substrate 10 in the semiconductor device 150. Here, the net doping concentration (a) shows only an example of the semiconductor device 100. In fig. 3, each distribution diagram in the semiconductor device 100 is shown by a solid line, and each distribution diagram in the semiconductor device 150 is shown by a broken line.
The vertical axes of the profiles (a), (B), (C), (D), and (F) are shown on a logarithmic (log) scale, and the vertical axis of the profile (E) is shown on a linear (linear) scale. In fig. 3, in the distribution diagram displayed on a logarithmic scale on the vertical axis, the value on the vertical axis at the point intersecting the horizontal axis is not 0 but a predetermined value equal to or greater than 0. The horizontal axis in each profile is shown in linear scale. The horizontal axis of each distribution in fig. 3 shows the depth from the upper surface 21 of the semiconductor substrate 10.
Profile (a) shows the net doping concentration profile (i.e., the profile of the difference between the donor concentration and the acceptor concentration) of the electrically activated donors and acceptors. As shown in fig. 1B, the net doping concentration has a peak (donor peak) at position Ps. In this example, a region including the position Ps and having a net doping concentration higher than that of the drift region 18 is set as the high concentration region 26. The high concentration region 26 may be a region having a net doping concentration greater than half the net doping concentration at location Ps. The peak concentration of the net doping concentration at the position Ps of the high concentration region 26 is referred to as Np.
In the distribution diagram (A), the doping concentration is set to be higher than the doping concentration N of the semiconductor substrate 100The high N-type region is N + -type. In this example, the doping concentration and the doping concentration N of the drift region 18 disposed at a position deeper than the high concentration region 260And (5) the consistency is achieved. The hydrogen ions implanted from the upper surface 21 of the semiconductor substrate 10 pass through the drift region 18 disposed between the anode region 14 and the high concentration region 26. The doping concentration of the drift region 18 can be controlled by the residual hydrogenMainly becomes lower than the doping concentration N of the semiconductor substrate 100High. The average value of the doping concentration of the drift region 18 may be the doping concentration N of the semiconductor substrate 100Less than three times.
Between the anode region 14 and the drift region 18, the N-type accumulation region 16 may be provided at a higher concentration than the drift region 18. The accumulation region 16 is a portion where the dopant of the donor is accumulated at a higher concentration than the drift region 18. More than two accumulation regions 16 may be provided in the depth direction. More than two accumulation regions 16 may have more than two peaks of doping concentration. Two adjacent peaks may be N-type. More than two accumulation zones 16 may also be in the shape of a kink.
Profile (B) shows the chemical concentration of implanted hydrogen or helium. The hydrogen concentration is shown in the semiconductor device 100, and the helium concentration is shown in the semiconductor device 150. For example, the chemical concentration of atoms can be measured by Secondary Ion Mass Spectrometry (SIMS). The concentrations of helium and hydrogen are distributions obtained by diffusion of implanted helium ions and hydrogen ions by annealing. The degree of diffusion can be controlled according to the annealing time, annealing temperature, and the like. The hydrogen concentration has a peak at position Ps. The helium concentration has a peak at position Dks'.
The hydrogen concentration is a chemical concentration of hydrogen, and a peak concentration Hp, which is called Hp. hydrogen concentration at a position Ps of a peak having the highest hydrogen concentration, is higher than a peak concentration Np of net doping concentration at the position Ps, and if the donor rate of hydrogen donors is α, Hp is α Np, and α may be 0.001 to 0.5.
As described above, the concentration distribution of hydrogen has the tail S from the position Ps of the peak toward the one main surface (the upper surface 21 in this example). The tail S is a concentration distribution that changes more gradually when comparing the concentration distribution of hydrogen in a region shallower than the peak position Ps with the concentration distribution of hydrogen in a region deeper than the peak position Ps. That is, the concentration distribution of hydrogen streaks toward the main surface implanted with hydrogen ions. The smear S may or may not reach the upper surface 21. As shown in the distribution diagram (a), the average doping concentration of the drift region 18 on the shallower side than the high concentration region 26 may be compared with the average doping concentration of the drift region 18 on the deeper side than the high concentration region 26, and it may be determined that the tail S of the hydrogen concentration distribution is present on the higher side than the average doping concentration.
The distribution chart (C) shows the crystal defect density after annealing is performed under predetermined conditions after hydrogen ions or helium ions are implanted into the semiconductor substrate 10. In the semiconductor device 150 implanted with helium ions, the distribution of the crystal defect density and the distribution of the helium concentration have the same shape. For example, the position Dks 'of the peak of helium concentration coincides with the position Ks' of the peak of crystal defect density.
The net doping concentration of the high concentration region 26 is set to be equal to the doping concentration N of the semiconductor substrate 10 in the region on the lower surface 23 side of the position Ps0The substantially coincident position is set as a position Z0. At a specific position Z0In the region further toward the lower surface 23 side, the crystal defect density may be a sufficiently small value Nr0. Crystal defect density is sufficiently small value of Nr0The method comprises the following steps: crystal defect density has a low carrier lifetime of not less than0The value of (a). For example, the concentration of vacancies or vacancies is Nr0At a temperature of 300K, Nr0May be 1 × 1012atoms/cm3Or less than 1X 1012atoms/cm3May be 1X 1011atoms/cm3Hereinafter, the number of the particles may be 1 × 1010atoms/cm3The following. At the position J of the pn junction of the anode region 14 with the drift region 18 or the accumulation region 160The crystal defect density can be compared with Nr0High.
The density of crystal defects such as vacancies and double vacancies generated by the implantation of helium ions becomes highest near the position Dks' where helium ions are most implanted. As described above, in the semiconductor device 150, since hydrogen is substantially not present in the substrate, crystal defects are not substantially reduced even if annealing is performed. Therefore, the distribution of the crystal defect density before and after annealing is maintained.
In contrast, in the semiconductor device 100 into which hydrogen ions are implanted, since crystal defects are terminated by hydrogen, the distribution of the crystal defect density and the distribution of the hydrogen concentration have different shapes. For example, the position Ps of the peak of the hydrogen concentration does not coincide with the position Ks of the peak of the crystal defect density. The position Ks of the peak of the crystal defect density in this example is located on the upper surface 21 side of the semiconductor substrate 10 with respect to the peak position Ps of the hydrogen concentration. The crystal defect density may be monotonically decreased in a region on the upper surface 21 side than the position Ks. The crystal defect density may be monotonically decreased steeply than the upper surface 21 side in a region on the lower surface 23 side than the position Ks.
In the vicinity of the peak position Ps of the hydrogen concentration, a large amount of hydrogen terminates dangling bonds such as vacancies and double vacancies. Therefore, the crystal defect density in the vicinity of the peak position Ps of the hydrogen concentration is very small compared with the crystal defect density at the peak position Ks of the crystal defect density. In the present specification, the width of a distribution indicating a concentration greater than 1% of the peak concentration (Hp) is referred to as 1% full width or FW 1% M. The vicinity of the peak position Ps may refer to a region within a range of 1% of the full width centered on the peak position Ps. The position Ks of the peak of the crystal defect density may be set at a position shallower than the range of 1% full width centered on the peak position Ps.
However, the distance D between the peak position Ks of the crystal defect density and the peak position Ps of the hydrogen concentration is determined according to the distance by which hydrogen diffuses in the semiconductor substrate 10 by annealing. The distance D may be 40 μm or less, 20 μm or less, or 10 μm or less. The distance D may be 1 μm or more, 3 μm or more, or 5 μm or more. The distance D may be above 1% full width of the hydrogen concentration or greater than 1% full width of the hydrogen concentration. The distance D may be above 1% full width of the net doping concentration at the location Ps or greater than 1% full width of the net doping concentration at the location Ps. In this case, the 1% full width of the net doping concentration is the width of the peak at 0.01 Np. The range of values of the distance D may be a combination of the above-described upper limit value and lower limit value. As an example, the crystal defect density can be observed by measuring the density distribution of vacancies and double vacancies by positron annihilation.
The distribution diagram (D) shows a carrier lifetime distribution after annealing is performed under predetermined conditions after hydrogen ions or helium ions are implanted into the semiconductor substrate 10. In the semiconductor device 150 implanted with helium ions, the carrier lifetime distribution is in a shape in which the vertical axis of the crystal defect density distribution is inverted. For example, the position at which the carrier lifetime becomes the minimum value coincides with the central peak position Ks' of the crystal defect density.
Similarly, in the semiconductor device 100 into which hydrogen ions are implanted, the carrier lifetime distribution is inverted with respect to the vertical axis of the crystal defect density distribution. For example, the position at which the carrier lifetime becomes the minimum value coincides with the central peak position Ks of the crystal defect density. In the region in the range of FW 1% M centered on the peak position Ps of the hydrogen concentration, the carrier lifetime of the semiconductor device 100 can be the maximum value τ0. Maximum value τ0The lifetime of carriers in the drift region 18 on the lower surface 23 side of the peak position Ps of the hydrogen concentration may be set.
At a specific position Z0In the region further on the lower surface 23 side, the carrier lifetime may be a sufficiently large value τ0. The carrier lifetime is a sufficiently large value τ0Can mean that: the carrier lifetime is obtained without intentionally introducing a lifetime controller or a defect mainly composed of a vacancy or a double vacancy into the semiconductor substrate 10. At a temperature of 300K, tau0The concentration may be 10. mu.s or more, or may be 30. mu.s or more. As an example, τ0Is 10. mu.s. At the position J of the pn junction of the anode region 14 with the drift region 18 or the accumulation region 160The carrier lifetime may be less than τ0。
The distribution chart (E) shows the distribution of the mobility of carriers after annealing is performed under predetermined conditions after hydrogen ions or helium ions are implanted into the semiconductor substrate 10. At a specific position Z0In the region further on the lower surface 23 side, the mobility of carriers may be the mobility μ in the case of an ideal crystal structure0. As an example, the mobility μ0In the case of silicon at a temperature of 300K, the electron is 1360cm2/(Vs), holes are 495cm2/(Vs). At the position J of the pn junction of the anode region 14 with the drift region 18 or the accumulation region 160The mobility of the carriers may be less than μ0。
The distribution chart (F) shows the distribution of carrier concentration after annealing is performed under predetermined conditions after hydrogen ions or helium ions are implanted into the semiconductor substrate 10. For example, the carrier concentration can be measured by a diffusion resistance measurement method (SR measurement method).
In the SR measurement method, the diffusion resistance is converted into resistivity, and the carrier concentration is calculated from the resistivity. When the resistivity is rho (omega cm), the mobility is mu (cm)2V · s), the basic charge is q (C), and the carrier concentration is N (/ cm)3) And N is 1/(μ q ρ).
In the SR measurement method, a value at which the crystal state of the semiconductor substrate 10 is an ideal state is used as the mobility of carriers. However, if the semiconductor substrate 10 is damaged by ion implantation, the crystal state of the semiconductor substrate 10 is broken to be disordered, and the mobility is actually lowered. The reduced mobility should be originally used as the mobility in SR measurement, but it is difficult to measure the value of the reduced mobility. Therefore, in the SR measurement in the example of the profile (F), an ideal value is used as the mobility. Therefore, the denominator of the formula of the carrier concentration becomes large, and the mobility is lowered. That is, in the distribution chart (F), the measured carrier concentration is decreased as a whole in the region through which the hydrogen ions pass (the region from the lower end of the anode region 14 of the semiconductor substrate 10 to the high concentration region 26). However, in the high concentration region 26 near the range Rp of the hydrogen ions, the hydrogen concentration is high, and therefore the disordered state is relaxed by the hydrogen termination effect, and the mobility is close to the value of the crystalline state. Further, hydrogen donors are also formed. Therefore, the carrier concentration becomes higher than the carrier concentration N of the semiconductor substrate 100High.
In the semiconductor device 150 into which helium ions are implanted, the carrier concentration is reduced in a narrow region near the peak position Ks' of the helium concentration (i.e., near the peak position of the crystal defect density). When helium ions are implanted into the semiconductor substrate 10 to form a crystal defect, the peak position of the helium concentration, the position indicating that the carrier concentration is extremely small, the peak position of the crystal defect density, and the position indicating that the carrier lifetime is extremely small all coincide at the position Ks'.
When hydrogen ions are implanted into the semiconductor substrate 10 to form crystal defects, the peak position Ps of the hydrogen concentration may often coincide with the peak position of the crystal defect density before annealing. However, if annealing is performed after hydrogen ion implantation, hydrogen diffuses from the peak position of the hydrogen concentration toward the upper surface 21 of the semiconductor substrate 10, and dangling bonds contained in vacancies and double vacancies are terminated by hydrogen. Therefore, the crystal defect density after annealing decreases before and after the peak position Ps of the hydrogen concentration. Therefore, the carrier lifetime in the vicinity of the position Ps where the hydrogen concentration becomes a peak increases, and becomes substantially τ0。
The lifetime control region (in this example, the upper surface side lifetime control region 74) may be: in the region where the hydrogen concentration is shifted from the peak toward the main surface side (upper surface 21 side in this example) showing the tail as shown in the distribution (B), the carrier concentration becomes higher than the carrier concentration N of the semiconductor substrate 10 as shown in the distribution (F)0A low region. Further, as shown in the distribution chart (C), the density distribution of vacancies and vacancies may be measured, and the region of the region closer to the upper surface 21 side than the peak position Ps, in which the density of vacancies and vacancies is higher than that of the region closer to the lower surface 23 side, may be used as the lifetime control region. Alternatively, a region of the vacancy or double-vacancy density distribution having a width (FW 1% M) of two positions of 1% of the maximum value with the position Ks of the maximum value therebetween may be used as the lifetime control region. Further, the position Ks at which the crystal defect density becomes a peak as described above can also be simply taken as the lifetime control region.
Fig. 4 is a diagram showing another example of a cross section of the semiconductor device 100 of the present embodiment. The semiconductor device 100 of this example is different from the semiconductor device 100 shown in fig. 1B in that hydrogen ions are implanted from the lower surface 23 side, the high concentration region 26 is provided on the lower surface 23 side, and the crystal defect region 19-2 is provided on the lower surface 23 side. The lower surface 23 side is a region closer to the lower surface 23 side than the center of the semiconductor substrate 10 in the Z-axis direction.
In the semiconductor device 100 of this example, the concentration distribution of hydrogen in the depth direction of the semiconductor substrate 10 has a peak of the concentration distribution at a first position Pb that is separated by a predetermined distance Dpb in the depth direction of the semiconductor substrate 10 from the one main surface (in this example, the lower surface 23) of the semiconductor substrate 10. In fig. 4, the peak of the concentration distribution of hydrogen at the first position Pb is shown with an "x" symbol (mark). The first position Pb may be arranged closer to the lower surface 23 than 1/2 of the thickness T of the semiconductor substrate.
The concentration distribution of hydrogen in the depth direction of the semiconductor substrate 10 has a tail S of a concentration distribution having a concentration smaller than the peak in a region closer to the lower surface 23 than the first position Pb (see fig. 3). The first position Pb may be disposed below the first position Ps in the Z-axis direction.
In the semiconductor device 100 of this example, the semiconductor substrate 10 may have the high concentration region 26 having a higher doping concentration than the drift region 18 between the drift region 18 and the lower surface 23 of the semiconductor substrate 10. The high concentration region 26 is disposed in such a manner as to include the first position Pb. The high concentration region 26 of this example may be a region formed by annealing the semiconductor substrate 10 implanted with hydrogen ions from the lower surface 23. After the hydrogen ions are implanted, the semiconductor substrate 10 is annealed to make hydrogen donor, thereby forming a high concentration region 26 having a higher doping concentration than the drift region 18.
In the semiconductor device 100 of this example, the high concentration region 26 is provided so as to be sandwiched by the drift region 18 in the Z-axis direction. Since the high concentration region 26 has a higher doping concentration than the drift region 18, the depletion layer diffused from the lower surface side of the anode region 14 can be prevented from reaching the cathode region 82.
A crystal defect region 19-2 is provided below the high concentration region 26. The crystal defect region 19-2 may be a region containing a crystal defect formed by implanting hydrogen ions from the lower surface 23. In fig. 4, the range in the Z-axis direction where the crystal defect region 19-2 is provided is shown by a double arrow.
Crystal defect region 19-2 has a central peak of the crystal defect density at a position Kb separated by distance Dkb in the Z-axis direction from lower surface 23. Crystal defect region 19-2 may be provided from position Kb to lower surface 23.
In this example, the peak in the Z-axis direction of the crystal defect density in the crystal defect region 19-2 is referred to as a central peak. The position of the central peak in the Z-axis direction is defined as position Kb. As described in fig. 3, when a crystal defect is formed by implanting hydrogen ions, the peak position of the crystal defect density is located on the main surface (lower surface 23 in this example) side where the hydrogen ions are implanted, compared with the peak position of the hydrogen concentration. Therefore, the position Kb is set shallower than the first position Pb, which is the peak position of the doping concentration of the high concentration region 26, with reference to the lower surface 23. That is, distance Dkb is less than distance Dpb. In fig. 4, the central peak of the crystal defect density at the position Kb is shown with a "+" sign (mark).
In the semiconductor device 100 of this example, the carrier lifetime is controlled by utilizing crystal defects generated by hydrogen ion implantation. In the semiconductor device 100 of this example, the central peak of the crystal defect density in the crystal defect region 19-2 can be set as the lower surface side lifetime controlled region 78. The crystal defect density of the lower surface side lifetime controlled region 78 is higher than that of other regions of the semiconductor substrate 10.
Fig. 5 is a diagram showing another example of a cross section of the semiconductor device 100 of the present embodiment. In the semiconductor device 100 of this example, in addition to the configuration of the semiconductor device 100 shown in fig. 1B, a buffer region 20 of the first conductivity type having a higher doping concentration than the drift region 18 is provided below the drift region 18. As an example, the buffer 20 of this example is N + type. The buffer region 20 may be disposed between the drift region 18 and the lower surface 23 in the Z-axis direction. In this example, the buffer region 20 is provided in contact with the drift region 18. The buffer region 20 can function as a field stop region for preventing a depletion layer diffused from the lower surface side of the anode region 14 from reaching the cathode region 82.
In the semiconductor device 100 of this example, the concentration distribution of hydrogen has peaks of concentration distribution at a plurality of positions in the buffer 20. That is, from the upper surface side toward the lower surface side of the buffer 20, there are peaks of the concentration distribution at four positions of the position Pb4, the position Pb3, the position Pb2, and the position Pb 1. In fig. 5, peaks of the concentration distribution of hydrogen at a plurality of positions in the Z-axis direction are shown with an "x" symbol (mark). The buffer 20 of this example may be a region formed by annealing the semiconductor substrate 10 after implanting hydrogen ions from the lower surface 23 into the position Pb4, the position Pb3, the position Pb2, and the position Pb1 of the semiconductor substrate 10.
The semiconductor device 100 of this example is provided with a plurality of crystal defect regions 19. Crystal defect region 19-1 is provided on the upper surface 21 side of semiconductor substrate 10, and crystal defect region 19-2 is provided on the lower surface 23 side.
The crystal defect region 19-1 is a region containing crystal defects formed by implanting hydrogen ions from the upper surface 21. Crystal defect region 19-1 is the same as crystal defect region 19-1 shown in fig. 1B. The crystal defect region 19-2 is a region containing a crystal defect formed by implanting hydrogen ions or helium ions from the lower surface 23. The crystal defect region 19-2 is not necessarily configured, and may be provided as needed. The crystal defect region 19-2 may be disposed inside the buffer region 20. In fig. 5, the range in the Z-axis direction where the crystal defect region 19-1 is provided is shown by a double arrow.
The crystal defect region 19-2 may have a central peak of the crystal defect density between a plurality of peaks of the hydrogen concentration in the depth direction of the semiconductor substrate 10. That is, the crystal defect region 19-2 may have a central peak of the crystal defect density in the Z-axis direction at any one of the peak positions of the hydrogen concentration of the buffer region 20, that is, between the positions Pb1 and Pb2, between the positions Pb2 and Pb3, and between the positions Pb3 and Pb 4. Further, the entire crystal defect region 19-2 may be disposed between any peak positions of the hydrogen concentration. The crystal defect region 19-2 of this example shows an example having a central peak of the crystal defect density at the position Kb between the position Pb1 and the position Pb 2. In fig. 5, the central peak of the crystal defect density between the position Pb1 and the position Pb2 is shown with a "+" symbol (mark).
In the semiconductor device 100 of this example, the carrier lifetime is controlled by utilizing crystal defects generated by hydrogen ion implantation. In the semiconductor device 100 of this example, the central peak of the crystal defect density in the crystal defect region 19-2 is set as the lower surface side lifetime controlled region 78.
The crystal defect region 19-2 of this example contains crystal defects formed when hydrogen ions or helium ions are implanted from the lower surface 23 to the position Pb 2. As described in fig. 3, when a crystal defect is formed by implanting hydrogen ions, the peak position of the crystal defect density is arranged on the main surface side where the hydrogen ions are implanted, compared with the peak position of the hydrogen concentration.
Fig. 6 is a diagram showing another example of a cross section of the semiconductor device 100 of the present embodiment. The semiconductor device 100 shown in fig. 6 is different from the semiconductor device 100 shown in fig. 5 in that the lower surface side lifetime controlled region 78 is provided at a position lower than the position Pb1 in the Z-axis direction. The crystal defect region 19-2 may be provided up to the lower surface 23 of the semiconductor substrate 10.
The position of the lower-surface-side lifetime controlled region 78 in the Z-axis direction can be adjusted by adjusting the order of the implantation step (step) of hydrogen ions at a plurality of positions in the Z-axis direction and the annealing step of the semiconductor substrate 10 into which the hydrogen ions have been implanted. The hydrogen ion implantation step and the annealing step will be described later.
Fig. 7A shows respective profiles of net doping concentration (a), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along the C-C' line of the semiconductor device 100 of the embodiment shown in fig. 5. The vertical axis and horizontal axis of each profile are the same as the corresponding profiles shown in fig. 3.
Profile (a) shows the net doping concentration profile of the electrically activated donors and acceptors. As shown in fig. 5, the buffer 20 has peaks (donor peaks) of doping concentration at a plurality of positions Pb4, Pb3, Pb2, Pb 1. In addition, the high concentration region 26 has a peak of the doping concentration (donor peak) at the position Ps. The doping concentration between the respective donor peaks may be greater than the doping concentration N of the semiconductor substrate 100High, it may be the same concentration as that. In this example, the doping concentration of at least a part of the region between the position Ps and the position Pb4 is the doping concentration N0. The dopant of the semiconductor substrate 10 may be phosphorus or the like. Doping concentration N0May be N as illustrated in distribution (A) of FIG. 30。
In the profile (a), an N-type region having a higher doping concentration than the drift region 18 is an N + -type region. At least a part of the region of the drift region 18 between the position Ps and the position Pb4 may have a doping concentration lower than that of the and positionPs is the doping concentration of the drift region 18 on the side closer to the upper surface 21 than Ps. The drift region 18 on the upper surface 21 side is passed with hydrogen ions implanted from the upper surface 21 of the semiconductor substrate 10. Therefore, the doping concentration of the drift region 18 can become higher than the doping concentration N of the semiconductor substrate 10 due to the remaining hydrogen donors0High. The average value of the doping concentration of the drift region 18 on the upper surface 21 side may be the doping concentration N of the semiconductor substrate 100Less than 3 times of the total weight of the composition.
At the positions Pb4, Pb3, Pb2, Pb1, hydrogen ions are implanted from the lower surface 23 of the semiconductor substrate 10. Therefore, the doping concentration of the region on the lower surface 23 side of the position Pb4 as a whole can be made higher than the doping concentration N of the semiconductor substrate 100High. That is, the doping concentration (donor concentration in this example) of the drift region 18 in the region sandwiched between the peaks of two hydrogen donors (the peaks of hydrogen donors at the position Ps and the position Pb4 in this example) in the depth direction is the lowest. The doping concentration of the region sandwiched between the peaks of the two hydrogen donors (donor concentration in this example) may be the doping concentration N of the semiconductor substrate 100The doping concentration profile may be substantially flat. Also, due to the two hydrogen donors, the doping concentration from the position Ps toward the upper surface 21 side and the doping concentration from the position Pb4 toward the lower surface 23 side can become larger than the doping concentration N of the semiconductor substrate 100High. The cathode region 82 in this example is formed by implanting phosphorus and diffusing the phosphorus.
The profile (B) shows the chemical concentration of the injected hydrogen. Each peak of the hydrogen concentration has a tail on the main surface side where the hydrogen ions are implanted. In this example, the peak of the hydrogen concentration at the position Ps has a tail S on the upper surface 21 side. That is, the hydrogen concentration distribution of this example gently decreases monotonously from the first position Ps to the upper surface 21 on the upper surface 21 side. The tail S may be disposed throughout the drift region 18 and the anode region 14.
The hydrogen concentration distribution of this example has a tail in which the change in concentration distribution is steeper than the tail S in the region from the first position Ps toward the lower surface 23 side. That is, the hydrogen distribution is asymmetric in the region closer to the upper surface 21 than the first position Ps and in the region closer to the lower surface 23 than the first position Ps.
Further, the peak of the hydrogen concentration of each of the positions Pb4, Pb3, Pb2, Pb1 has a tail S' on the lower surface 23 side. The peak of the hydrogen concentration of each of the positions Pb4, Pb3, Pb2, Pb1 has a tail whose variation in concentration distribution is steeper than the tail S' on the upper surface 21 side. That is, the peaks of the hydrogen concentrations at the positions Pb4, Pb3, Pb2, and Pb1 show asymmetric distributions in the region on the upper surface 21 side of the position Pb1 and the region on the lower surface 23 side of the position Pb 1.
The hydrogen concentration may be the minimum value between the position closest to the lower surface 23 (position Ps in this example) of the positions where the hydrogen ions are implanted from the upper surface 21 side and the position closest to the upper surface 21 (position Pb4 in this example) of the positions where the hydrogen ions are implanted from the lower surface 23 side. The position where the sum of the distribution of diffusion of hydrogen injected at the position Ps and the distribution of diffusion of hydrogen injected at the position Pb4 is the minimum value of the hydrogen concentration. Alternatively, the position where the hydrogen concentration becomes the minimum may be sandwiched between the peaks of two hydrogen donors (in this example, the position Ps and the position Pb4) and located at the doping concentration N where the doping concentration shows the semiconductor substrate 100In the region of the substantially flat doping concentration profile.
The distribution chart (C) shows the crystal defect density after annealing is performed under predetermined conditions after hydrogen ions are implanted into the semiconductor substrate 10. The distribution of the crystal defect density in the region closer to the upper surface 21 than the position Ps is the same as the distribution of the crystal defect density of the semiconductor device 100 shown in the distribution chart (C) of fig. 3. Crystal defect concentration Nr0May be Nr illustrated in the distribution diagram (C) of fig. 30. At a position Ks on the upper surface 21 side than the position Ps, the crystal defect density has a peak. The crystal defect density may be monotonically decreased in a region on the upper surface 21 side than the position Ks. The crystal defect density may monotonically decrease in a steeper manner in a region on the lower surface 23 side than the position Ks than in a region on the upper surface 21 side.
The crystal defect density in the vicinity of the peak position Ps of the hydrogen concentration is very small compared with the crystal defect density at the peak position Ks of the crystal defect density. The position Ks of the peak of the crystal defect density may be set at a shallower position than the range of 1% full width centered on the peak position Ps. The distance D between the peak position Ks of the crystal defect density and the peak position Ps of the hydrogen concentration may be 40nm or less, or 20nm or less. The distance D may be 5 μm or more and 10 μm or less. The distance D may be above 1% full width of the hydrogen concentration or greater than 1% full width of the hydrogen concentration. The distance D may be more than 1% full width of the net doping concentration at the location Ps or greater than 1% full width of the net doping concentration at the location Ps. In this case, the 1% full width of the net doping concentration is the width of the peak of 0.01 Np.
In this example, a peak of the crystal defect density is arranged at a position Kb between the position Pb2 and the position Pb 1. The peak of the crystal defect density at the position Kb mainly includes crystal defects formed when hydrogen ions are implanted from the lower surface 23 to the position Pb 2. In this example, in the region on the lower surface 23 side of the position Pb4, a peak of the crystal defect density is not provided except for the position Kb.
For example, hydrogen ions are implanted into the positions Pb4, Pb3, Pb1, and the semiconductor substrate 10 is annealed under the first condition. Thereby, peaks of the hydrogen concentration distribution are formed at the positions Pb4, Pb3, Pb 1. Thereafter, hydrogen ions are implanted into the position Ps and the position Pb2, and the semiconductor substrate 10 is annealed under the second condition. The second condition has an annealing temperature lower than the annealing temperature of the first condition. The crystal defects generated by implanting hydrogen ions into the positions Pb4, Pb3, Pb1 are substantially capped by the higher temperature annealing. In contrast, the crystal defects generated by implanting hydrogen ions into the position Ps and the position Pb2 end up the crystal defects in the vicinity of the position Ps and the position Pb2 by annealing at a lower temperature. Since a large amount of hydrogen is also present in the vicinity of the position Pb1, a proportion of crystal defects generated by implanting hydrogen ions into the position Pb2 is also capped in the vicinity of the position Pb1 is large. Therefore, the crystal defect density has a peak between the position Pb2 and the position Pb 1.
In this example, the peak of the hydrogen concentration at the position Ps is not provided with another peak of the hydrogen concentration on the side where the hydrogen ions are implanted (the upper surface 21 side in this example). On the other hand, the peak of the hydrogen concentration at Pb2 is provided with another peak of the hydrogen concentration (position Pb1) on the side where the hydrogen ions are implanted (the lower surface 23 side in this example). The integrated value of the crystal defect density on the upper surface 21 side than the position Ps may be larger than the integrated value of the crystal defect density on the lower surface 23 side than the position Pb 2.
The distribution diagram (D) shows a carrier lifetime distribution after annealing is performed under predetermined conditions after hydrogen ions are implanted into the semiconductor substrate 10. The carrier lifetime distribution is a shape obtained by inverting the longitudinal axis of the crystal defect density distribution. Carrier lifetime τ0May be τ illustrated in profile (D) of FIG. 30. For example, the position at which the carrier lifetime becomes the minimum value coincides with the central peak position Ks of the crystal defect density. Further, the position where the carrier lifetime becomes the minimum value coincides with the central peak position Kb of the crystal defect density. In the same manner as the distribution diagram (D) of fig. 3, in the region in the range of FW 1% M centered on the peak positions Ps, Pb4, Pb3, Pb2, and Pb1 of the hydrogen concentration, the carrier lifetime of the semiconductor device 100 may become the maximum value τ0。
The distribution chart (E) shows the distribution of the mobility of carriers after annealing is performed under predetermined conditions after hydrogen ions are implanted into the semiconductor substrate 10. Mobility of carrier mu0May be μ illustrated in the distribution chart (E) of fig. 30. For example, the position at which the mobility of the carrier becomes the minimum value coincides with the central peak position Ks of the crystal defect density. Further, the position where the mobility of the carrier becomes a minimum value coincides with the central peak position Kb of the crystal defect density. As with the distribution diagram (E) of fig. 3, in the region in the range of FW 1% M centered on the peak positions Ps, Pb4, Pb3, Pb2, and Pb1 of the hydrogen concentration, the mobility of carriers of the semiconductor device 100 may be the maximum value μ0。
The distribution chart (F) shows the distribution of the carrier concentration after annealing is performed under predetermined conditions after hydrogen ions are implanted into the semiconductor substrate 10. Similarly to the distribution diagram (F) in fig. 3, the measured carrier concentration decreases in the whole region through which hydrogen ions pass (the region from the lower end of the anode region 14 of the semiconductor substrate 10 to the vicinity of the position Ps). However, the region on the lower surface 23 side of the position Pb4 has a high hydrogen concentration as a whole, and thereforeCarrier concentration to substrate concentration N0High.
In the semiconductor device 100 of this example, the crystal defect density after annealing is reduced before and after the peak position Ps of the hydrogen concentration. Therefore, the carrier lifetime in the vicinity of the position Ps where the hydrogen concentration becomes a peak increases, and becomes substantially τ0。
Fig. 7B shows respective profiles of net doping concentration (a), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) in the case where the crystal defect region 19-2 on the lower surface 23 side is formed by implanting helium ions. The same as the example of fig. 7A except that the crystal defect region 19-2 on the lower surface 23 side is formed by implanting helium ions. The net doping concentration (a) and carrier concentration (F) profiles are the same as for the example of fig. 7A.
The distribution chart (B) shows the distribution of the chemical hydrogen concentration and helium concentration. The distribution of the hydrogen concentration is the same as that in fig. 7A. However, in this example, helium is distributed inside the buffer zone 20. In this example, the peak of the helium concentration is located in the region closer to the lower surface 23 than the position Pb 1.
The peak of helium concentration may be located between adjacent peaks of hydrogen concentration. That is, the peak of helium concentration may be located between Pb4 and Pb3, between Pb3 and Pb2, or between Pb2 and Pb 1. As an example, the peak of the helium concentration indicated by the broken line in the distribution chart (B) is located between Pb2 and Pb 1. Helium may be introduced in only one of a solid line distribution having a peak in a region closer to the lower surface 23 than Pb1 and a broken line distribution having a peak between Pb2 and Pb1, or in both distributions.
The distribution chart (C) shows the crystal defect density after annealing is performed under predetermined conditions after implanting hydrogen ions and helium ions into the semiconductor substrate 10. The crystal defect density distribution in the crystal defect region 19-1 formed by implanting hydrogen ions is the same as that of the crystal defect region 19-1 in the distribution diagram (C) of fig. 7A. Further, the crystal defect region 19-2a shown by a broken line in the profile (C) is a crystal defect region in the case where helium is implanted at a position shown by a solid line in the profile (B). The crystal defect region 19-2B is a crystal defect region in the case where helium is implanted at a position shown by a broken line in the profile (B). Note that, in the distribution diagrams (D) and (E), the distribution corresponding to the crystal defect region 19-a is also shown by a solid line, and the distribution corresponding to the crystal defect region 19-b is also shown by a broken line. The crystal defect density distribution of the crystal defect regions 19-2a and 19-2b formed by implanting helium ions has the same shape as the distribution of helium concentration. For example, the peak position of the crystal defect density coincides with the peak position of the helium concentration.
The distribution diagram (D) shows a carrier lifetime distribution after annealing is performed under predetermined conditions after hydrogen ions and helium ions are implanted into the semiconductor substrate 10. The carrier lifetime distribution is a shape obtained by inverting the longitudinal axis of the crystal defect density distribution.
The distribution chart (E) shows the distribution of the mobility of carriers after annealing is performed under predetermined conditions after hydrogen ions and helium ions are implanted into the semiconductor substrate 10.
In the semiconductor substrate 10, hydrogen is present in a large amount in the buffer region 20 and in a region closer to the lower surface 23 than the buffer region 20. Therefore, the dangling bonds are easily terminated, and it is sometimes difficult to form the crystal defect region 19. On the other hand, by forming the crystal defect region 19-2 by implanting helium ions having a larger mass than hydrogen ions, crystal defects such as vacancies and double vacancies are easily formed. Thus, even if the crystal defects are capped by annealing, crystal defects can remain at a certain density in the buffer 20 and the region closer to the lower surface 23 than the buffer 20. By providing the crystal defect region 19 in the buffer region 20 or the like, it is possible to control the tail current with high accuracy during the switching termination such as turning off or reverse recovery of the semiconductor device 100.
Fig. 7C shows another example of each profile of net doping concentration (a), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F). The vertical axis and horizontal axis of each profile are the same as the corresponding profiles shown in fig. 3. In this example, the crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) in anode region 14 (base region 17 forming a channel in transistor portion 70 described later) and crystal defect region 19-1 are different from those in the examples of fig. 7A and 7B. The respective distributions at other positions are the same as the example of any one of fig. 7A and 7B.
In this example, each distribution of the crystal defect density (C), the carrier lifetime (D), the carrier mobility (E), and the carrier concentration (F) has a peak in the crystal defect region 19-1. The peak of the crystal defect density distribution has a tail SV1 in a region on the upper surface 21 side than the central peak position Ks, and has a tail SV2 steeper than the tail SV1 in a region on the lower surface 23 side than the central peak position Ks. The peak of the carrier lifetime distribution has a tail S τ 1 in a region on the upper surface 21 side than the central peak position Ks, and has a tail S τ 2 steeper than the tail S τ 1 in a region on the lower surface 23 side than the central peak position Ks. The peak of the carrier mobility distribution has a tail S μ 1 in a region on the upper surface 21 side than the central peak position Ks, and has a tail S μ 2 steeper than the tail S μ 1 in a region on the lower surface 23 side than the central peak position Ks. The peak of the carrier concentration distribution has a tail SN1 in a region on the upper surface 21 side than the central peak position Ks, and has a tail SN2 steeper than the tail SN1 in a region on the lower surface 23 side than the central peak position Ks.
Each smear may be a portion from the peak of the peak to the same level as a predetermined reference value in each distribution. The reference value in the crystal defect density may use the minimum value Nr in the drift region 180The reference value in the carrier lifetime may use the maximum τ in the drift region0The reference value in the carrier mobility may use the maximum value μ in the drift region 180The reference value in the carrier concentration may use the minimum value N from the peak position Ps of the hydrogen concentration to the buffer region 200. In the present specification, the term "same" may include a case with an error of 10% or less.
None of the tails SV1, S τ 1, S μ 1, and SN1 in this example reaches the anode region 14 (base region 17 in the transistor portion 70). That is, the crystal defect density, carrier lifetime, carrier mobility and carrier concentration of the anode region 14 and the base region 17 are set to the reference value Nr described above0、τ0、μ0、N0The same is true. Thereby, the formation of crystals can be reducedThe effect of defects on the anode region 14 and the base region 17. In particular, variation in gate threshold can be suppressed. The gate threshold is determined by the location of the peak concentration of the base region 17. If the crystal defect density ratio Nr is at the peak position of the base region 170If the threshold value is high, the interface state and the like affecting the gate threshold value increase, and the gate threshold value may change. Nr is the crystal defect density at the peak position of the base region 170Thus, the influence on the gate threshold can be suppressed to a minimum. Note that, for example, by adjusting the implantation position of hydrogen ions and the annealing conditions after the hydrogen ion implantation, it is possible to control each smear so as not to reach the anode region 14 and the base region 17.
Fig. 7D shows another example of each profile of net doping concentration (a), hydrogen concentration (B), crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F). The vertical axis and horizontal axis of each profile are the same as the corresponding profiles shown in fig. 3. In this example, the crystal defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) in anode region 14 (base region 17 in transistor portion 70) and crystal defect region 19-1 are different from the example of fig. 7C. The distributions at other positions are the same as in the example of fig. 7C.
In this example, at least one of the tails SV1, S τ 1, S μ 1, and SN1 reaches anode region 14 or base region 17. However, the crystal defect density, carrier lifetime, carrier mobility, and carrier concentration in the anode region 14 and the base region 17 are sufficiently close to the above-described reference value Nr0、τ0、μ0、N0。
In this example, the crystal defect density, carrier lifetime, carrier mobility, and carrier concentration at the central peak position Ks are set to Nrp, τ p, μ p, Np. Note that the crystal defect density, carrier lifetime, carrier mobility, and carrier concentration in the anode region 14 or the base region 17 are Nrb, τ b, μ b, and Nb. The crystal defect density Nrb, carrier lifetime τ b, carrier mobility μ b, and carrier concentration Nb may use values at the PN junction position of the N-type region such as the anode region 14 or the base region 17 and the drift region 18. Note that, as the carrier concentration Nb, the maximum value of the carrier concentration in the N-type region in contact with the PN junction can be used.
The crystal defect density Nrb, the carrier lifetime τ b, the carrier mobility μ b, and the carrier concentration Nb may be equal to or less than half of the crystal defect density Nrp, the carrier lifetime τ p, the carrier mobility μ p, and the carrier concentration Np at the central peak position Ks, 1/4 or less, 1/10 or less, or 1/100 or less. This can reduce the influence on anode region 14 and base region 17 due to the formation of crystal defects.
Fig. 8A is a diagram partially showing an example of the upper surface of the semiconductor device 200 of the present embodiment. Semiconductor device 200 of the present example is a semiconductor chip including transistor portion 70 and diode portion 80 provided adjacent to transistor portion 70. The upper surface of the semiconductor device 200 may be the same as the upper surface of the semiconductor device 100 shown in fig. 1A. Transistor portion 70 includes a transistor such as an IGBT. Boundary portion 90 is a region adjacent to diode portion 80 in transistor portion 70. The Diode portion 80 includes a Diode such as FWD (Free Wheel Diode) on the upper surface of the semiconductor substrate 10. In fig. 8A, the chip upper surface at the periphery of the chip end is shown, and other regions are omitted.
Further, although the active region of the semiconductor substrate 10 in the semiconductor device 200 is illustrated in fig. 8A, the semiconductor device 200 may have an edge termination structure portion in a manner of surrounding the active region. The active region is a region through which a current flows when the semiconductor device 200 is controlled to be in an on state. The edge termination structure portion alleviates electric field concentration on the upper surface 21 side of the semiconductor substrate 10. The edge termination structure portion has, for example, a guard ring, a field plate, a reduced surface field, and a structure obtained by combining these.
The semiconductor device 200 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 17, and a contact region 15, which are provided inside a semiconductor substrate 10 and exposed on the upper surface of the semiconductor substrate 10. The semiconductor device 200 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the upper surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.
An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 50, and the upper surface 21 of the semiconductor substrate 10, but is omitted in fig. 8A. In the interlayer insulating film of this example, contact hole 56, contact hole 49, and contact hole 54 are provided so as to penetrate the interlayer insulating film.
Further, emitter electrode 52 is connected to the dummy conductive portion in dummy groove portion 30 through contact hole 56. A connection portion 25 made of a conductive material such as impurity-doped polycrystalline silicon may be provided between the emitter electrode 52 and the dummy conductive portion. An insulating film such as an oxide film is provided between the connection portion 25 and the upper surface 21 of the semiconductor substrate 10.
The gate runner 48 of this example is formed from below the contact hole 49 to the tip end of the gate groove 40. An insulating film such as an oxide film is formed between the gate runner 48 and the upper surface 21 of the semiconductor substrate 10.
At the tip end of the gate groove 40, the gate conductive portion is exposed on the upper surface 21 of the semiconductor substrate 10. The gate trench portion 40 is in contact with the gate runner 48 through the exposed portion of the gate conductive portion.
The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a partial region of the emitter electrode 52 may be formed of aluminum or an aluminum-silicon alloy.
At least a portion of the region of the gate metal layer 50 may be formed of aluminum or an aluminum-silicon alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium, a titanium compound, or the like, under a region formed of aluminum or the like. Further, emitter electrode 52 and gate metal layer 50 may have a plug formed of tungsten or the like in the contact hole.
The one or more gate trench portions 40 and the one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (Y-axis direction in this example). The gate trench portion 40 of this example may have two extending portions 39 extending in an extending direction (in this example, the X-axis direction) parallel to the upper surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connecting portion 41 connecting the two extending portions 39. At least a part of the connection portion 41 is preferably formed in a curved shape. By connecting the end portions of the two extending portions 39 of the gate trench portion 40, the electric field concentration at the end portions of the extending portions 39 can be alleviated. In this specification, each extension portion 39 of the gate trench portion 40 may be treated as one gate trench portion 40. The gate runner 48 may be connected to the gate conductive portion at the connection portion 41 of the gate trench portion 40.
The dummy trench portion 30 of this example may have a U-shape on the upper surface 21 of the semiconductor substrate 10, similarly to the gate trench portion 40. That is, the dummy groove portion 30 of this example may have two extending portions 29 extending in the extending direction and a connecting portion 31 connecting the two extending portions 29.
The mesa portion is provided in a plane parallel to the upper surface 21 of the semiconductor substrate 10 so as to be adjacent to each groove portion in the Y-axis direction. The mesa portion is a portion of the semiconductor substrate sandwiched between two adjacent trench portions. The mesa portion may be a portion extending from the upper surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. The region sandwiched between the extending portions of the adjacent two groove portions may be made the mesa portion.
In the transistor portion 70, the first mesa portion 60 is provided so as to be adjacent to each trench portion. In a boundary portion 90 of the transistor portion 70, which is a boundary with the diode portion 80, a second mesa portion 62 is provided in a region sandwiched between adjacent dummy trench portions 30. In diode portion 80, third mesa portion 64 is provided in a region sandwiched between adjacent dummy groove portions 30.
As an example, the base region 17 of the second conductivity type is provided so as to be exposed on the upper surface 21 of the semiconductor substrate 10 at both ends of the first mesa portion 60, the second mesa portion 62, and the third mesa portion 64 in the X-axis direction. The base region 17 of this example is P-type, as an example. Fig. 8A shows only one end portion of the base region 17 in the X-axis direction.
The emitter region 12 is provided on the upper surface of the first mesa portion 60 so as to be in contact with the gate trench portion 40. The emitter region 12 may be provided from one to the other of two trench portions extending in the X-axis direction across the first mesa portion 60 in the Y-axis direction. The emitter region 12 is also disposed below the contact hole 54.
The emitter region 12 may be in contact with the dummy trench portion 30, or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is provided in contact with the dummy trench portion 30. The emitter region 12 of this example is of the first conductivity type. As an example, the emitter region 12 of this example is of the N + type.
A contact region 15 of the second conductivity type having a higher doping concentration than the base region 17 is provided on the upper surface of the first mesa portion 60. As an example, the contact region 15 of this example is P + type. In the first mesa portion 60, the emitter regions 12 and the contact regions 15 may be alternately arranged in the extending direction of the gate trench portion 40. The contact region 15 may be provided from one to the other of two groove portions extending in the X-axis direction across the first mesa portion 60 in the Y-axis direction. The contact region 15 is also disposed below the contact hole 54.
The contact region 15 may or may not be in contact with the gate trench portion 40. The contact region 15 may or may not be in contact with the dummy groove portion 30. In this example, the contact region 15 is provided so as to be in contact with the dummy trench portion 30 and the gate trench portion 40.
A contact region 15 is provided on the upper surface of the second mesa portion 62. The area of the contact region 15 provided on the upper surface of one second mesa portion 62 is larger than the area of the contact region 15 provided on the upper surface of one first mesa portion 60. The area of the contact region 15 provided on the upper surface of one second mesa portion 62 may be larger than the area of the contact region 15 provided on the upper surface of one third mesa portion 64. In the second mesa portion 62, the contact region 15 is also provided below the contact hole 54.
The contact region 15 on the upper surface of the second mesa portion 62 may be provided over the entire region sandwiched between the base regions 17 provided at both end portions of the second mesa portion 62 in the X-axis direction. In the second mesa portion 62, extraction of carriers at the time of turn-off is performed more efficiently than in the first mesa portion 60.
On the upper surface of the third mesa portion 64, contact regions 15 are provided at both ends in the X-axis direction. Further, on the upper surface of the third mesa portion 64, a base region 17 is provided in a region sandwiched between contact regions 15 provided at both end portions of the third mesa portion 64 in the X-axis direction. The base region 17 may be provided over the entire area sandwiched between the contact regions 15 in the X-axis direction. In the third mesa portion 64, the base region 17 is also provided below the contact hole 54. The contact region 15 may also be disposed below the contact hole 54.
In the third mesa portion 64, the contact region 15 and the base region 17 are formed from the dummy groove portion 30 on one side to the dummy groove portion 30 on the other side across the third mesa portion 64. That is, on the upper surface of the semiconductor substrate, the width of the third mesa portion 64 in the Y-axis direction is equal to the width of the contact region 15 or the base region 17 provided on the third mesa portion 64 in the Y-axis direction.
The emitter region 12 may not be formed in the third mesa portion 64, and the emitter region 12 may be formed. In this example, the emitter region 12 is not formed in the third mesa portion 64.
In the semiconductor device 200 of this example, the diode portion 80 is provided with the dummy groove portion 30. The respective linear extending portions 29 of the adjacent dummy groove portions 30 may be connected by a connecting portion 31. The third mesa portion 64 is a region sandwiched between the dummy groove portions 30.
The diode portion 80 has a cathode region 82 of the first conductivity type on the lower surface 23 side of the semiconductor substrate 10. For example, the cathode region 82 of this example is N + type. Fig. 8A shows a region where the cathode region 82 is provided in a plan view of the semiconductor substrate 10 by a one-dot chain line. The diode portion 80 may be a region obtained by projecting the cathode region 82 onto the upper surface 21 of the semiconductor substrate 10. The diode portion 80 may include the entire third mesa portion 64 in which the cathode region 82 is partially provided, and the dummy trench portion 30 adjacent to the third mesa portion 64. A region obtained by projecting the cathode region 82 onto the upper surface 21 of the semiconductor substrate 10 may be separated from the contact region 15 along the X-axis direction positive side.
In a region of the lower surface 23 of the semiconductor substrate 10 where the cathode region 82 is not formed, a collector region of the second conductivity type may be formed. As an example, the collector region of this example is P + -type. The collector region may be formed at a position where the negative side end portion of the contact hole 54 in the X-axis direction in the diode portion 80 is projected on the lower surface 23 of the semiconductor substrate 10.
In the transistor portion 70 except for the boundary portion 90, the contact hole 54 is formed above each region of the contact region 15 and the emitter region 12. In the first mesa portion 60 other than the first mesa portion 60 adjacent to the boundary portion 90, the contact hole 54 may be provided so as not to overlap the gate trench portion 40 and the dummy trench portion 30 extending in the X-axis direction in a plan view of fig. 8A. The width in the Y-axis direction of the contact hole 54 may be smaller than the width in the Y-axis direction of the emitter region 12 and the contact region 15.
In the transistor portion 70 except for the boundary portion 90, the contact hole 54 may be continuously provided from above the contact region 15 provided on the most negative side in the X-axis direction of the first mesa portion 60 to above the contact region 15 provided on the most positive side in the X-axis direction in the plan view of the semiconductor substrate 10 shown in fig. 8A. The contact hole 54 may be provided so as to overlap at least a part of the contact region 15 provided on the most negative side in the X-axis direction of the first mesa portion 60 in the plan view of the semiconductor substrate 10 shown in fig. 8A. The contact hole 54 may be provided so as to overlap at least a part of the contact region 15 provided on the most positive side in the X-axis direction of the first mesa portion 60 in the plan view of the semiconductor substrate 10 shown in fig. 8A.
In the boundary portion 90, the contact hole 54 is formed above the contact region 15. In the second mesa portion 62, the contact hole 54 may be provided so as not to overlap the dummy groove portion 30 extending in the X-axis direction in the plan view of the semiconductor substrate 10 shown in fig. 8A. The width in the Y-axis direction of the contact hole 54 may be smaller than the width in the Y-axis direction of the contact region 15.
In the boundary portion 90, the contact hole 54 may be provided continuously in the X-axis direction above the contact region 15 provided in the second mesa portion 62 in the plan view shown in fig. 8A. The contact hole 54 may be provided to overlap with at least a part of the contact region 15 provided at the second mesa portion 62 in the top view shown in fig. 8A.
In the diode portion 80, the contact hole 54 is formed above the base region 17 and the contact region 15. In the third mesa portion 64, the contact hole 54 may be provided so as not to overlap with the dummy groove portion 30 extending in the X-axis direction in the top view shown in fig. 8A. The width in the Y-axis direction of the contact hole 54 may be smaller than the width in the Y-axis direction of the base region 17 and the contact region 15.
In diode unit 80, contact hole 54 may be provided continuously from above contact region 15 provided on the most negative side in the X-axis direction of third mesa portion 64 to above contact region 15 provided on the most positive side in the X-axis direction in the plan view shown in fig. 8A. The contact hole 54 may be provided so as to overlap with at least a part of the contact region 15 provided on the X-axis direction negative side of the third mesa portion 64 in the plan view shown in fig. 8A. The contact hole 54 may be provided so as to overlap with at least a part of the contact region 15 provided on the X-axis direction positive side of the third mesa portion 64 in the top view shown in fig. 8A.
In the transistor portion 70, the accumulation region 16 of the first conductivity type may be provided below the base region 17. For example, the accumulation region 16 of this example is N + type. In fig. 8A, the range where the accumulation region 16 is formed is shown by a dotted line. The accumulation region 16 may be formed from a region where the contact region 15 at the end in the-X axis direction overlaps the contact hole 54 toward the + X axis direction side in a plan view of the semiconductor substrate. In the diode portion 80, the accumulation region 16 may not be provided, and the accumulation region 16 may be provided.
The semiconductor device 200 of this example has a crystal defect region 19 inside the semiconductor substrate 10. As shown in fig. 1A to 6, the semiconductor device 200 may have one or both of the crystal defect region 19-1 on the upper surface 21 side and the crystal defect region 19-2 on the lower surface 23 side. The semiconductor device 200 of this example has both crystal defect regions 19-1 and 19-2. The crystal defect region 19-2 may be provided in the entire transistor portion 70 and the entire diode portion 80. The crystal defect region 19-1 may be provided in the entire diode portion 80 and a part of the transistor portion 70.
In fig. 8A, a region where the crystal defect region 19-1 is provided is shown by a one-dot chain line and an arrow. In this example, crystal defect region 19-1 is arranged in the entire diode portion 80 in the XY plane and in a region not overlapping with gate trench portion 40 in transistor portion 70. The crystal defect region 19-1 may be provided continuously in the Y-axis direction from the diode portion 80 to the first mesa portion 60 adjacent to the gate trench portion 40 closest to the diode portion 80 in the transistor portion 70. In another example, the crystal defect regions 19-1 may be arranged discretely in the Y-axis direction so as not to overlap with the gate trench portions 40 in the transistor portion 70.
Fig. 8B is a diagram partially showing another example of the upper surface of the semiconductor device 200. In the semiconductor device 200 of this example, the arrangement of the crystal defect region 19-1 is different from that of the example of fig. 8A. The other structure is the same as the example of fig. 8A.
In semiconductor device 200 of this example, crystal defect region 19-1 is arranged so as to overlap gate trench portion 40 of transistor portion 70. More specifically, one or more gate trench portions 40, which are disposed closest to diode portion 80, of gate trench portions 40 of transistor portion 70 are disposed so as to overlap crystal defect region 19-1. The crystal defect region 19-1 may be arranged so as not to overlap at least the first mesa portion 60 arranged at the center in the Y axis direction in each gate trench portion 40 of the transistor portion 70.
Fig. 8C is a diagram partially showing another example of the upper surface of the semiconductor device 200. In the semiconductor device 200 of this example, the arrangement of the crystal defect region 19-1 and the cathode region 82 is different from that of the example of fig. 8A. The other structure is the same as the example of fig. 8A.
The crystal defect region 19-1 may be disposed in a larger range in the X-axis direction and the Y-axis direction than the cathode region 82. In fig. 8C, crystal defect region 19-1 is arranged in boundary portion 90 and diode portion 80 in the Y-axis direction, and is not arranged in transistor portion 70 other than boundary portion 90. The area of the contact region 15 exposed on the upper surface of the one second mesa portion 62 of the boundary portion 90 is larger than the area of the contact region 15 exposed on the upper surface of the one first mesa portion 60 of the transistor portion 70. The second mesa portion 62 may have a configuration in which the emitter regions 12 in the first mesa portion 60 are replaced with the contact region 15. The cathode region 82 is provided in the Y-axis direction in at least a part of the diode portion 80. In this example, a region sandwiched by the transistor portions 70 in the X-axis direction is set as the diode portion 80. In the diode portion 80, the cathode region 82 in fig. 8C is not provided on the one or more third mesa portions 64 closest to the boundary portion 90. The cathode region 82 of fig. 8C is provided in the diode portion 80 separately from the contact region 15 in the X-axis direction.
Further, the end portion of crystal defect region 19-1 in the X-axis direction is disposed between the end portion of cathode region 82 in the X-axis direction and gate metal layer 50. The end portion of crystal defect region 19-1 in the X-axis direction may be arranged between contact hole 54 and gate metal layer 50 (crystal defect region 19-1a in fig. 8C). In another example, the end portion of the crystal defect region 19-1 in the X-axis direction may be disposed between the dummy trench portion 30 and the gate metal layer 50 (the crystal defect region 19-1b in fig. 8C).
The end portion in the X-axis direction of the crystal defect region 19-1 may be located inside the well region 11 (the crystal defect region 19-1b in fig. 8C) in plan view. The doping concentration of the well region 11 of the P-type is higher than the doping concentration of the anode region 14 or the base region 17 of the P-type. By further disposing the crystal defect region 19-1 in the well region 11, injection of holes from the well region 11 toward the cathode region 82 can be suppressed.
An end portion of crystal defect region 19-1 in the Y axis direction may be located on first mesa portion 60 or dummy trench portion 30 on the diode portion 80 side of gate trench portion 40 provided on the side closest to diode portion 80 among gate trench portions 40 of transistor portion 70 (crystal defect region 19-1C in fig. 8C). This can suppress injection of holes from transistor portion 70 into cathode region 82 without affecting the gate threshold.
Crystal defect region 19-1 may extend in the Y-axis direction to gate runner 48 or gate metal layer 50. The end of crystal defect region 19-1 in the Y-axis direction may be located in gate runner 48, may be located in gate metal layer 50, or may be located beyond gate metal layer 50. This reduces carriers remaining in the gate runner 48 or the gate metal layer 50, thereby suppressing the influence on the switching operation.
Although the gate insulating film is formed on the lower surface 23 side of the gate runner 48 or the gate metal layer 50, it is also a region where an inversion layer channel is not formed. When ion implantation is performed to form the crystal defect region 19-1, the implanted ions are also introduced into or pass through the gate insulating film on the lower surface 23 side of the gate runner 48 or the gate metal layer 50. Therefore, damage may be formed in the gate insulating film during ion implantation. However, since no inversion layer channel is formed on the lower surface 23 side of the gate runner 48 or the gate metal layer 50, the influence on the gate threshold is sufficiently small.
The contact region 15 on the upper surface of the second mesa portion 62 may not be provided over the entire region sandwiched between the base regions 17 provided at both end portions of the second mesa portion 62 in the X-axis direction. Specifically, the contact region 15 on the upper surface of the second mesa portion 62 covers only both ends of the contact hole 54, and the base region 17 may be exposed on the upper surface of the second mesa portion 62 sandwiched by the contact region 15. The area of the exposed base region 17 on the upper surface of the second mesa portion 62 may be larger than the area of the contact region 15 covering both ends of the contact hole 54, and may be 10 times or more. The configuration may be the same as that of diode unit 80.
Fig. 8D is a diagram partially showing another example of the upper surface of the semiconductor device 200. In the semiconductor device 200 of this example, the arrangement of the cathode region 82 in the Y-axis direction is different from that of the example of fig. 8C. The other structure is the same as the example of fig. 8C. The position of the end portion in the Y-axis direction of crystal defect region 19-1 may be the same as the example of fig. 8C.
The cathode region 82 in this example is provided over the diode portion 80 in the Y-axis direction. Further, in the Y-axis direction, the crystal defect region 19-1 is provided in a partial region in the transistor portion 70 which is in contact with the diode portion 80. The crystal defect region 19-1 may be further provided in the first mesa portion 60 outside the boundary portion 90. However, the crystal defect region 19-1 is not provided within a predetermined range including the center in the Y-axis direction of the transistor portion 70. With this configuration, carriers can be prevented from flowing from the cathode region 82 to the upper surface side of the transistor portion 70.
Fig. 9A is a view showing an example of a section d-d' of fig. 8A. The d-d' cross section is a YZ plane passing through emitter region 12 and contact region 15 in transistor portion 70 and diode portion 80. The semiconductor device 200 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in a d-d' cross section. Emitter electrode 52 is provided on upper surface 21 of semiconductor substrate 10 and on the upper surface of interlayer insulating film 38.
The region a corresponds to the semiconductor device 100 shown in fig. 5. However, in the semiconductor device 100 shown in fig. 5, the dummy groove portion 30 and the interlayer insulating film 38 in fig. 9A are not provided. Further, the emitter electrode 52 in fig. 9A corresponds to the upper surface side electrode 53 in fig. 5.
The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a conductive material such as metal.
The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or the like. The semiconductor substrate 10 of this example is a silicon substrate.
The semiconductor substrate 10 includes a drift region 18 of a first conductivity type. The drift region 18 in this example is N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without providing other doped regions.
One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench portion is provided so as to penetrate the base region 17 from the upper surface 21 and reach the drift region 18.
The gate trench portion 40 has a gate trench provided on the upper surface 21, and a gate insulating film 42 and a gate conductive portion 44 provided in the gate trench. The gate insulating film 42 is provided so as to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding a semiconductor of an inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench at a position further inside than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.
The gate conductive portion 44 is provided inside the gate groove portion 40 so as to be surrounded by the gate insulating film 42. The gate conductive portion 44 includes a region facing at least the adjacent base region 17 with the gate insulating film 42 interposed therebetween in the depth direction. The gate groove portion 40 in the cross section is covered with the interlayer insulating film 38 on the upper surface 21. When a predetermined voltage is applied to the gate conductive portion 44, a channel composed of an inversion layer of electrons is formed in the surface layer of the interface of the base region 17 in contact with the gate trench.
The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy groove portion 30 has a dummy groove provided on the upper surface 21 side, and a dummy insulating film 32 and a dummy conductive portion 34 provided in the dummy groove. The upper end of the dummy trench may be at the same position as the upper surface 21 in the Z-axis direction. The dummy insulating film 32 is provided so as to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy groove portion 30 so as to be surrounded by the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.
The dummy conductive portions 34 may be formed of the same material as the gate conductive portions 44. The dummy conductive portion 34 is formed of a conductive material such as polysilicon, for example. The dummy conductive portions 34 may have the same length in the depth direction as the gate conductive portions 44. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross section) so as to protrude downward.
In the first mesa portion 60, the accumulation region 16 is provided above the drift region 18 so as to be in contact with the gate trench portion 40. In the case where a plurality of accumulation regions 16 are provided, the accumulation regions 16 are arranged in line in the Z-axis direction. As an example, the accumulation region 16 is N + type. The accumulation region 16 has a higher doping concentration than the drift region 18 and accumulates a dopant at a higher concentration than the drift region 18. By providing the accumulation region 16, it is possible to improve the carrier injection enhancement effect (IE effect) and reduce the on-voltage.
The accumulation region 16 may be in contact with the dummy groove portion 30 in the first mesa portion 60, but may be separated from the dummy groove portion 30. Fig. 9A shows an example in which the accumulation region 16 is provided in contact with the dummy trench portion 30.
In the first mesa portion 60, a base region 17 of the second conductivity type is provided above the accumulation region 16 so as to be in contact with the gate trench portion 40. For example, the base region 17 is N-type. In the first mesa portion 60, the base region 17 may be provided so as to be in contact with the dummy trench portion 30.
In the second mesa portion 62 of the boundary portion 90, the base region 17 of the second conductivity type is provided above the drift region 18 so as to be in contact with the dummy trench portion 30. In the third mesa portion 64 of the diode portion 80, the anode region 14 of the second conductivity type is provided above the drift region 18 so as to be in contact with the dummy trench portion 30. The anode region 14 is disposed in contact with the upper surface 21.
In the first mesa portion 60, the emitter region 12 is provided in contact with the upper surface 21 and in contact with the gate trench portion 40 in the d-d' cross section. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. In the first mesa portion 60, contact regions 15 are provided so as to contact the upper surface 21 and the gate trench portion 40 on the X-axis direction positive side and the X-axis direction negative side of the d-d' cross section.
In the second mesa portion 62, the contact region 15 is provided on the upper surface 21 so as to be adjacent to the dummy groove portion 30. The contact region 15 may be in contact with the dummy groove portion 30, but may be separated from the dummy groove portion 30. Fig. 9A shows an example in which the contact region 15 is provided in contact with the dummy groove portion 30.
In the transistor portion 70, a collector region 22 of the second conductivity type is provided below the drift region 18. For example, the collector region 22 in this example is of the P + type. The collector region 22 is arranged in contact with the lower surface 23. In the diode portion 80, a cathode region 82 of the first conductivity type having a higher doping concentration than the drift region 18 is provided below the drift region 18. For example, the cathode region 82 of this example is N + type. The cathode region 82 is disposed in contact with the lower surface 23.
In the semiconductor device 200 of this example, the semiconductor substrate 10 may have the buffer region 20 of the first conductivity type having a higher doping concentration than the drift region 18 between the drift region 18 and the lower surface 23 of the semiconductor substrate 10. The buffer 20 is disposed in a manner to include the first position Ps'. As an example, the buffer of this example is N + type. In this example, the buffer region 20 is provided in contact with the drift region 18.
The semiconductor device 200 of this example is provided with a hydrogen-containing region inside the semiconductor substrate 10. In the semiconductor device 200 of this example, the concentration distribution of hydrogen in the depth direction of the semiconductor substrate 10 has a peak of the concentration distribution at a first position Ps that is separated by a predetermined distance Dps in the depth direction of the semiconductor substrate 10 from the upper surface 21 that is one main surface of the semiconductor substrate 10.
In fig. 9A, the peak of the concentration distribution of hydrogen at the first position Ps is shown with an "x" symbol (mark). The first position Ps is arranged closer to the upper surface 21 than 1/2 of the thickness T of the semiconductor substrate 10. The semiconductor substrate 10 is provided with the high concentration region 26 as a region containing hydrogen implanted at the first position Ps. In the XY plane, the same range as the crystal defect region 19-1 shown in fig. 8A is set. That is, high concentration region 26 is provided in the XY plane over diode portion 80 and at least a part of a region of transistor portion 70 that does not overlap with gate trench portion 40.
In the semiconductor device 200 of this example, the concentration distribution of hydrogen has peaks at a plurality of positions in the buffer 20. That is, four positions, that is, the position Pb4, the position Pb3, the position Pb2, and the position Pb1 have peaks of concentration distribution from the upper surface side to the lower surface side of the buffer 20. Peaks of the concentration distribution of hydrogen at a plurality of positions in the Z-axis direction are shown with an "x" symbol (mark) in fig. 9A.
The buffer 20 of this example may be a region formed by annealing hydrogen injected from the lower surface 23 to the position Pb4, the position Pb3, the position Pb2, and the position Pb1 of the semiconductor substrate 10. The hydrogen is donated by annealing the hydrogen-implanted semiconductor substrate 10, thereby forming the buffer region 20 having a higher doping concentration than the drift region 18. Note that the formation of the buffer 20 will be described later.
The first position Ps may be a peak position of the doping concentration of the high concentration region 26 after annealing the hydrogen implanted semiconductor substrate 10. After annealing, the doping concentration at the first location Ps may be 1 × 1014(/cm3) Above and 1 × 1015(/cm3) The following.
In the semiconductor device 200 of this example, the buffer region 20 has a higher doping concentration than the drift region 18. Therefore, the buffer region 20 can function as a field stop region that prevents the depletion layer diffused from the lower surface sides of the anode region 14 and the base region 17 from reaching the cathode region 82 and the collector region 22.
In the semiconductor device 200 of this example, crystal defect regions 19-1 and 19-2 are provided. As shown in fig. 8A, crystal defect region 19-1 is provided in the entire diode portion 80 and at least a part of a region of transistor portion 70 that does not overlap with gate trench portion 40. The crystal defect region 19-2 may be provided in the XY plane over the diode 80 and over the transistor portion 70.
Fig. 9B is a view showing an example of a section d-d' of fig. 8B. The semiconductor device 200 of this example is different from the semiconductor device 200 shown in fig. 9A in the range in which the crystal defect region 19-1 and the high concentration region 26 are provided in the XY plane. The other structure is the same as the example shown in fig. 9A.
In this example, the crystal defect region 19-1 and the high concentration region 26 are provided in the XY plane over the diode portion 80 and a part of the transistor portion 70. In transistor portion 70, crystal defect region 19-1 and high concentration region 26 are provided in a region that is in contact with diode portion 80 and overlaps one or more gate trench portions 40.
Fig. 9C is a view showing an example of a section d-d' of fig. 8C. The semiconductor device 200 of this example is different from the semiconductor device 200 shown in fig. 9A in the range where the crystal defect region 19-1c and the high concentration region 26 are provided and the boundary position between the collector region 22 and the cathode region 82 in the XY plane. The other structure is the same as the example shown in fig. 9A.
Fig. 10A is a diagram illustrating an example of an outline of a method for manufacturing a semiconductor device according to the present embodiment. In this example, the crystal defect region 19-1 on the upper surface 21 side is formed by implantation of hydrogen ions (protons in this example), and the crystal defect region 19-2 on the lower surface 23 side is formed by implantation of helium ions. As an example, in the method of manufacturing the semiconductor device of this embodiment, as shown in fig. 10A, ion implantation into the lower surface 23 in step S1002 and laser annealing of the lower surface 23 in step S1004 are performed before proton implantation in step S1006 and thereafter.
In step S1002, the ions implanted into the lower surface 23 are, for example, B (boron) and P (phosphorus). In step S1002, boron and phosphorus are implanted into a region which is P-type and a region which is N-type in the lower surface 23, respectively, as an example.
In step S1004, laser annealing is performed on the boron and phosphorus implanted in step S1002. In step S1004, the collector region 22 is formed in the boron-implanted region, and the cathode region 82 is formed in the phosphorus-implanted region.
Next, protons are injected from the lower surface 23 in step S1006. The proton implantation in step S1006 may be performed a plurality of times as shown in step S1006-1, step S1006-2, step S1006-3, and step S1006-4. This example shows an example in which the proton implantation is performed four times in step S1006. In step S1006, protons are injected into the region where the buffer 20 should be formed.
In step S1008, the proton-implanted semiconductor substrate 10 is annealed at the second temperature. In this example, the second temperature may be 330 ℃ or higher and 450 ℃ or lower, and may be 370 ℃ as an example. Further, the second temperature may be 350 ℃ or higher and 420 ℃ or lower, and may be 370 ℃ or higher and 400 ℃ or lower. The annealing time in step S1008 may be 30 minutes or more and 10 hours or less, and in this example, 5 hours. Further, the annealing time in step S1008 may be 1 hour or more and 7 hours or less.
Next, helium ions are implanted from the lower surface 23 in step S1010. Further, protons are injected from the upper surface 21. Helium ions are implanted to a depth at which a defect density peak of the crystal defect region 19-2 should be formed. The protons are implanted to a position deeper than the region where the defect density peak of the crystal defect region 19-1 should be formed. The protons may be implanted to a depth at which the high concentration region 26 should be formed. Either one of the implantation of helium ions and the implantation of protons may be performed first.
In step S1012, the semiconductor substrate 10 implanted with protons and helium ions is annealed at a first temperature. The first temperature is lower than the second temperature. In this example, the first temperature may be 360 ℃.
The first temperature in step S1012 may be a temperature at which hydrogen ends dangling bonds contained in vacancies and double vacancies at and near the peak position Ps of the hydrogen ions injected in step S1010 (for example, in the region of FW 1%). The first temperature may be, for example, 300 ℃ or higher and 420 ℃ or lower, in this example 360 ℃. Further, the first temperature may be 330 ℃ or higher and 400 ℃ or lower, and may be 350 ℃ or higher and 380 ℃ or lower. Further, the first temperature may be less than 370 ℃ or 360 ℃ or less.
The annealing time in step S1012 may be shorter than the annealing time in step S1008. The annealing time in step S1012 may be 30 minutes or more and 8 hours or less, and in this example, 1 hour. Further, the annealing time in step S1012 may be 1 hour or more and 5 hours or less. By setting at least one of the annealing temperature and the annealing time in step S1012 to be lower than the annealing temperature and the annealing time in step S1008, crystal defects generated by implanting protons and helium ions are likely to remain. The semiconductor device shown in fig. 7B can be formed by such a process.
Further, after step S1012, an electrode forming step of forming an electrode toward the lower surface 23, not shown, may be performed. The electrode forming step includes a film forming step of forming one or more metal films. After the film formation step of the metal film, an electrode annealing step may be performed. The temperature of the electrode annealing step is lower than the first temperature. For example, the temperature may be 140 ℃ or higher and 330 ℃ or lower. The temperature of the electrode annealing step may be 220 ℃ or higher.
In addition, after the semiconductor device is diced to chip the semiconductor substrate, the semiconductor device may be soldered to a circuit board such as a DCB (Direct Copper Bond) substrate. The welding temperature at this time is set to the third temperature. The first temperature of the annealing in step S1012 is higher than the third temperature at the time of welding. For example, the temperature of soldering may be 280 ℃ to 400 ℃. Note that, if the third temperature is lower than the first temperature, the third temperature may be lower than the temperature of the electrode annealing step, may be the same as the temperature of the electrode annealing step, or may be higher than the temperature of the electrode annealing step.
Further, the time of welding may be 100 seconds or more and 500 seconds or less. The time of annealing in step S1012 may be longer than that of welding. Under such conditions, termination of crystal defects by hydrogen at the time of welding can be suppressed. The time for annealing in step S1012 may be 10 minutes or longer, or 30 minutes or longer. The annealing time may be 2 hours or less, or 1 hour or less. From the above description, if the second temperature is T2, the first temperature is T1, and the third temperature is T3, T2 > T1 > T3 is preferable.
Fig. 10B is a diagram illustrating another example of a method for manufacturing a semiconductor device. In this example, the crystal defect region 19-1 on the upper surface 21 side and the crystal defect region 19-2 on the lower surface 23 side are formed by proton implantation. Steps S1002 and S1004 of this example are the same as steps S1002 and 1004 shown in fig. 10A.
In step S1006, protons are injected from the lower surface 23. The proton implantation in step S1006 may be performed a plurality of times as shown in step S1006-1, step S1006-2, and step S1006-3. In step S1006, protons are injected to positions of hydrogen peaks other than one hydrogen peak among the plurality of hydrogen peaks that should be formed in the buffer 20. This example shows an example in which three times of proton implantation are performed in step S1006.
In step S1008, the proton-implanted semiconductor substrate 10 is annealed at the second temperature. In this example, the second temperature may be 370 ℃. The annealing time may be 5 hours.
Next, protons are implanted from the upper surface 21 and the lower surface 23 in step S1011. The protons are injected from the lower surface 23 to the position of the hydrogen peak where the protons were not injected in step S1006 among the plurality of hydrogen peaks to be formed in the buffer 20. Protons are implanted from the upper surface 21 to a position deeper than the region where the defect density peak of the crystal defect region 19-1 should be formed. Either one of the proton implantation from the upper surface 21 and the proton implantation from the lower surface 23 may be performed first.
In step S1012, the semiconductor substrate 10 implanted with protons and helium ions is annealed at a first temperature. Step S1012 is the same as step S1012 shown in fig. 10A. The semiconductor device shown in fig. 7A can be formed by such a process.
Fig. 11 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present embodiment. Fig. 11 is a diagram illustrating in detail step S1010 and step S1012 shown in fig. 10A. As shown in fig. 11, in step S1010, protons are implanted from the upper surface 21, which is one main surface of the semiconductor substrate 10, in the depth direction of the semiconductor substrate 10. In this example, protons are implanted to a depth of a first position Ps separated from the upper surface 21 by a distance Dps in the depth direction of the semiconductor substrate 10. In fig. 11, the protons injected to the depth of the first position Ps are shown by "x". In step S1010, the injection amount of protons may be 1 × 1012(/cm2) Above and 1 × 1013(/cm2) The following.
By the proton implantation from the upper surface 21, crystal defects are generated from the upper surface 21 of the semiconductor substrate 10 to the first position Ps. Further, the hydrogen concentration is distributed in the depth direction of the semiconductor substrate 10 with the first position Ps as a peak by proton implantation from the upper surface 21. Further, in step S1010, helium ions are implanted from the lower surface 23 in the depth direction of the semiconductor substrate 10. In this example, helium ions are implanted at the position Kb.
Next, in step S1012, the semiconductor substrate 10 into which the protons and the helium ions are implanted is annealed at the first temperature. The first temperature may be 360 ℃. The annealing time may be 1 hour. In step S1012, crystal defects generated by the implantation of protons and helium ions are terminated with hydrogen. Thereby, peaks of the crystal defect density are formed at the position Ks and the position Kb. Further, by this annealing, the hydrogen implanted into the first site Ps is donated.
The semiconductor device of this example uses the crystal defect region 19-1 distributed in the depth direction of the semiconductor device with the position Ks as the peak of the concentration distribution as the upper surface side lifetime control region 74. In addition, the semiconductor device of this example uses a region including the first site Ps where hydrogen is donated as the high concentration region 26.
Fig. 12 is a graph showing respective distributions of the hydrogen concentration (B), the crystal defect density (C), and the carrier concentration (F) along the line h-h' of fig. 11. In fig. 12, the distribution before annealing in step S1010 of fig. 11 is shown by a broken line, and the distribution after annealing in step S1012 is shown by a solid line.
As shown in the distribution graph (B), the hydrogen concentration is distributed with the first position Ps as a peak before annealing. The hydrogen is diffused by annealing, whereby the concentration distribution of hydrogen is expanded in the Z-axis direction. The distribution of the hydrogen concentration after annealing has a tail S of the concentration distribution in a region closer to the upper surface 21 than the first position Ps. The hydrogen concentration in the region closer to the upper surface 21 than the first position Ps is more gradually distributed than in the region closer to the lower surface 23 than the first position Ps.
As shown in the distribution chart (C), the distribution of the crystal defect density before annealing and the shape of the hydrogen concentration distribution before annealing were the same. For example, the peak position of the crystal defect density before annealing is the same as the peak position Ps of the hydrogen concentration before annealing. By annealing the semiconductor substrate 10, hydrogen is diffused in the Z-axis direction, and the dangling bonds are terminated. As described above, since a large amount of hydrogen exists in the vicinity of the peak of the hydrogen concentration, the crystal defects are substantially terminated in the vicinity of the peak position Ps.
The distribution graph (F) shows the distribution of the carrier concentration after annealing. The profile (F) is the same as a part of the profile (F) in fig. 7B. As shown in distribution diagrams (B) and (C), annealing is performed by implanting hydrogen ions from the upper surface 21 side, thereby forming the high concentration region 26 and forming the crystal defect region 19-1 in the region on the upper surface 21 side than the high concentration region 26.
Fig. 13 is a diagram illustrating another example of the method for manufacturing a semiconductor device according to the present embodiment. Fig. 13 is a diagram illustrating in detail step S1006, step S1008, step S1011, and step S1012 shown in fig. 10B.
As shown in fig. 13, the method for manufacturing a semiconductor device of this example includes a step of implanting protons a plurality of times so that the positions of the peaks of the hydrogen concentration distribution in the depth direction of the semiconductor substrate 10 are different. That is, in step S1006, protons are implanted from the lower surface 23, which is the other main surface of the semiconductor substrate 10, in the depth direction of the semiconductor substrate 10. In step S1006, protons are injected to positions of hydrogen peaks other than one hydrogen peak among the plurality of hydrogen peaks that should be formed in the buffer 20. In this example, in step S1006, protons are injected to the positions Pb4, Pb3, Pb1 in order. After the protons are implanted in step S1006, the semiconductor substrate 10 is annealed in step S1008. For example, the annealing temperature is 370 ℃ and the annealing time is 5 hours.
Next, in step S1011, protons are injected from the lower surface 23 to the position pb 2. Further, protons are injected from the upper surface 21 to the position Ps.
Next, in step S1012, the semiconductor substrate 10 is annealed. For example, the annealing temperature is 360 ℃ and the annealing time is 1 hour. Through step S1012, crystal defect region 19-1, crystal defect region 19-2, and high concentration region 26 are formed.
Fig. 14 is a diagram illustrating another example of the method for manufacturing the semiconductor device according to the present embodiment. The method for manufacturing the semiconductor device shown in fig. 14 is different from the method for manufacturing the semiconductor device shown in fig. 13 in that: protons are injected to the position Pb2 instead of the position Pb1 in step S1006 shown in fig. 13 and to the position Pb1 in step S1011. In this example, the peak position Kb of the crystal defect density 19-2 is located on the lower surface 23 side with respect to the position Pb 1. In this manner, the peak position Kb of the crystal defect density can be adjusted by adjusting the position at which protons are injected in step S1006 and step S1011.
Fig. 15 is a diagram illustrating another example of the outline of the method for manufacturing a semiconductor device according to the present embodiment. The method for manufacturing a semiconductor device of this example is different from the example of fig. 10B in that: there is an annealing step between the proton implantation step of implanting protons from the upper surface 21 and the proton implantation step of implanting protons from the lower surface 23 in step S1011 shown in fig. 10B. Steps S1002 to S1008 are the same as the example shown in fig. 10B.
In this example, in step S1011-1, protons are injected from the lower surface 23. After step S1011-1, annealing is performed in step S1012-1. The annealing temperature in step S1012-1 is lower than the annealing temperature in step S1008. The annealing time in step S1012-1 may be shorter than the annealing time in step S1008. The annealing is, for example, 360 ℃ for 1 hour.
Next, in step S1011-2, protons are injected from the upper surface 21. After step S1011-2, annealing is performed in step S1012-2. The annealing temperature in step S1012-2 is lower than that in step S1012-1. However, the annealing temperature in step S1012-2 is preferably higher than the bonding temperature in the die bonding process. The order of step S1011-1 and step S1011-2 may be changed.
Fig. 16 is a diagram illustrating a step of forming the crystal defect region 19 and the high concentration region 26 by implanting hydrogen ions (protons in this example) from the upper surface 21 side of the semiconductor substrate 10. The regions where protons are not implanted are covered by a mask 110 of photoresist or the like. The mask 110 may be disposed on the emitter electrode 52. The thickness T110 of the mask 110 is sufficiently large compared to the depth (range) of implanting protons into the semiconductor substrate 10. For example, when the range of protons is 8 μm, the thickness T110 is 33 μm or more.
In the step of implanting protons, hydrogen ions may be implanted at an acceleration energy at which a range from the upper surface 21 of the semiconductor substrate 10 is 8 μm or more. This enables the crystal defect region 19 to be formed at a position lower than the lower end of each trench portion. The acceleration energy of the proton may be 600keV or more, 1.0MeV or more, or 1.5MeV or more. This makes it possible to set the range of protons to 8 μm or more. In the case of an acceleration energy of 1.0MeV, the range of protons is, for example, about 16 μm. In the case of an acceleration energy of 1.5MeV, the range of protons is, for example, about 30 μm.
The acceleration energy of the proton may be 5.0MeV or more. In the case of an acceleration energy of 5.0MeV, the range of protons is, for example, about 215 μm. In this case, protons can be implanted to a deeper position. Even if protons are injected from the lower surface 23 side of the semiconductor substrate 10, protons can be injected near the lower end of the groove portion. Even before the step of polishing and thinning the lower surface 23 of the semiconductor substrate 10, protons can be injected from the lower surface 23 side of the semiconductor substrate 10 and injected to the vicinity of the lower end of the groove portion. After the protons are implanted from the lower surface 23 of the semiconductor substrate 10, the lower surface 23 of the semiconductor substrate 10 may be polished.
The acceleration energy of the proton may be 11.0MeV or less, or may be 5.0MeV or less. This can suppress the injection of protons into an excessively deep position. Further, protons can be suppressed from penetrating the semiconductor substrate 10. The acceleration energy of the proton may be 2.0MeV or less. In the case of an acceleration energy of 2.0MeV, the range of protons is, for example, about 47 μm.
In addition, the dose of protons may be 1.0 × 1012/cm2The above. Thereby, defects of sufficient density can be formed. In addition, the dose of protons may be 1.0 × 1015/cm2The following. Thus, even when protons are implanted from upper surface 21 at a range of, for example, 8 μm, the influence of the crystal defect density on anode region 14 or base region 17 can be suppressed.
Fig. 17 is a diagram illustrating a step of forming the crystal defect region 19 and the high concentration region 26 by implanting hydrogen ions (protons in this example) from the lower surface 23 side of the semiconductor substrate 10. The regions where protons are not implanted are covered by a mask 110 of photoresist or the like. The mask 110 may be disposed on the collector electrode 24. The thickness T110 of the mask 110 is sufficiently large compared to the depth (range) of implanting protons into the semiconductor substrate 10.
In the case where the mask 110 is an organic film such as a photoresist, if the implantation depth of hydrogen ions is X1(μm), the lower limit value Y1(μm) of the thickness T110 of the mask 110 may be the lower limit value Y1(μm) expressed by the following relational expression (expression 1) with respect to X1(μm).
(math formula 1)
Y1＝5.52317×(X1)0.79538
This enables the region covered with the mask 110 to sufficiently shield hydrogen ions. In the case where the mask 110 is an organic film such as a photoresist, if the acceleration energy at the time of ion implantation of hydrogen ions is E1(eV), the lower limit value Y2(μm) of the thickness T110 of the mask 110 may be the lower limit value Y2(μm) expressed by the following relational expression (expression 2) with respect to E1 (eV). As described above, the region covered with the mask 110 can sufficiently shield hydrogen ions.
(math figure 2)
Y2＝1.07515×10-11×(E1)2+3.83637×10-5×(E1)
As described above, the region covered with the mask 110 can sufficiently shield hydrogen ions.
In the step of implanting protons, hydrogen ions may be implanted with an acceleration energy such that the distance between the position of implantation of protons and the upper surface 21 of the semiconductor substrate 10 is 8 μm or more. The acceleration energy of the proton may be 2.0MeV or more, 3.0MeV or more, or 4.0MeV or more. By adjusting the acceleration energy, the high concentration region 26 can be formed on the upper surface 21 side of the semiconductor substrate 10. The high concentration region 26 may also be formed at the position of the accumulation region 16.
Fig. 18 shows the profile of the net doping concentration (a), the hydrogen concentration (B), the crystal defect density (C), the carrier lifetime (D), the carrier mobility (E), and the carrier concentration (F) in the depth direction in the semiconductor device 100 shown in fig. 17. As described above, the high concentration region 26 is formed by implanting hydrogen ions from the lower surface 23 of the semiconductor substrate 10 in this example.
As shown in the distribution diagram (a), the net doping concentration may have a concentration ratio concentration N up to a position Pf on the upper surface 21 side of the position Pb40A high region. From the lower surface 23 side to the position Ps, the hydrogen ions pass through the semiconductor substrate 10, and form crystal defects mainly composed of vacancies and double vacancies. Since the hydrogen concentration from the position Pb4 to the position Pf is sufficiently high, dangling bonds of crystal defects are terminated by hydrogen, forming hydrogen donors.
As shown in the distribution chart (B), the hydrogen concentration has a peak at the position Ps. The hydrogen concentration distribution in this example has a tail S from the peak position Ps toward one main surface (in this example, the lower surface 23). The hydrogen concentration between the location Ps and the location Pb4 may be higher than the hydrogen concentration in the anode region 14.
As shown in the distribution chart (C), the crystal defect density distribution has a peak at the position Ks. The crystal defect density distribution has a tail SV1 toward the lower surface 23 from the position Ks and a tail SV2 toward the upper surface 21. The trailing SV1 is gentler than the trailing SV2 in this example. Crystal defect density ratio concentration Nr0The high area is the area from position Pr to position Pf.
As shown in the distribution diagram (D), the carrier lifetime distribution has a peak at the position Ks. The carrier lifetime distribution has a tail S τ 1 from the position Ks toward the lower surface 23 and a tail S τ 2 toward the upper surface 21. The tail S.tau.1 is gentler than the tail S.tau.2 in this example. Carrier lifetime ratio τ0The low region is the region from position Pr to position Pf.
As shown in the distribution graph (E), the carrier mobility distribution has a peak at the position Ks. The carrier mobility distribution has a tail S μ 1 from the position Ks toward the lower surface 23 and a tail S μ 2 toward the upper surface 21. The tail S μ 1 is gentler than the tail S μ 2 in this example. Carrier mobility ratio mu0The low region is the region from position Pr to position Pf.
As shown in the distribution diagram (F), the carrier concentration distribution has a peak at the position Ks. The carrier concentration distribution has a tail SN1 from the position Ks toward the lower surface 23 and a tail SN2 toward the upper surface 21. The tail SN1 of this example is gentler than the tail SN 2. The tail SVs 1, S τ 1, S μ 1 and SN1 in this example may or may not reach the buffer 20.
The present invention has been described above with reference to the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes and modifications can be made in the above embodiments. The embodiments of the present invention may be modified or improved as described in the claims.
Note that the order of execution of the respective processes such as the actions, the sequence, the steps, and the stages in the devices, systems, programs, and methods shown in the claims, the description, and the drawings may be implemented in any order unless it is explicitly stated that "earlier than", "in advance", or the like, and further, a result of a process before a subsequent process is used is not a result of a subsequent process. In the operation flows in the claims, the description, and the drawings, even if the description is made using "first", "next", and the like for convenience, it does not mean that the operations are necessarily performed in this order.
The claims (modification according to treaty clause 19)
1. A semiconductor device is characterized by comprising:
a semiconductor substrate provided with a dopant of a first conductivity type;
a high concentration region having a doping concentration higher than a concentration of a dopant of the semiconductor substrate, and a hydrogen concentration distribution in a depth direction of the semiconductor substrate having a peak at a first position; and
a first crystal defect region provided at a position closer to the one main surface side of the semiconductor substrate than the high concentration region and having a central peak having a highest crystal defect density at a second position closer to the one main surface side than the first position,
the hydrogen concentration distribution of the semiconductor substrate in the depth direction has:
a first tail provided at a position closer to the one main surface side than the first position, and having a hydrogen concentration decreasing from the first position toward the one main surface; and
a second tail provided at a position closer to the other main surface side of the semiconductor substrate than the first position, the hydrogen concentration decreasing from the first position toward the other main surface steeper than the first tail,
the profile of the doping concentration in the depth direction has a first donor peak having a concentration lower than a hydrogen concentration at the first position.
2. The semiconductor device according to claim 1,
the crystal defect density distribution of the first crystal defect region has a third tail decreasing from the central peak toward the one major face in a region of the first tail.
3. The semiconductor device according to claim 1 or 2,
the semiconductor substrate includes:
a drift region of the first conductivity type provided so as to include the first donor peak; and
an anode region of a second conductivity type provided between the one main surface of the semiconductor substrate and the drift region,
the first crystal defect region includes the anode region.
4. The semiconductor device according to claim 3,
the crystal defect density of the anode region is less than half of the crystal defect density at the central peak.
5. The semiconductor device according to claim 4,
the crystal defect density of the anode region is the same as the minimum of the crystal defect density in the drift region.
6. The semiconductor device according to any one of claims 1 to 5,
the carrier mobility distribution in the depth direction has a mobility center peak at which the carrier mobility becomes minimum at the second position.
7. The semiconductor device according to any one of claims 3 to 5,
the carrier mobility distribution in the depth direction has a mobility center peak at which the carrier mobility becomes minimum at the second position,
the carrier mobility at the mobility center peak is smaller than the carrier mobility at the first donor peak, and is smaller than the carrier mobility of the drift region on the other principal surface side than the first donor peak.
8. The semiconductor device according to any one of claims 1 to 7,
the semiconductor substrate has a drift region of a first conductivity type provided so as to include the first donor peak,
the drift region closer to the one main surface side than the high concentration region has a higher doping concentration than the drift region closer to the other main surface side than the high concentration region.
9. The semiconductor device according to any one of claims 1 to 8,
in the first crystal defect region, a carrier concentration measured by a diffusion resistance measuring method is smaller than the doping concentration.
10. The semiconductor device according to any one of claims 3 to 5,
the semiconductor substrate has a buffer region of a first conductivity type having a higher doping concentration than the drift region between the drift region and the other main surface of the semiconductor substrate.
11. The semiconductor device according to claim 10,
a doping concentration profile in the depth direction of the buffer region has a plurality of doping concentration peaks,
the semiconductor device is further provided with a second crystal defect region having a central peak of the crystal defect density between two adjacent doping concentration peaks within the buffer region along the depth direction.
12. The semiconductor device according to claim 10,
the doping concentration profile of the buffer region has a plurality of doping concentration peaks,
the semiconductor device further includes a second crystal defect region having a central peak of a crystal defect density at a position closer to the other main surface side of the semiconductor substrate than a doping concentration peak located closest to the other main surface side among the plurality of doping concentration peaks of the buffer region.
13. The semiconductor device according to any one of claims 1 to 12,
the first crystal defect region is provided from the central peak of the first crystal defect region to the one main surface.
14. The semiconductor device according to any one of claims 1 to 13,
the doping concentration at the first location is 1 x 1014(/cm3) Above and 1 × 1015(/cm3) The following.
15. The semiconductor device according to any one of claims 1 to 14,
the semiconductor device includes:
a transistor portion provided with a collector region of a second conductivity type in a region in contact with the other main surface of the semiconductor substrate; and
a diode section provided with a cathode region of a first conductivity type having a higher dopant concentration than the dopant concentration of the semiconductor substrate in a region in contact with the other main surface of the semiconductor substrate,
the diode portion includes the first crystal defect region.
16. The semiconductor device according to claim 15,
the transistor portion includes the first crystal defect region.
17. The semiconductor device according to claim 16,
the transistor portion includes the first crystal defect region in a region in contact with the diode portion.
18. The semiconductor device according to any one of claims 15 to 17,
the semiconductor device further includes an edge termination structure portion disposed between an active portion and an outer peripheral end of the semiconductor substrate on an upper surface of the semiconductor substrate, the active portion being provided with the transistor portion and the diode portion,
the edge termination structure portion includes the first crystal defect region.
19. The semiconductor device according to any one of claims 1 to 18,
a distance between the peak of the hydrogen concentration distribution and the central peak of the first crystal defect region is 20 μm or less.
20. A method for manufacturing a semiconductor device, comprising:
implanting hydrogen ions from one main surface of a semiconductor substrate in a depth direction of the semiconductor substrate; and
and annealing the semiconductor substrate at a first temperature to reduce crystal defects generated at a position of a maximum hydrogen concentration of the hydrogen ion implantation, and to form a position where a defect density of the crystal defects generated by the hydrogen ion implantation is a maximum on the one principal surface side of the position of the maximum hydrogen concentration.
21. The method for manufacturing a semiconductor device according to claim 20, further comprising, before the step of implanting hydrogen ions in a depth direction of the semiconductor substrate from one main surface of the semiconductor substrate:
implanting hydrogen ions from the other main surface of the semiconductor substrate in a depth direction of the semiconductor substrate; and
and annealing the semiconductor substrate implanted with the hydrogen ions from the other main surface at a second temperature higher than the first temperature.
22. The method for manufacturing a semiconductor device according to claim 21,
the step of implanting hydrogen ions from the other main surface of the semiconductor substrate in the depth direction of the semiconductor substrate includes: and implanting the hydrogen ions a plurality of times so that positions of peaks of the concentration distribution of the hydrogen ions in the depth direction of the semiconductor substrate are different.
23. The method for manufacturing a semiconductor device according to any one of claims 20 to 22, further comprising:
a step of dicing the semiconductor substrate after the step of annealing at the first temperature; and
a bonding step of bonding the semiconductor substrate obtained by the formation of the chip to a circuit board at a third temperature,
the third temperature is lower than the first temperature.
24. The method for manufacturing a semiconductor device according to any one of claims 20 to 23, wherein in the step of implanting the hydrogen ions, the hydrogen ions are implanted at an acceleration energy at which a range from the one main surface of the semiconductor substrate is 8 μm or more.
25. The method for manufacturing a semiconductor device according to any one of claims 20 to 24, wherein an acceleration energy in the step of implanting the hydrogen ions is 1.0MeV or more.
26. The method for manufacturing a semiconductor device, according to claim 25, wherein the acceleration energy is 1.5MeV or more.
27. The method for manufacturing a semiconductor device according to any one of claims 20 to 24, wherein an acceleration energy in the step of implanting the hydrogen ions is 11.0MeV or less.
28. The method for manufacturing a semiconductor device, according to claim 27, wherein the acceleration energy is 5.0MeV or less.
29. The method for manufacturing a semiconductor device, according to claim 27, wherein the acceleration energy is 2.0MeV or less.
30. The method for manufacturing a semiconductor device according to any one of claims 20 to 29, wherein a dose of the hydrogen ions in the step of implanting the hydrogen ions is 1.0 x 1012/cm2The above.
31. The method for manufacturing a semiconductor device according to any one of claims 20 to 30, wherein the hydrogen ion implantation step is performed in the step of implanting hydrogen ionsThe dosage of hydrogen ions is 1.0X 1015/cm2The following.
Claims (25)
1. A semiconductor device is characterized by comprising:
a semiconductor substrate;
a hydrogen donor provided inside the semiconductor substrate in a depth direction, having a doping concentration higher than a doping concentration of a dopant of the semiconductor substrate, having a peak of a doping concentration distribution at a first position separated from the one main surface of the semiconductor substrate by a predetermined distance in the depth direction of the semiconductor substrate, and having a tail of the doping concentration distribution having a doping concentration smaller than the peak at a position closer to the one main surface side than the first position; and
and a crystal defect region having a central peak of a crystal defect density at a position closer to the one main surface side than the first position in a depth direction of the semiconductor substrate.
2. The semiconductor device according to claim 1,
the semiconductor substrate has:
a drift region of the first conductivity type provided so as to include the first position; and
and an anode region of a second conductivity type provided between the drift region and the one main surface of the semiconductor substrate.
3. The semiconductor device according to claim 2,
the semiconductor substrate has a buffer region of a first conductivity type having a higher doping concentration than the drift region between the drift region and the other main surface of the semiconductor substrate.
4. The semiconductor device according to claim 3,
the doping concentration profile of the hydrogen donor has donor peaks at a plurality of positions in the buffer region,
the crystal defect region has a central peak of a crystal defect density between a plurality of donor peaks of the hydrogen donor in a depth direction of the semiconductor substrate.
5. The semiconductor device according to claim 3,
the doping concentration profile of the hydrogen donor has donor peaks at a plurality of positions in the buffer region,
the crystal defect region has a central peak of a crystal defect density at a position closer to the other principal surface side of the semiconductor substrate than the plurality of donor peaks of the hydrogen donor in a depth direction of the semiconductor substrate.
6. The semiconductor device according to claim 4,
the crystal defect region is provided from the central peak to the one main surface in a depth direction of the semiconductor substrate.
7. The semiconductor device according to any one of claims 1 to 6,
the concentration distribution of the hydrogen donor has a doping concentration of 1 × 10 at the first position14(/cm3) Above and 1 × 1015(/cm3) The following.
8. The semiconductor device according to claim 2 or 3,
the semiconductor device includes:
a transistor portion in which a collector region of a second conductivity type is provided in a region in contact with the other main surface of the semiconductor substrate; and
a diode section having a cathode region of a first conductivity type provided in a region in contact with the other main surface of the semiconductor substrate and having a higher doping concentration than the drift region,
the diode portion includes the crystal defect region.
9. The semiconductor device according to claim 8,
the transistor portion includes the crystal defect region.
10. The semiconductor device according to claim 9,
the transistor portion includes the crystal defect region in a region in contact with the diode portion.
11. The semiconductor device according to any one of claims 8 to 10,
the semiconductor device further includes an edge termination structure portion disposed between an active portion and an outer peripheral end of the semiconductor substrate on an upper surface of the semiconductor substrate, the active portion being provided with the transistor portion and the diode portion,
the edge termination structure portion includes the crystal defect region.
12. The semiconductor device according to claim 2 or 3,
the distribution of the crystal defect density has a tail from the central peak toward the one main surface of the semiconductor substrate,
the crystal defect density of the anode region is less than half of the crystal defect density at the central peak.
13. The semiconductor device according to claim 12,
the crystal defect density of the anode region is the same as the minimum of the crystal defect density in the drift region.
14. A method for manufacturing a semiconductor device, comprising:
implanting hydrogen ions from one main surface of a semiconductor substrate in a depth direction of the semiconductor substrate; and
and annealing the semiconductor substrate at a first temperature to reduce crystal defects generated at a position of a maximum hydrogen concentration of the hydrogen ion implantation, and to form a position where a defect density of the crystal defects generated by the hydrogen ion implantation is a maximum on the one principal surface side of the position of the maximum hydrogen concentration.
15. The method for manufacturing a semiconductor device according to claim 14, further comprising, before the step of implanting hydrogen ions in a depth direction of the semiconductor substrate from one main surface of the semiconductor substrate:
implanting hydrogen ions from the other main surface of the semiconductor substrate in a depth direction of the semiconductor substrate; and
and annealing the semiconductor substrate implanted with the hydrogen ions from the other main surface at a second temperature higher than the first temperature.
16. The method for manufacturing a semiconductor device according to claim 15,
the step of implanting hydrogen ions from the other main surface of the semiconductor substrate in the depth direction of the semiconductor substrate includes: and implanting the hydrogen ions a plurality of times so that positions of peaks of the concentration distribution of the hydrogen ions in the depth direction of the semiconductor substrate are different.
17. The method for manufacturing a semiconductor device according to any one of claims 14 to 16, further comprising:
a step of dicing the semiconductor substrate after the step of annealing at the first temperature; and
a bonding step of bonding the semiconductor substrate obtained by the formation of the chip to a circuit board at a third temperature,
the third temperature is lower than the first temperature.
18. The method for manufacturing a semiconductor device according to any one of claims 14 to 17, wherein in the step of implanting the hydrogen ions, the hydrogen ions are implanted at an acceleration energy at which a range from the one main surface of the semiconductor substrate is 8 μm or more.
19. The method for manufacturing a semiconductor device according to any one of claims 14 to 18, wherein an acceleration energy in the step of implanting the hydrogen ions is 1.0MeV or more.
20. The method for manufacturing a semiconductor device, according to claim 19, wherein the acceleration energy is 1.5MeV or more.
21. The method for manufacturing a semiconductor device according to any one of claims 14 to 18, wherein an acceleration energy in the step of implanting the hydrogen ions is 11.0MeV or less.
22. The method for manufacturing a semiconductor device, according to claim 21, wherein the acceleration energy is 5.0MeV or less.
23. The method for manufacturing a semiconductor device, according to claim 21, wherein the acceleration energy is 2.0MeV or less.
24. The method for manufacturing a semiconductor device according to any one of claims 14 to 23, wherein a dose of the hydrogen ions in the step of implanting the hydrogen ions is 1.0 x 1012/cm2The above.
25. The method for manufacturing a semiconductor device according to any one of claims 14 to 24, wherein a dose of the hydrogen ions in the step of implanting the hydrogen ions is 1.0 x 1015/cm2The following.
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