CN1110951C - System controller in HDTV video decoder - Google Patents
System controller in HDTV video decoder Download PDFInfo
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- CN1110951C CN1110951C CN 98120073 CN98120073A CN1110951C CN 1110951 C CN1110951 C CN 1110951C CN 98120073 CN98120073 CN 98120073 CN 98120073 A CN98120073 A CN 98120073A CN 1110951 C CN1110951 C CN 1110951C
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Abstract
The present invention relates to a system controller in HDTV video decoders, which is characterized in that the system controller comprises a front unpacking unit (1), an audio-video synchronization circuit (2), an input buffer (3), an input buffer controller (4), a list memory (5), a data distributor (6), a back unpacking unit (7), a display control circuit (8), etc. The system controller divides an input PES stream into two parts that one is a PES head, a decode time sign/ display time sign (DTS/PTS) can be extracted from the PES head so as to restore image synchronization; the other part is image coding data which accords with standards of an MPEG-2MP@H-1440 class. The data is temporarily stored in the input buffer and is shifted out of the buffer in corresponding display time or decode time by frames, and the data is sent to a core decoder unit of a video decoder so as to encode out the image data.
Description
The present invention relates to a kind of HDTV Video Decoder, relate more specifically to the system controller in the HDTV Video Decoder.
Digital high-definition television (HDTV) is the radio data system of a new generation, be digital image processing techniques and very lagre scale integrated circuit (VLSIC) (VLSIC) technical development to the product of certain phase, the level of representing a national science and technology development is a big hot research field of International Technology circle in recent years.The picture quality of the brilliance that it provides can satisfy the visual characteristic of human eye better.Comprise many countries of China, carried out the research to high definition TV hardware implementation method one after another, wherein the U.S. successfully develops functional prototype of high definition TV.
System controller in the HDTV Video Decoder receives video Packet Elementary Stream (the being called for short PES stream) data from demodulation multiplexer, and its code stream form should meet MPEG-2 system layer standard.System controller resolves into two parts to the PES stream of input: a part is the PES head, can therefrom extract decode time sign/demonstration time tag (DTS/PTS), in order to recover image synchronization; Another part is the image coded data that meets the MPEG-2MP@H-1440 grade standard.This part data will be temporarily stored in the input buffer, and shift out buffer frame by frame in corresponding demonstration time or decode time, and the core decoder unit of delivering to Video Decoder is to solve view data.
The purpose of this invention is to provide the system controller in a kind of HDTV Video Decoder.
According to the system controller in a kind of HDTV Video Decoder of the present invention, it comprises: the preceding unit of unpacking, audio-visual synchronization circuit, input buffer, input-buffer controller, table memory, data distribution device, after unpack unit and display control circuit etc.; It is characterized in that:
Before the unit of unpacking receive the input of PES data, therefrom extract with system controller and realize the video heads information that control is relevant, and send the table memory to keep in this information; Before the unit of unpacking also produce first frame read output signal and give the input-buffer controller; Before the unit of unpacking basic flow data is delivered to input buffer;
After the unit of unpacking from the video data of input buffer output, extract the decoding parametric of core decoder necessity, and produce fast read signal and give the input-buffer controller;
Input buffer receives the basic flow data from the unit of preceding unpacking under the control of input-buffer controller, and video data is outputed to the data distribution device;
Respective frame is provided necessary control information for the input-buffer controller, and gives audio-visual synchronization circuit and display control circuit the information of current display frame for information about in the table memory stores input buffer;
The audio-visual synchronization circuit is judged the synchronous situation of decoding end audio/video according to the pts value of audio frequency current playback frame and the pts value of the current display frame of video, and to the input-buffer controller provide audio frequency leading/the video anticipating signal, indicate it to finish the synchronous adjustment of audio/video;
Display control circuit according on type that will display frame in the table memory and the input buffer/the underflow situation, realize control to the video Display Register, finish reordering of video sequence;
The data distribution device receives the video data from input buffer, and shunting rear push is to core decoder.
System controller in a kind of HDTV Video Decoder of the present invention is in the great scientific and technological industry engineering of State Scientific and Technological Commission " functional prototype of high definition TV system ", through the decoding and displaying checking, it can satisfy the requirement of handling video data stream in the high definition TV well.
Fig. 1 is a basic operation schematic diagram of explaining input buffer in the HDTV Video Decoder;
Fig. 2 explains the schematic diagram of determining the overflow thresholding of input buffer in the HDTV Video Decoder;
Fig. 3 is a schematic diagram of explaining the frame-skipping processing of input buffer in the HDTV Video Decoder;
Fig. 4 is the block diagram of a kind of embodiment of the system controller in the HDTV Video Decoder of the present invention.
Key technology below with reference to Fig. 1-3 pair system controller describes.It comprises: the processing of unpacking, input-buffer management, audio/video are synchronously and the control of video display buffer.
1. the processing of unpacking
Unpack and mainly comprise: tear the PES bag open and tear video heads two parts open.Tearing the PES bag open mainly is in order to extract different information such as code check, timing and data description from the PES head, therefrom to isolate the video-frequency basic flow data simultaneously.Tearing video heads open is in order to extract each video heads information, to be correctly decoded the decoding parametric that provides necessary for core decoder.
Because the structure of PES bag and each video heads is all fixed according to the regulation of mpeg standard, therefore unpacking to handle is called the fixed length decoding again.The key that realizes it is how to find corresponding initial code quickly and accurately.Then, just can code stream really allocation extract needed PES header and video heads information.
With reference to the pertinent regulations of advanced television system committee (be called for short ATSC) about Digital Television: " payload of the video PES bag that transmits in the HDTV system is made up of piece image (or video access units); its first byte or be the initial code of image sequence; or be the initial code of image sets, or be the initial code of image." therefore, find corresponding initial code also just to find the payload of PES bag, promptly isolated the video-frequency basic flow data.
2. input-buffer management
The input-buffer management is one of control technology the most complicated in the mpeg decode system, and it mainly is that the overflow of input buffer and underflow situation are managed (see figure 1).
Under normal conditions, input buffer overflows or underflow never.Yet, for an actual decoder, when the data flow of input, will not overflowed or underflow when unequal in strict accordance with the input rate of mpeg standard correct coding or input buffer and output speed.The basic operation of input buffer is (annotate: for convenience of explanation, reading of buffer is idealized as instantaneous finishing among the figure, and read operation will be taken time in the practical application, below each figure in like manner) as shown in Figure 1.
Among Fig. 1, A is a frame data amount size; B is the data volume that writes buffer in the frame time; C is the frame period; R is an input bit rate.
(1) the overflow thresholding determines
Because overflowing of data can cause irremediable loss to view data, so must avoid the generation of overflowing.Method is to formulate an overflow thresholding, when data volume surpasses threshold value, judges that overflow has taken place buffer.After overflow took place, the control buffer was skipped present frame, calls over next frame, even following frame, to guarantee having enough spaces to store the data of back input in the buffer.
Comprise three kinds of frame types in the video sequence of HDTV: I frame (intracoded frame), P frame (forward predicted frame) and B frame (bi-directional predicted frames).I, P frame are as the reference frame, and its decoding that is correctly decoded for each P frame of postorder or B frame all can exert an influence, and the B frame only is related to it oneself.Therefore, when buffer generation overflow, frame-skipping should can not be jumped in line with the I frame, and the P frame is not jumped as far as possible, the principle that the B frame can be jumped.
Again because I frame or P frame data amount are all bigger usually, greater than writing the data in buffer amount in the frame time.The speed that the while buffer is read is far longer than the speed of writing again, so when I frame or P frame generation overflow, even normally read, also can not overflow, if overflow has taken place the B frame, for fear of overflowing, then must frame-skipping handle.
Therefore, according to the real work situation of buffer, under the prerequisite that the supposition buffer does not overflow just, as shown in Figure 2, the overflow thresholding computing formula that draws is:
Overflow thresholding=heap(ed) capacity-input bit rate * frame period+B frame minimum data amount (unit: megabit)
B among Fig. 2
*Be B frame minimum data amount; C is the frame period; R is an input bit rate.
(2) judgement and the countermeasure of last underflow
Judge the situation that goes up underflow, will the full scale of buffer be detected.In the appendix C of mpeg standard, stipulate, after and finishing before each read operation is carried out, buffer is detected.But find by calculating, read the back detection and there is no need for Video Decoder.Reason has two: the first, read the overflow threshold value that detects the back should with read before detect different, in side circuit, read operation needs the time in the buffer, because the data volume of every two field picture is not of uniform size, so the interval between every frame read operation zero hour is just uncertain, and determining of threshold value is closely-related with this time interval, determines that therefore the overflow thresholding of reading to detect the back almost is impossible; Second: detection has the ability to prevent the generation that buffer overflows fully before reading.
Before each read operation, the full scale of buffer is detected.Full scale is to be determined by buffer write address and the difference of reading the address.When full scale surpasses the overflow threshold value, judge that overflow has taken place buffer, to the processing of overflow be: skip present frame, and before calling over next frame, detect the full scale of buffer again, if be lower than the overflow threshold value, then read next frame; If still be higher than the overflow threshold value, then skip present frame again, prepare to read down frame down, by that analogy, till sinking to reading next frame.It should be noted that overflow is handled just current just carries out will read frame and be the B frame time, as shown in Figure 3.In the detection before reading, as finding neither one whole frame in buffer this moment, then underflow has taken place at this moment in explanation.During underflow, should repeat to show previous frame decoded picture (see figure 3).
(3) first frame readout time determines
In the MPEG02 standard, vbv_delay value in each frame image head and the PTS/DTS value in the PES head are all stipulated the time that view data goes out buffer.Because the time interval among the HDTV between each two field picture is fixed, and is 40 milliseconds, just can calculate out as long as therefore know the correct time that first frame is read, the readout time of each frame of postorder.
Because use PTS/DTS value, must advance clock (can recover out) with the local system of decoding end and match, so adopt the method for the definite first frame of vbv_delay value readout time more convenient, faster by PCR.
3. audio/video is synchronous
Usually realize that the synchronous mode of audio/video has two kinds: a kind of is to be benchmark with the video, adjusts audio-visual synchronization by the method for repetition or jumping audio frame; Otherwise another kind then, is benchmark with the audio frequency, by the frame of video frame-skipping is finished with repeating to show.Consider that the change frame of video can obviously not influence display effect, the general a kind of method in back that adopts.
The definition of PTS/DTS is to come according to System Target Decoder (STD) model in the mpeg standard.And STD is the Mathematical Modeling of a true decoder, it is idealized as instantaneous finishing to decoder to the operation of code stream, and in actual decode system, the Voice ﹠ Video decoder all can not instantaneous finishing to the operation of data, buffer is read the decoding of will taking time and will be taken time, demonstrate and will take time, these time-delays can also should not be left in the basket.And because the size of audio frame and video requency frame data amount has significant difference, corresponding time-delay also differs widely, and it is very complicated to consider to get up, and this just brings very big difficulty for decoding end realizes audio-visual synchronization.
For the simplification problem, be convenient to the synchronous realization of audio/video, the strategy that can take is: the pts value that guarantees current frame of display video is consistent with the PTS of current playback audio frame, can guarantee that just the decoding end audio/video is synchronous.
4. display buffer control
For video sequence, its input sequence is different with showing.The task of display buffer is exactly reordering of video sequence, and the control of the display buffer of system controller is exactly that the indicated number buffer is rinsed new which frame and deposited, and the data output which frame is deposited shows, to finish the function that reorders.
Because the control of display buffer is relevant with the type of coding of want display frame, if input buffer generation frame-skipping or repeat to show previous frame, then display buffer is controlled out and will be adjusted accordingly, again because frame-skipping and repeat to show do not have a rule, therefore, the realization of display buffer control is implemented according to the concrete condition of current display frame.
Below with reference to Fig. 4 most preferred embodiment of the present invention is described.System controller in a kind of HDTV Video Decoder of the present invention comprises: the preceding unit 1 of unpacking, audio-visual synchronization circuit 2, input buffer 3, input-buffer controller 4, table memory 5, data distribution device 6, after unpack unit 7 and display control circuit 8 etc.
Unpack handle unpack before being divided into and after the two parts of unpacking.
Before unpack unit 1 receive the input of PES data, the process of unpacking before PES is carried out: extract with system controller and realize the video heads information (as the type of coding of frame of video) that control is relevant, and send table memory 5 to keep in; Before the unit 1 of unpacking also produce first frame read output signal and give input-buffer controller 4.Before the unit 1 of unpacking basic flow data is delivered to input buffer 3.
After the unit 7 of unpacking from the video data of input buffer 3 output, extract the decoding parametric of core decoder necessity, and produce fast read signal and give input-buffer controller 4.
Input buffer 3 receives the basic flow data from the unit of preceding unpacking under the control of input-buffer controller, and video data is outputed to data distribution device 6.
Because the quantity difference of different coding frame can show with constant rate of speed in order to guarantee decoded image, system controller needs a buffer to realize the buffer memory of data in the HDTV Video Decoder, Here it is input buffer 3.
For in a time in frame period, can read buffer memory to frame data smoothly, the coded data of input before writing input buffer 3, earlier through also conversion of string, the read-write that makes input buffer at be parallel data.So not only improve the speed of reading and writing data, also improved the reliability of reading and writing data.
Concerning input buffer 3, write operation is continuous, and read operation is interrupted, and read-write operation might clash.For fear of the generation of conflict, but the read-write operation timesharing of input buffer is carried out.
Design for convenience, unpack after the assurance and can adopt identical structure with before unpacking, require the read operation of input buffer to have two cover sequential: a cover is read sequential slowly, make the parallel data of reading from input buffer, speed is identical with the serial data rate of input system controller after also string is changed, with the operate as normal of unpacking after guaranteeing; Another set of is to read sequential soon, with the fastest speed the data in the input buffer is read.
The input-buffer management is finished jointly by input-buffer controller 4 and table memory 5.The first frame read output signal that input-buffer controller 4 is sent here according to the unit 1 of before unpacking recovers the frame synchronization of Video Decoder, and specified data time of reading from input buffer 3 thus; According to after unpack that unit 7 sends here read commencing signal soon, finish input buffer 3 fast/read slowly to switch; According to the full scale situation of current input buffer 3, judge whether it overflow or underflow take place, and take measures areput one frame-skipping or repeat to show a last decoded frame; According to the audio frequency of audio-visual synchronization circuit 2 leading/the video anticipating signal carries out respective handling, processing method is identical with the processing method of last/underflow.
Respective frame for information about in the table memory 5 storage input buffers, as pts value, frame type of coding etc., in order that necessary control information is provided for input-buffer controller 4, and gives audio-visual synchronization circuit 2 and display control circuit 8 information of current display frame.
Audio-visual synchronization circuit 2 is to judge the situation that the decoding end audio/video is synchronous according to the pts value of the pts value of audio frequency current playback frame and the current display frame of video, and to input-buffer controller 4 provide audio frequency leading/the video anticipating signal, indicate it to finish the synchronous adjustment of audio/video.
Display control circuit 8 be according on type that will display frame in the table memory 5 and the input buffer 3/the underflow situation, realize control to the video Display Register, finish reordering of video sequence.
Because hardware process speed does not reach, the core decoder of HDTV Video Decoder can only adopt parallel organization, therefore will be by the data of input buffer output through shunting, all assign in each daughter nucleus heart decoder and go to finish decoding, data distribution device 6 is finished this function, it receives the video data from input buffer 3, and shunting rear push is to core decoder.
Claims (1)
1. system controller is characterized in that it comprises: the preceding unit of unpacking (1), audio-visual synchronization circuit (2), input buffer (3), input-buffer controller (4), table memory (5), data distribution device (6), after unpack unit (7) and display control circuit (8) etc.;
Before the unit (1) of unpacking receive the input of PES data, therefrom extract with system controller and realize the video heads information that control is relevant, and send table memory (5) to keep in this information; Before the unit (1) of unpacking also produce first frame read output signal and give input-buffer controller (4); Before the unit (1) of unpacking basic flow data is delivered to input buffer (3);
After the unit (7) of unpacking from the video data of input buffer (3) output, extract the decoding parametric of core decoder necessity, and produce fast read signal and give input-buffer controller (4);
Input buffer (3) receives the basic flow data from the unit of preceding unpacking (1) under the control of input-buffer controller (4), and video data is outputed to data distribution device (6);
Respective frame is provided necessary control information for input-buffer controller (4), and gives audio-visual synchronization circuit (2) and display control circuit (8) information of current display frame for information about in table memory (5) the storage input buffer (3);
Audio-visual synchronization circuit (2) is judged the synchronous situation of decoding end audio/video according to the demonstration time tag value of audio frequency current playback frame and the demonstration time tag value of the current display frame of video, and to input-buffer controller (4) provide audio frequency leading/the video anticipating signal, indicate it to finish the synchronous adjustment of audio/video;
Display control circuit (8) according on type that will display frame in table memory (5) and the input buffer (3)/the underflow situation, realize control to the video Display Register, finish reordering of video sequence;
Data distribution device (6) receives the video data from input buffer (3), and shunting rear push is to core decoder.
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| CN 98120073 CN1110951C (en) | 1998-10-06 | 1998-10-06 | System controller in HDTV video decoder |
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| CN 98120073 CN1110951C (en) | 1998-10-06 | 1998-10-06 | System controller in HDTV video decoder |
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| CN1110951C true CN1110951C (en) | 2003-06-04 |
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| CN1306819C (en) * | 2004-07-30 | 2007-03-21 | 联合信源数字音视频技术（北京）有限公司 | Video frequency decoding control method and device |
| CN101072371B (en) * | 2006-05-11 | 2011-05-04 | 创视科技股份有限公司 | Video signal generating device |
| CN101500158B (en) * | 2008-12-26 | 2013-10-16 | 深圳市同洲电子股份有限公司 | Visible interphone and audio/video data transmission method and system |
| CN101931775A (en) * | 2010-09-01 | 2010-12-29 | 中兴通讯股份有限公司 | Video recording method and device |
| CN107911714B (en) * | 2017-11-28 | 2019-11-26 | 北京数码视讯科技股份有限公司 | Code stream method for splitting, device and bit stream equipment |
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